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Adv. Radio Sci., 7, 191–196, 2009 www.adv-radio-sci.net/7/191/2009/ © Author(s) 2009. This work is distributed under the Creative Commons Attribution 3.0 License. Advances in Radio Science Impact of negative and positive bias temperature stress on 6T-SRAM cells S. Drapatz1,2 , G. Georgakos2 , and D. Schmitt-Landsiedel1 1 Lehrstuhl 2 Infineon für Technische Elektronik, Technische Universität München, Germany Technologies AG, München-Neubiberg, Germany Abstract. With introduction of high-k gate oxide materials, the degradation effect Positive Bias Temperature Instability (PBTI) is starting to play an important role. Together with the still effective Negative Bias Temperature Instability (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event. 1 Introduction The ongoing miniaturization in semiconductor industry has already led to decananometer transistors (ITRS roadmap). As the voltage cannot be scaled according to geometry and gate oxides are getting thinner, electric fields and tunneling currents in the devices are increasing. This was exacerbating Negative Bias Temperature Instability (NBTI) and leakage in the past years. In order to reduce these harmful effects (especially leakage), thicker gate oxide materials are needed. To keep the ability to store charges and control the MOSFET channel, the dielectric constant must then be higher than in conventional SiO2 . This is done with the introduction of high-k gate oxide materials. One disadvantage of these new materials is an upcoming effect similar to NBTI: Positive Bias Temperature Instability (PBTI), which occurs predominantely on nMOS transistors, while NBTI is effective mainly on pMOS transistors. In the Correspondence to: S. Drapatz ([email protected]) past, NBTI alone fortunately did not have huge impact on the SRAM memory cell performance (Fischer et al., 2007). But does the additional effect PBTI together with the still effective NBTI have a significant influence on SRAM core cell performance? The following section gives a brief overview on the degradation mechanisms NBTI and PBTI. To quantitatively measure the influence of these effects on the SRAM 6T core cell, a benchmark is required. This is done with some metrics to describe the quality of the memory cell, introduced in Sect. 3. Using these metrics, the impact of NBTI and PBTI on SRAM is simulated in Sect. 4. Next, it is examined to what extent normal usage of the memory cell, i.e. hold, read and write, leads to BTI stress conditions of the single transistors. The worst use case will then be isolated and considered in the last section separately together with variation and yield considerations. 2 NBTI and PBTI In this section, both degradation effects Negative Bias Temperature Instability and Positive Bias Temperature Instability are introduced. 2.1 NBTI degradation NBTI is an effect only influencing pMOS transistors. It is caused by the following scenario: negative potential at the gate relative to higher potentials on source and drain. For standard CMOS circuits this means gate connected to VSS , source and drain connected to VDD . This leads to a conducting transistor without current in the channel (Fig. 1). The failure mechanism NBTI is still under discussion, but it seems to be clear that the stress condition breaks siliconhydrogen bonds, and the hydrogen ions diffuse away. These vacant positions, acting as traps, can bond holes. These additional holes in the gate oxide cause a decreasing threshold Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V. 192 2 NBTI the stress condition is contrary to NBTI: positive potential on the gate, zero potential on source and drain. This lets the threshold voltage drift to higher values, so both NBTI and Drapatz et Impact NBTI PBTI 6T-SRAM cells S.S.Drapatz al.:al.: Impact of of NBTI andand PBTI on on 6T-SRAM Cells PBTI et weaken the devices over time (Fig. 2). In summary, Vth,deg Vth −IDS degraded −IDS NBTI the stress condition is contrary to NBTI: positive potential on the gate, zero potentialIon source and drain. This lets the DS threshold voltage drift to higher values, so both NBTI and non−degraded PBTI weaken the devices over time (Fig. 2). In summary, PBTI Vth,deg Vth non−degraded NBTI degraded −VGS NBTI non−degraded Fig. 1. Stress conditions and impact of NBTI to pMOS transistors −VGS sistor is getting slower (Fig. 1). Typical threshold voltage Fig. 1.values Stress in conditions and impact of after NBTI 8to years pMOSof transistors drift 65nm technology: stress at 1. Stress conditions and impact of NBTI to pMOS transistors VFig. DD,nom and 125°C there will be a mean drift value of approx. 60mV. voltage, e.g. from −0.5 V it goes down to −0.55 V. This sistor isthegetting slower (Fig.over 1). time, Typical makes transistor weaker andthreshold a circuitvoltage built of 2.1.1 NBTI distribution drift values in 65nm technology: after 8 years of threshold stress at this transistor is getting slower (Fig. 1). Typical VDD,nom 125°Cin there willThere be a mean drift value of voltage values 65 nm technology: after 8 years of NBTI is drift a and statistical process. is a distribution of apsinprox. 60mV. ◦ stress at values, VDD,nombut and C there will mean gle drift the125 simulation toolsbesoafar candrift onlyvalue hanof approx. 60 mV. dle and predict the mean value of this distribution. Analyses 2.1.1 NBTI distribution have shown that a stress of 10.000 seconds at 125°C lets the 2.1.1 value NBTI distribution mean drift for process. approx. 45mV, buta single devices have NBTI is a statistical There is distribution of sinshown a drift of up to 150mV (Fischer et al., 2007). Espegle drift but the simulation tools far can onlyofhanNBTI is values, a statistical process. There is asodistribution sincially forpredict SRAMthe with a huge cells in an Analyses array, this dle and mean valuenumber of this of distribution. gle drift values, but the simulation tools so far can only hanmeans that single will experience big drifts. have shown that a memory stress of cells 10.000 seconds at 125°C lets the dle and predict the mean value of this distribution. Analyses mean value drift for approx. 45mV, but single devices have have shown that a stress of 10 000 s at 125◦ C lets the mean 2.1.2 shown NBTI a drift annealing of up to 150mV (Fischer et al., 2007). Espevalue drift for approx. 45 mV, but single devices have shown cially for SRAM with a huge number of cells in an array, this a drift of up toNBTI 150 mV (Fischer et al., 2007). for Additionally, shows a recovery effect: Especially directly means that single memory cells will experience big drifts.after SRAM with athe huge numbervoltage of cellsdrift in anisarray, end of stress, threshold worst,this butmeans is anthat memory will experience big drifts. nealing with aannealing short cells time constant, depending on the duration 2.1.2single NBTI of the stress (Reisinger et al., 2007). This means that for a 2.1.2 annealing Additionally, NBTI showstoa work recovery directly afterof circuit itNBTI would be worst witheffect: this high amount end of stress, the threshold voltage drift is worst, is an-If threshold voltage drift during or very shortly afterbut stress. Additionally, shows a recovery effect:on directly after nealing with a NBTI short time constant, depending the duration the circuit only experiences the annealed drift values, the imend of stress, the threshold voltage drift is worst, but is of the stressbe(Reisinger 2007). This means that strong forana pact would much less.etItal., is not analysed so far how nealing with a short time constant, depending on the duration circuit it would worst tothe work with circuits. this high amount of relaxation effectsbeinfluence SRAM of the stress (Heinrigs et al., or 2007). This means that forIfa threshold voltage drift during very shortly after stress. circuit it would be worst to work with this high amount the circuit only experiences the annealed drift values, the im-of 2.2 Expected PBTI degradation threshold drift during or very shortly after stress. pact wouldvoltage be much less. It is not analysed so far how strongIf the circuittoonly experiences theSRAM annealed drift values, imrelaxation effects influence the circuits. Contrary NBTI that is relatively well-known in thethe meanpact would much less. Itresearched is not analysed far how strong time, PBTI be was not much in thesopast. Many parelaxation effects influence the 2.2 are Expected PBTI degradation pers available for NBTI, butSRAM PBTI iscircuits. just coming up. The reason is clear: up to now, it did not occur on semiconductor 2.2 Expected PBTI Contrary to NBTI that degradation is relatively well-known in the meanchips without high-k gate oxide. time, PBTI was not much researched in the past. Many paOnly withtothe introduction of thesewell-known new materials, themeanPBTI Contrary NBTI thatNBTI, is relatively in the pers are available for but PBTI is just coming up. The effect appears. This is because NBTI is based on traps for time, wasup nottomuch in the Many pareasonPBTI is clear: now, itresearched did not occur on past. semiconductor holes, which only happens at the interface states. PBTI, howpers available for gate NBTI, but PBTI is just coming up. The chipsare without high-k oxide. ever, is based on electron trapping, which reason is clear: up to now, it notnew occur onmainly semiconductor Only with the introduction ofdid these materials, thehappens PBTI in high-k bulk as well as in high-k SiON interfacial chips gate oxide.NBTI is based on trapslayer. effect without appears.high-k This is because for PBTI only works nMOSattransistors, according that Only with the on introduction theseand new materials, the holes, which only happens theof interface states. PBTI, to howPBTI effect appears. This istrapping, because which NBTI mainly is basedhappens on traps ever, is based on electron in high-k wellhappens as in high-k interfacial for holes, bulk whichasonly at theSiON interface states. layer. PBTI, PBTI onlyisworks transistors, and according to that however, basedononnMOS electron trapping, which mainly happens in high-k bulk as well as in high-k SiON interfacial Adv. Radio Sci., 7, 191–196, 2009 PBTI IDS degraded non−degraded PBTI Vth Vth,deg VGS PBTI degraded Fig. 2. Stress conditions and impact of PBTI to nMOS transistors. Fig. 2. Stress conditions and impact of PBTI to nMOS transistors Vth Vth,deg GS PBTI isPBTI not yet good on analyzed NBTI, butand theVaccordbehavlayer. onlyasworks nMOS as transistors, ior seems to be very similar (Zafar et al., 2006). Within the ing to that the stress condition is contrary to NBTI: positive scope of this work, we therefore assume the PBTI threshold potential onconditions the gate, and zeroimpact potential on source andtransistors drain. This Fig. 2. Stress of PBTI to nMOS voltage drift to behave NBTI in terms of absolute value, lets the threshold voltagelike drift to higher values, so both NBTI distribution and annealing. and PBTI the devices overastime (Fig. PBTI is notweaken yet as good analyzed NBTI, but2).the behavIn summary, PBTI is not(Zafar yet asetgood analyzed as NBTI, ior seems to be very similar al., 2006). Within the but the to be very similar al., 2006). scope of behavior this work,seems we therefore assume the(Zafar PBTIetthreshold 3 Modeling and Metrics Within the scope of SRAM this we assume the PBTI voltage drift to behave likework, NBTI intherefore terms of absolute value, threshold voltage drift to behave like NBTI in terms of absodistribution and annealing. For modeling, we use the following approach: ∆Vth together lute value, distribution and annealing. with SensitivitySRAM results in Degradationperf ormance transistor parameter drift ∆Vth is the direct result of 3 The Modeling and SRAM Metrics the NBTI and PBTI effects, as described in the previous 3 Modeling and SRAM metrics section. Together the sensitivity of the circuit For modeling, we usewith the following approach: ∆VSRAM th together Sensitivity , it results in a degraded performance of with Sensitivity results in Degradation SRAM ormance For modeling,SRAM we use the following approach: perf 1Vth together The transistor parameter drift ∆V is the direct result of the SRAM cell Degradation . The schematic th ormance performance . with SensitivitySRAM results in perf Degradation the NBTI and PBTI effects, asused described the is previous of The the 6T-SRAM cell that isdrift for thisinwork shown in transistor parameter 1V th is the direct result of section. Together with the sensitivity of the SRAM circuit Fig. 3. While ’performance’ at e.g. logic gates would refer the NBTI and PBTI effects, as described in the previous Sensitivity , it results in a degraded performance of SRAM section. Together with the sensitivity of the SRAM circuit the SRAM cell Degradation perf ormance . The schematicthe Sensitivity SRAM , it results in a degraded performance ofBLB BL ofSRAM the 6T-SRAM cell that is used for this work is shown in cell WLof the 6TWLDegradationperformance . The schematic Fig. 3. While ’performance’ at e.g. logic gates would refer SRAM cell that is used for this work is shown in Fig. 3. While “performance” at e.g. logic gates PL1 PL2would refer to delay, in memories it refers to some metrics that describe BL BLB the WLof the memory cell. Three standard WL “quality” metrics are de’1’ SB scribed in the next sections. PG2 3.1 PG1 PL1S ’0’ PL2 “Static Noise Margin (SNM)” or “Is it safe to read?” PD1 PD2 When a data is read from memory,’1’itSB is important that the PG2 S ’0’ cell does not flip because of this read cycle. The metric dePG1 termining how safe is the read operation is called SNM(read). PD2 It is measured PD1 in Volts and determines how much additional noise voltage is necessary to flip the cell. The smaller this metric, the less stable the cell. SNM is also available for Fig. 3. Schematic of 6T SRAM circuit with naming conventions hold case and determines how much additional noise voltand assumed memory state: ’0’on left side age is necessary to flip the cell under hold conditions. Under hold conditions, the cell is much more stable than under read Fig. 3. Schematic of 6T SRAM circuit naming conventions conditions, which would make thiswith SNM(hold) metric disand assumed The memory state:to’0’on sidemetric is that under hold pensable. reason keepleftthis conditions, it is common to reduce VDD in order to minimize www.adv-radio-sci.net/7/191/2009/ 4 S. S. Drapatz et al.: Impact of NBTI and PBTI on 6T-SRAM cells BL 193 0,24 BLB WL WL PL1 NBTI 0,235 0,23 PL2 ’1’SB PG1 PG2 S ’0’ SNM(read) [V] 0,225 0,22 0,215 -10% 0,21 PD1 PD2 0,205 Vth drift on ’1’ side Vth drift on ’0’ side 0,2 0,195 static power dissipation, which on its part reduces read stability as well. In this work, the focus is on SNM(read), because it is the most critical memory cell parameter. 3.2 “Write Margin” or “Is writing possible?” Besides reading, it is also necessary for a memory cell that safe writing is possible. When writing conditions are applied to the memory cell, it must be sure that the cell will flip accordingly. This metrics called “Write Margin” determines how easy is writing, i.e. at which voltage applied to the according bitline the cell will flip. The higher the flip-voltage, the easier a zero can be written into the cell from the “low” BL. 3.3 “I(read)” or “How fast is reading?” Speed, or in other words access time, is mainly determined by the current flowing in the channel of the access transistors. If it allows big current during the read cycle, faster discharging of the bitline capacity is possible. The bigger this metric “I(read)”, the faster a memory cell can be read. 3.4 Safe reading or fast and writable? All the mentioned SRAM metrics have opposite requirements. Either a cell can be optimized to safe reading or fast and easy writing, both optimizations are not possible together. For example, a cell which is optimized to safe reading will be characterized by a small access transistor and a big pulldown transistor to keep the output of the voltage divider (formed by the access and pulldown transistor) low. But this automatially slows down the cell, because fast access would require a wide access transistor. Additionally, it is getting harder to write, because this would require a small voltage drop across the access transistor. In summary, the critical point in SRAM design besides minimizing the cell area is adjustment of the bias point as www.adv-radio-sci.net/7/191/2009/ -0,075 -0,05 -0,025 0 0,025 ∆Vth [V ] 0,05 0,075 0,1 Fig. 4. Impact of threshold voltage drift of pullup transistor on read stability: 10% loss at −100 mV Vth drift Fig. 4. Impact of threshold voltage drift of pullup transistor on read stability: 10% loss at -100mV Vth drift a tradeoff between readable, writeable and speed. Ongoing downscaling, especially in SRAM design, lets the margin get smaller. A back door for this increasing problem would be alternative SRAM circuit design, e.g. with more than 6 transistors, which of course needs more area per cell. 0,27 0,26 PBTI 0,25 4 Sensitivity of SRAM circuit to BTI degradation 0,24 SNM(read) [V] Fig. 3. Schematic of 6T SRAM circuit with naming conventions and assumed memory state: “0”on left side. -0,1 0,23 In this section, the sensitivity of the 6T SRAM circuit (Fig. 3) 0,22 to BTI degradation ofsidesingle transistors is examined. Since Vth drift on ’1’ Vth drift on ’0’ side BTI0,21degradation mainly causes Vth shifts, the impact of 0,2 threshold voltages is examined. The following -20% drifted analy0,19based on hypothetical Vth drifts. sis is 0,18 4.1 0,17Sensitivity to NBTI-degraded pullup transistor 0,16 -0,1 -0,075 -0,05 -0,025 0 0,025 0,05 0,075 0,1 We present the consequence ∆V of ±100 th [V ] mV Vth drift of one of the pMOS pullup transistors to SNM(read). This, as well as all following simulations, is done with a Spice-based simulation tool. DC simulations were performed with varying threshold voltage of PL1 or PL2. We see that −100 mV Vth Fig. 5. result Impactinofapprox. threshold drift(Fig. of pulldown on 4). Two transistor curves drift 10%voltage SNM loss read stability: 20% loss at +100mV Vth drift exist in the graph because of two states of the memory cell: if the threshold voltage drift is applied to the transistor on side where the “0” is stored (PL1), the dashed line results: influence onduring the readnormal stability. SRAM On the other hand, if the 5 noBTI stress operations threshold voltage drift is applied to the side where the “1” is stored (PL2), the what solid BTI line results, which means reduc-normal Now it is examined stress effects arise from tion of the read stability. Of course, one cannot choose the SRAM operations that are namely hold, read and write. better memory state, because the user operation is deciding. As a consequence, the worse result has to be chosen in these 5.1graphs. Hold Altogether, NBTI in the pullup transistor makes an SRAM During hold, data is kept in the feedbacked inverter-pair. cell more vulnerable to destructive reads, but better writeable During this period, PL2 experiences NBTI stress conditions (compare Fig. 1 and Fig. 3). Furthermore, the pulldown tranAdv. Radio Sci., 7, 191–196, 2009 sistor on the opposite side (PD1) experiences PBTI stress conditions (compare Fig. 2 and Fig. 3). The access transistors do not see PBTI stress conditions, since they are in Fig. 4. Impact of threshold voltage drift of pullup transistor on Fig. 6. Impact of threshold voltage drift of access transisto read stability: 10% loss at -100mV Vth drift read stability: no change for worst case complete time of data hold, one pullup and its opposite pulldown are affected by BTI (Fig. 7), and this state can last for years! et al.: Impact of NBTI and PBTI on 6T-SRAM cells S. Drapatz 0,27 0,26 194 PBTI 0,25 complete time of data hold, one pullup and its opposite down are affected by BTI (Fig. 7), and this state can las years! 0,24 SNM(read) [V] 0,27 0,23 0,26 0,22 PBTI Vth drift on ’1’ side Vth drift on ’0’ side 0,25 0,21 -20% 0,2 0,24 NBTI SNM(read) [V] 0,19 0,23 0,18 0,22 0,17 0,21 0,16 ’1’ Vth drift on ’1’ side Vth drift on ’0’ side -0,1 -0,075 -0,05 0,2 -0,025 0 0,025 ∆Vth [V ] 0,05 0,075 ’0’ 0,1 -20% NBTI 0,19 PBTI 0,18 ’1’ 0,17 Fig. 5. Impact of threshold voltage drift of pulldown transistor on 0,16stability: 20% loss at +100mV Vth drift read -0,1 0 0,1 -0,075 -0,05 -0,025 0,025 0,05 0,075 ’0’ S. Drapatz et al.: Impact of NBTI ∆Vthand [V ] PBTI on 6T-SRAM Cells 5 5. BTI stress normal operations Fig. Impact of during threshold voltageSRAM drift of pulldown transistor on read stability: 20% loss at +100 mV Vth drift. Fig. 7. NBTI stress on pullup and PBTI stress on pulldown during Fig. 7. NBTI on pullupPBTI and hold results in stress an asymmetrical cell.PBTI stress on pulldown during hold results in an asymmetrical cell Now it is examined what BTI stress effects arise from normal Fig.SRAM 5.0,27Impact of threshold pulldown transistor on operations that arevoltage namelydrift hold,ofread and write. 5 BTI stress during normal SRAM operations read stability: 20% loss at +100mV VthPBTI drift 0,26 5.2 Read Now it is examined what BTI stress effects arise from normal SRAM operations that are namely hold, read and write. 0,24 In a read cycle, data isstress extracted from the cell and hold, during data is kept in theSRAM feedbacked inverter-pair. Fig. 7. NBTI on pullup andmemory PBTI stress on pulldown d 5 During BTI stress normal operations transferred to the bitlines via the access transistors. During During this period, PL2 experiences NBTI stress conditions 0,23 hold results in an asymmetrical cell 5.1 Hold this cycle, the situation is almost the same as during hold. (compare Fig. 1 and Fig. 3). Furthermore, the pulldown tran0,22 Now it is examined what BTI stress effects arise from normal Additionally, be in a time the access transistor sistor on the opposite side (PD1) experiences PBTI stress During hold, there data might is kept the when feedbacked inverter-pair. 0,21 operations that are namely hold, read and write. SRAM on the ’0’ side experiences PBTI stress conditions, after the conditions (compare Fig. 2 and Fig. 3). The access tranDuring this period, PL2 experiences NBTI stress conditions 0,2 bitline got discharged, and the wordline is still open. this sistors do not see PBTI stress conditions, since they are in (compare Figs.Read 1 and 3). Furthermore, the pulldownBut transis5.2 5.1non-conducting Hold is not regarded to be critical for the access transistor. state. Summing up, this means that for the 0,19 Vth drift on ’1’ side tor on the opposite side (PD1) experiences PBTI stress con5.1 Hold SNM(read) [V] 0,25 Vth drift on ’0’ side 0,18 on ditions (compare Figs. 2 and 3). The access transistors do not Instress a read cycle, data extracted from the memory cel During hold, data is kept in the feedbacked inverter-pair. see PBTI conditions, sinceis they are in non-conducting 0,17 -0,1 0 0,1 -0,075 -0,05 -0,025 0,025 0,05 0,075 transferred to means the bitlines access transistors. Du During this period, PL2 experiences NBTI stress conditions state. Summing up, this that forvia the the complete time of ∆Vth [V ] data hold, onecycle, pullupthe andsituation its oppositeispulldown are affected this almost the same as during (compare Fig. 1 and Fig. 3). Furthermore, the pulldown tranby BTI (Fig. 7), and thisthere state might can lastbe forayears! Fig. 6.on Impact threshold side voltage(PD1) drift of access transistor PBTI on read stress Additionally, time when the access trans sistor the of opposite experiences stability: no change for worst case. on the ’0’ side experiences PBTI stress conditions, afte conditions (compare Fig. 2 and Fig. 3). The access tran5.2 Read bitline got discharged, and the wordline is still open. Bu sistors not of seethreshold PBTI stress conditions, sincetransistor they are on in Fig. 6. do Impact voltage drift of access in stability: one memory state. hasworst no effect on this access time since not regarded to be critical formemory the access transistor. non-conducting state.It for Summing up, means that itfor the read no change case In a readiscycle, data is extracted from the cell and does not change the read current. transferred to the bitlines via the access transistors. During this cycle, the situation is almost the same as during hold. 4.2 Sensitivity to PBTI-degraded pulldown transistor Additionally, there might be a time when the access transistor complete time of data hold, one pullup and its opposite pullon the “0” side experiences PBTI stress conditions, after the Again, Vth drifts up to ±100 mV are applied. This time, one down are affected by BTI (Fig. 7), and this state can last for bitline got discharged, and the wordline is still open. But this pulldown transistor (PD1 or PD2) gets varied, and +100 mV years! is not regarded to be critical for the access transistor. Vth drift result in 20% SNM loss. So the influence of Vth on read stability is approx. double for pulldown compared to 5.3 Write pullup, i.e. if PBTI will be in the same range of Vth drift, the effect on read stability will be twice as high (Fig. 5). 4.3 Sensitivity to PBTI-degraded access transistor Analysis of threshold voltage drift of the NBTI access transistor showed improvement of read stability for one memory state, but no worst case change (Fig. 6). However, a weak access transistor decreases’1’ both the write level as well as the read current. ’0’ Adv. Radio Sci., 7, 191–196, 2009 PBTI on During a write cycle, two cases must be distinguished: either the same data is written to the cell that was in memory before. Then the access transistor on the “0” side of the cell experiences PBTI stress for the cycle time, additionally to the hold stress for the pullup and pulldown. Or the cell flips because of the write, then the access transistor on the newly written “0” side only sees PBTI stress for the time after the cell has flipped. The pullup and pulldown stress are changing www.adv-radio-sci.net/7/191/2009/ M Cells S. Drapatz et al.: Impact of NBTI and PBTI on 6T-SRAM cells 195 1 0,28 NBTI+PBTI 0,27 0,9 0,26 0,8 0,25 0,7 0,6 0,23 0,22 0,21 0,3 0,19 0,18 0,2 0,17 pullup Vth drift on ’0’ side + pulldown Vth drift on ’1’ side pullup Vth drift on ’1’ side + pulldown Vth drift on ’0’ side 0,16 0,15 lity ens eriare with ead ned ich ow e to oa sult the be raons oclly: 0,5 0,4 -29% 0,2 -0,1 -0,075 -0,05 -0,025 0 0,025 ∆Vth [V ] 0,05 0,1 0,075 0 0,8 0,1 BTI ost ing wn diing BTI oling . Variations (Var) Var+25mV NBTI Var+50mV NBTI Var+75mV NBTI Var+25mV NBTI+25mV PBTI Var+50mV NBTI+50mV PBTI Var+75mV NBTI+75mV PBTI 0,24 Yield SNM(read) [V] eiory cell to ips wly the ing ary, 5 Fig. 8. Impact of threshold voltage drift of pullup- and opposite pulldown-transistor on read stability: 30% loss at ±100 mV drift. 0,85 0,9 1 0,95 1,05 Supply Voltage [V] 1,1 1,15 1,2 Fig. 9. Yield including global and local variations after long hold of one data with NBTI and PBTI degradation for 256 kBit cell array. Fig. 8. Impact of threshold voltage drift of pullup- and opposite pulldown-transistor on read stability: 30% lossInatsummary, ±100mV drift6.2 Variations in manufacturing to the other pullup/pulldown pair, respectively. the write cycle also is not considered to be critical. One additional item was completely neglected so far: the unavoidable variations during manufacturing, which can be misaligned in the stepper etc. But modern processing tech6 Long hold followed by direct read: the worst case BTI divided into global and local variations. While the degranologies allowforreducing scenario SRAM these irregularities. In the scope of dation effects occur over long time of usage, the variations this work we regard a global variation according to the width exist right after the production process. Global variations ocof The 2σ. last section was pointing out: the hold state is the most cur because the wafers cannot be treated exactly identically: critical one for BTI impact on 6T SRAM, because during Local variations, however, are more severe for SRAM bethey have slightly different doping, the mask will be slightly the complete data hold phase, one pullup and one pulldown misaligned in the stepper etc. But modern processing techcause of the huge number of memory cells in one array. For both experience full BTI stress conditions. It is now addi20 nologies allow reducing these irregularities. In the scope of 1MBit (2 =1.048.576 cells), the variation corresponds to tionally taken into account that threshold voltage drift during this work we regard a global variation according to the width approx. 5,2σ. in the or directly afterThis stressisiswhy maximal, as scope there isof no this time work, for BTIwe reof 2σ . annealing. conclusion long hold of one data, fol- to the gard a local The variation withisa that maximum value according Local variations, however, are more severe for SRAM belowed direct read, is the most critical BTI scenario: during width ofby5σ. cause of the huge number of memory cells in one array. For this read, there is the biggest threat of destructive reading. 1MBit (220 =1 048 576 cells), the variation corresponds to ap6.36.1 Yield prox. 5,2σ . This is why in the scope of this work, we regard a NBTIconsiderations and PBTI effects are adding local variation with a maximum value according to the width of 5σ . Simulations have shown and the 20%local loss of read stability The global variations of 10% 2σ and variations of 5σ defor pullup/pulldown drifts, respectively. Now what happens scribed in section 6.2 are now additionally applied to the 6T 6.3 Yield considerations during “hold” state, when both pullup and pulldown expericore cell. In some devices, the NBTI and PBTI drifts will be ence BTI stress? In Fig. 8 one can see that both impacts are reduced because of the variations, i.e. the threshold voltage The global variations of 2σ and the local variations of 5σ adding! In other words: −100 mV pullup drift together with drifts due to variations and degradation effects will eliminate described in Sect. 6.2 are now additionally applied to the 6T +100 mV pulldown drift result in almost 30% loss of read core cell. In some devices, the NBTI and PBTI drifts will be each other. But in some cells, the threshold voltage drifts will stability. This addition of the two effects can be explained reduced because of the variations, i.e. the threshold voltage the small threshold voltage driftscandidates relative to VDD bewith boosted. These cells are best for, which destructive drifts due to variations and degradation effects will eliminate makes linearizing andSNM(read) therefore addition If itdramatically. is now reads, because their valuepossible. will drop taken into account that with SNM(read)<5% V each other. But in some cells, the threshold voltage drifts will In additionally this yield consideration, cells DD be boosted. These cells are best candidates for destructive are considered as failing cells. 1. single devices can have more than 100mV Vth drift due reads, because their SNM(read) value will drop dramatically. to the wide BTI distribution and the that ’Worst Case Distance’ These calculations were done with In this yield consideration, cells with SNM(read)<5% VDD are considered as failing cells. algorithm (Antreich, Graeb, Wieser, 1994), which gives the 2. all devices can have more than 100mV Vth drift due to same result Monte simulations, with less com- These calculations were done with the “Worst Case Disa directasread accessCarlo without time for BTIbut annealing, tance” algorithm (Antreich et al., 1994), which gives the puting effort. Fig. 9 shows the yield in terms of ’all memsame result as Monte Carlo simulations, but with less comthen it gets clear that these both effects together might result ory cells working in a 256kBit array’. If at least one cell puting effort. Figure 9 shows the yield in terms of “all in a yield deterioration of SRAM over time. in this complete array does not meet the specification, the whole array is considered as failing. One can see that loweringwww.adv-radio-sci.net/7/191/2009/ VDD generally decreases the yield, because SNM(read) is reduced. But the main information is that variations and NBTI together do not have huge impact on SRAM. The com- Adv. Radio Sci., 7, 191–196, 2009 196 S. Drapatz et al.: Impact of NBTI and PBTI on 6T-SRAM cells and PBTI induced threshold voltage drift on pullup and pulldown transistor. Here is the biggest threat of undesired write during a read cycle, which is equal to data loss. BTI behavior like distribution and annealing also plays an important role, especially if a long hold is directly followed by a read cycle, because then annealing is not possible. In future technologies including high-k materials, it is very important to consider these effects during SRAM memory design in order to be able to produce long-life memory cells. 1 0,8 Yield 0,6 0,4 0,2 0 0,7 Var+75mV NBTI+75mV PBTI Var+100mv NBTI+100mV PBTI Var+140mV NBTI+140mV PBTI 0,75 0,8 0,85 0,9 1 0,95 Supply Voltage [V] 1,05 1,1 1,15 1,2 Fig. 10. Yield including global and local variations after long hold of one data with NBTI and PBTI degradation for a single Bit cell. memory cells working in a 256 kBit array”. If at least one cell in this complete array does not meet the specification, the whole array is considered as failing. One can see that lowering VDD generally decreases the yield, because SNM(read) is reduced. But the main information is that variations and NBTI together do not have huge impact on SRAM. The combination of variations and NBTI plus PBTI, however, is much worse: even at VDD,nom , the yield for 25 mV BTI stress each is already below 90%. And the line for each 75 mV BTI stress does not even appear in the graph, because it is always zero! The yield in a 256 kBit array for Variations+NBTI+PBTI is so low that in Fig. 10, it is drawn for a single cell. Then the term “yield” is not the probability of all cells working in the array anymore, but the probability that this single cell fails. This can then be used to design appropriate cell circuits and redundancy schemes, so of course in realistic SRAM designs sufficient yield will still be obtained. 7 Acknowledgements. This work has been supported by the German Ministry of Education and Research (BMBF) within the project “Honey” (Project ID 01M3184A). The content is the sole responsibility of the authors. References Antreich, K. J., Graeb, H. E., and Wieser, C. U.: Circuit analysis and optimization driven by worst-case distances, IEEE T. Comput. Aid. D., 13(1), 57–71, 1994. Fischer, Th., Olbrich, A., Georgakos, G., Lemaitre, B., and SchmittLandsiedel, D.: Impact of Process Variations and long-term degradation on 6T-SRAM cells, Adv. Radio Sci., 2007. Fischer, Th., Amirante, E., Hofmann, K., Ostermayr, M., Huber, P., and Schmitt-Landsiedel, D.: A 65nm teststructure for the analysis of NBTI induced statistical variations in SRAM transistors, Proceedings of the European Solid State device research conference, 51–54, 2008. Heinrigs, W., Reisinger, H., Gustin, W., and Schluender, C.: Consideration of revocery effects during NBTI measurements for accurate lifetime predictions of state-of-the-art pMOSFETs Reliability physics symposium, 288–292, 2007. Seevinck, E., List, F., and Lohstroh, J.: Static Noise Margin Analysis of MOS SRAM Cells, IEEE J. Solid-St. Circ., 22, 748–754, 1987. Zafar, S., Kim, Y. H., Narayanan, V., et al.: A comparative study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates, Proceeding of the Symposium on VLSI Technology, 23–25, 2006. Conclusions The impact of global and local variations and NBTI on 6T SRAM core cell are not negligible, but still do not dramatically impact the SRAM design. This is because the two pMOS pullup transistors are the only ones to be affected by NBTI. The sensitivity of the SRAM circuit to small threshold voltage drifts of these transistors is not excessive. The situation including PBTI is much worse: this effect works on the nMOS pulldown as well as the access transistors, and the sensitivity especially of the pulldown transistor is much higher: with the same threshold voltage drift, the impact on read stability is twice as high for pulldown compared to pullup devices. Moreover, during hold state of the memory, the two effects are adding, so that the cell weakens drastically in terms of read stability. The cell loses approx. 30% for 100 mV NBTI Adv. Radio Sci., 7, 191–196, 2009 www.adv-radio-sci.net/7/191/2009/