Download Crosstalk Circuit 2

E3VB
Education Engagement Electrical Validation
Board Experiment Description
Sep 2013
Intel Contacts: Dennis Griffith, Mike Anderson, Tony Muilenburg
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Contents
Overview ...................................................................................................................................................... 4
Schematic Overview .................................................................................................................................. 4
Layout Overview ......................................................................................................................................... 5
Routing Examples ...................................................................................................................................... 6
Clocks .......................................................................................................................................................... 7
Experimental Setup.................................................................................................................................... 8
Experiments ................................................................................................................................................ 8
Blocks ....................................................................................................................................................... 8
Crosstalk Circuit 1 .................................................................................................................................. 9
Crosstalk Circuit 2 ................................................................................................................................ 12
Decoupling Circuit ................................................................................................................................ 16
Corners and Vias.................................................................................................................................. 18
Mystery Traces ..................................................................................................................................... 20
Simultaneous Switching Outputs ....................................................................................................... 24
LCR Transmission Line ....................................................................................................................... 26
Driver Circuit ......................................................................................................................................... 28
Package Differences............................................................................................................................ 31
Intersymbol Interference ..................................................................................................................... 33
Appendix .................................................................................................................................................... 36
1.1: Clock Design ................................................................................................................................. 36
1.2: Board Layers ................................................................................................................................. 36
1.3: Clock Drivers ................................................................................................................................. 40
Driver U9:........................................................................................................................................... 40
Driver U14: ........................................................................................................................................ 41
1.4: Mystery Traces ............................................................................................................................. 42
Routing ............................................................................................................................................... 42
Probe Points...................................................................................................................................... 44
1.5: Integrated Circuits ........................................................................................................................ 44
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1.6: Schematic Contents ..................................................................................................................... 44
1.7: Experiment Headers .................................................................................................................... 45
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Overview
The Education Engagement Electrical Validation Board was created as part of an
initiative called Intel Learning Company 2.0 to engage with university and help teach
students electrical validation concepts. The board is made up of several circuits
designed for hands-on experiments that can be conducted using a low bandwidth
oscilloscope. These experiments demonstrate the importance of adhering to good
design practices when laying out and routing signals on a board. The board is
configurable using sockets and jumpers so that the student can see the difference in
signal integrity when following or violating good design practices. The physical board is
shown in Figure 1.
Figure 1: E3VB board
Schematic Overview
The schematic is available in PDF format, with the experiments grouped in one or two
pages. Ten main experiments are listed, though many more signal integrity concepts
can be demonstrated. Figure 2 shows an example schematic circuit diagram. See
appendix 1.8 for the schematic contents.
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Figure 2: Schematic diagram example from the “corners and vias” experiment
Layout Overview
The board file can be opened using Allegro free physical viewer. The tool can be used to
search for components, signals, integrated circuits, etc. A snapshot of the top layer is shown in
Figure 3 with signal routing visibility disabled. A snapshot of each of the layers is available in
appendix 1.2.
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Figure 3: Top layer of the EV board
Routing Examples
Figure 4 and Figure 5 show examples of routing on the board. Many of the signal traces are
very long, routed too close to others, or violate routing practices. These characteristics are ideal
for demonstrating common signal integrity issues.
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Figure 4: Layer "Signal 1"
Figure 5: Layer "Signal 2"
Clocks
Two sets of clocks are used to feed the ten experiments. The clock frequency for the first five
experiments and experiment 7 are driven from the first set. This clock is selected and enabled
by populating one jumper on each of two header pin sets. The first set is labeled J54, and is
shown in Figure 6 with 1 MHz selected. The second set is labeled J71, and provides the clock
signal for the remaining experiments. Four frequencies are available including: 1 MHz, 2 MHz,
4 MHz, and 8 MHz. See Appendix 1.1 for more information about how the clocks are
generated.
Figure 6: The 1 MHz clock is selected using a jumper
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Experimental Setup
Power for the board is provided using mini USB. The cable can be plugged into a wall adapter,
or laptop computer. Signals are measured using an oscilloscope with a recommended
bandwidth of 500 MHz or more. Signals are probed using normal oscilloscope probes, or a
BNC to BNC cable for two of the experiments. Figure 7 shows the BNC to BNC connector
attached to the board. Header pins are provided for oscilloscope probing, as demonstrated in
Figure 8.
Figure 8: Probe connections
Figure 7: BNC Connection to the board
Experiments
In this section, we will walk through the ten experiments, describing how to configure
the board and connect probes to outputs in order to measure the signals.
Blocks
The experiments are broken into blocks as much as possible, and outlined in white on the
board. Figure 9 shows the location of each of the experiments overlaid on the board. The BNC
connectors are oriented up.
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Figure 9: Experiment Blocks
Crosstalk Circuit 1
The first experiment was designed to show the effects of crosstalk. A signal is driven down a
long trace that has two traces routed closely to it on either side. The trace in the middle is
called the victim trace, and the traces next to it are called aggressors. Figure 10 shows the
victim trace routing. Figure 11 and Figure 12 show the aggressors.
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Figure 10: Victim trace
Figure 11: Aggressor 1 trace
Figure 12: Aggressor 2 trace
Each of the three traces can be configured independently to behave in one of three ways:
toggle, stay high, or stay low. When in toggle mode, the clock is routed to the signal. The effect
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the aggressor traces have on the victim can be viewed and measured using an oscilloscope.
Figure 13 shows the schematic diagram for the victim trace. The aggressors schematic blocks
look the same. The signal comes into a header that is designed to provide three selectable
inputs: High, Low, and Toggle. For the victim trace, the header is labeled J30. The board also
has a label “V” next to this header. The aggressors can be configured similarly using headers
J24 and J28 (also labeled A1 and A2).
Figure 13: Victim schematic diagram
Figure 14 shows where the experiment is located on the board (circled in white).
Figure 14: Crosstalk circuit 1 location
The inverting buffer chips labeled U6 and U3 are socketed so different chips can be tried and
compared for this experiment. Both sockets should be stuffed as shown in Figure 15.
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Figure 15: Inverting buffer integrated circuit stuffed in socket U6
If a clock frequency has not yet been enabled, this should be done by stuffing one of the header
pins labeled 1MHz, 2MHz, 4MHz and 8MHz in the center of the board with a jumper. This
header is labeled J54.
Victim Output Exercise
Connect the oscilloscope to the victim output labeled J43. Capture the output for the victim
signal when the victim and both aggressors are toggling at 1MHz. Zoom in on the rising and
falling edges. How does the signal change when the aggressors are disabled vs enabled?
The quality of the victim signal when the aggressors are switching is dependent on the quality of
the chip used. Repeat the exercise for two different chip types, and compare the results. Two
possible chips could be:
sn74ac04n
74f04N
While the inverting buffer between the transmission line and output cleans up much of the
distortion on this transmission line. There is still significant distortion on the output.
Crosstalk Circuit 2
This experiment is similar to crosstalk circuit 1, but the victim signal is differential, and the chips
are soldered down rather than socketed. The victim portion of the schematic is shown in Figure
16. The aggressor traces are routed the same as the aggressor (and victim) traces from the
first crosstalk circuit.
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Figure 16: Differential victim circuit design
Routing for the victim and aggressor are long and close together as shown in Figure 17 and
Figure 18.
Figure 17: Differential victim trace (green dashed line)
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Figure 18: Aggressors surrounding the victim signal (green dashed line)
The location of the circuit for this experiment is shown in Figure 19 circled in white.
Figure 19: Crosstalk circuit 2 location
Similar to the first experiment, pattern selection headers are provided to set the signals high,
low, or to toggle. When in toggle mode, the clock is routed to the trace. The jumpers used to
select the pattern are as follows:
Aggressor 1: J45
Aggressor 2: J44
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Victim: J46
To set the signal low, leave the jumper unpopulated. Populating the jumper on pins 1 and 2 will
set the signal high, and stuffing 2 and 3 will set the signal to toggle up and down.
Outputs can be measured at the following pins:
Victim Output: J32
Aggressor 1 Output: J37
Aggressor 2 Output: J67
Exercise
Unlike the previous experiment where the victim signal was referenced to ground, the positive
victim signal will be referenced to the negative victim signal in this exercise. Figure 20 shows
how the differential signal is built. The top signal is the positive leg of the signal, probed from
J64 to ground. The signal in the center is the negative signal probed from J65 to ground. The
bottom signal is the combined differential signal probing from J65 to J64. Note: all three of
these signals were probed at the start of the transmission line.
Figure 20: Differential signal made up of the combined positive and negative signals
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To see the effects of crosstalk on the signal, enable the aggressor traces and set them to
toggle. To enable the aggressor traces, populate jumpers J63 and J42. Next, the aggressors
should be set to toggle, which will create noise on the differential signal. Aggressor 1 can be set
at header J45, and aggressor 2 can be set at header J44.
How does the victim channel look when:
Neither of the aggressors are enabled?
Aggressor 1 is enabled and toggling?
Both aggressors are enabled and toggling?
Only aggressor 2 is enabled and toggling?
Repeat the above set of experiment for the case where the victim is toggling, and the case
where the victim lane is not toggling. What is the amplitude of the distortion for each case?
Decoupling Circuit
It is important for high speed signal design to prevent undesired coupling between circuits. One
way to reduce coupling is to add capacitance. Good grounding is another important aspect.
Exercise 3 explores both of these. Figure 21 and Figure 22 show how the chips for this
exercise are fed. The amount of capacitance for the voltage feeding the chips can be changed
by adding a jumper to J78 labeled VCCIN. The grounding can be changed by adding a jumper
to J69 labeled SGND.
Figure 21: Input capacitance
Figure 22: Ground jumper
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The decoupling circuit can be found on the middle left side of the experiment board (circled in
white in Figure 23).
Figure 23: Decoupling circuit
Decoupling Exercise
The output for this experiment can be measured at the header block labeled: Lo T T T T Hi (J48
– J53). The outputs labeled T look similar to each other.
Capture waveforms at the output for the case where VCCIN is populated, and compare the
output to the case where the jumper is not populated. What is the difference in circuit behavior?
Grounding Exercise
The ground provided for the inverting buffer goes through a long high impedance trace when
jumper J69 is removed. Figure 41 shows the routing for this trace.
Figure 24: High Z Trace to Ground
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Measure the impedance for this trace with the jumper removed.
Adding the jumper J69 connects the point directly to ground.
How does the signal compare when the header labeled SGND is populated with a jumper vs
unpopulated? Zoom in on the rising and falling edges of the signal.
Corners and Vias
When routing a circuit board, it is important to be careful not to make corners too tight, and to
minimize the number of vias. This exercise will explore what the signal looks like with poor
routing. Figure 25, Figure 26, and Figure 27 show routing for three different traces labeled VTP,
CTP, and TLTP. The TLTP trace is the optimally routed, while VTP has lots of vias, and CTP
has lots of corners.
Figure 25: TLTP Trace
Figure 26: VTP Trace
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Figure 27: CTP Trace (over two layers)
The circuit is pretty simple. The clock signal comes in, goes through an inverting buffer, down a
trace, and through another inverting buffer. The general circuit topology is shown in Figure 28.
There are test points at the beginning of the trace, the end, and at the output.
Figure 28: General circuit topology
Figure 29 shows where the location of the experiment on the board.
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Figure 29: Corners and vias experiment location
The test points include:
VTP start: J58
CTP start: J59
TLTP start: J57
VTP end: J56
CTP end: J47
TLTP end: JJ61
Vout: J60
Cout: J47
TLout: J62
Exercise
Compare the rising and falling clock edges for the three signals.
How do the edges compare when probing at the start of the trace, and the end of the trace.
Note: The difference may be small enough that it is hard to measure.
Mystery Traces
For this exercise, the oscilloscope will be used to find trace length and impedance using a
technique called Time-domain reflectometry (TDR). A signal is sent down the trace, and signal
corruption due to reflections will be measured to determine trace characteristics. Trace length
is determined, by measuring time, and impedance is determined by measuring voltage level.
Exercise
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Figure 30 shows the location of the circuit components and trace selector on the top of the
board.
Figure 30: Mystery traces exercise location
Adding a jumper to Header J14 will enable the clock on one of eight traces, each of which is
routed differently. Figure 31 shows an example of the rising edge of the corrupted signal, and
how the trace length can be determined by the duration the signal stays at one level. In this
example, there are three different segments each with different impedance. The impedance
can be determined by the voltage level, and the trace width can be calculated from this. The
routing is shown in Figure 32 .
Figure 31: Mystery trace example
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Figure 32: Trace 5 routing
To measure the signal, a BNC connector is attached from the scope to the U1 connector on the
board. The shape of the rising edge of the signal is captured from which information about the
signal can be determined. In addition, probe points were placed between each of the trace
sections to help demonstrate how each leg of the trace contributes to the shape of the signal.
Figure 33 shows the circuit diagram.
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Figure 33: Circuit Diagram
The layer, size, and time for each of the traces are captured in the following table:
Experiment Layer
1
S1
2
S2
3
S1
4
S2
5
S1
6
S3
7
S1
8
S2
Trace 1
Size
(mil)
40
6
20
10
20
6
40
40
Time
(nS)
2
3
2
3
2
4
2
2
Layer
S2
S3
S4
Trace 2
Size
(mil)
20
20
8
Time
(nS)
2
2
4
Layer
S3
Trace 3
Size
(mil)
6
Time
(nS)
2
S4
6
2
S2
40
2
S4
S3
6
6
2
3
S2
12
2
Additional probe points are available and outlines in the appendix under the mystery traces
section.
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Simultaneous Switching Outputs
When multiple outputs switch simultaneously, it is difficult for power distribution to keep up. The
ground potential for the device briefly raises compared with the system ground. This effect is
known as simultaneous switching noise, or ground bounce. Induction in the board, traces, and
components keep power from being delivered instantaneously.
This exercise is designed using counters that feed a driver so that many edges line up only
some of the time. The location of the exercise on the board is shown in Figure 34.
Figure 34: Simultaneous switching exercise location
The circuit for this exercise is made up of eight signals that feed a driver. Two counters provide
seven square waves that feed seven of the signals. The eighth signal is DC voltage with the
level controlled by a potentiometer labeled CW LOWER (designator U20). The threshold can be
changed by turning the screw on the potentiometer, and measured at header J88.
Exercise
To begin this exercise, enable the counters by populating header J87 (next to the
potentiometer) with a jumper. The output of each of the seven signals is made available at
header J102. Each output is a square wave with twice the period of the preceding as shown in
Figure 35. The clock was captured along with the signals for comparison (J93).
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Figure 35: Driver outputs, and clock in
When the 1 MHz signal is selected for the clock, the frequency of each output is as follows:
Output
0
1
2
3
4
5
6
Frequency (kHz)
250
125
62.5
31.3
15.6
7.8
3.9
When the 8 MHz signal is selected, each clock frequency increases by a factor of 8.
Every 128 clock cycles all seven of the counter signals switch at the same time. This creates a
spike on the output signal. The same thing can happen even when only a few of the signals
switch, though the amplitude of the distortion will be smaller.
Measure the output, hit run and stop on the oscilloscope many times to view different noise
profiles, or set the trigger level high to view spikes created by switching.
Compare the signal with the clocks enabled and disabled.
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Enable persistence on the oscilloscope to see what the output looks like over many
superimposed cycles.
LCR Transmission Line
For this experiment, a clock signal is sent down a transmission line that can be lengthened
using jumpers, or outfitted with resistors, inductors and capacitors to mimic trace characteristics
for high speed signals. Clock 7 first goes through an inverting buffer, then has a connection for
a BNC connector to make measurements. From there, the trace extends across the board with
jumper headers that can be populated with the elements.
The inverting buffer block is labeled U5, and the BNC connector U2. The schematic for this
circuit is shown in Figure 36, and the location on the board is shown in Figure 37.
Figure 36: LCR Transmission Line Circuit
Figure 37: Location of the LRC Transmission Line Exercise
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Figure 38 shows the routing for the transmission line.
Figure 38: Transmission line routing
Exercise
To begin, take a look at how the signal changes due to lengthening the trace. The transmission
line is made as short as possible by removing the four jumpers that extend the transmission
line: TL1, TL2, TL3, and TL4 with designators: J26, J110, J2, and J111. Compare what the
signal looks like when each of the next stages are enabled.
Many configurations can be explored by adding resistors and capacitors to the legs rather than
just extending them with jumpers. Figure 39 shows three examples. The ISI exercise has
another example of a possible block in the circuit (an inductor and capacitor).
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Figure 39: Three possible configurations
Driver Circuit
This circuit provides an environment to compare driver technology. Relatively inexpensive
drivers exist that cannot switch as quickly as the more expensive ones. Some drivers can
switch the rising edge quickly, but not the falling edge, etc. Sockets are provided on the board
so that the driver chips can be swapped out. Here is a recommended list of chips to try:
Chip
74C04
74HC04
74F04
74AC04
Description
Inexpensive weak driver
Medium Speed
Fast rising edge, slow falling edge
Fast on both edges
The circuit is similar to that used in the crosstalk exercise, and is shown in Figure 40. The trace
labeled SGTP (slotted ground test point) is routed over a slot in the ground plane, making it
more susceptible to noise. Figure 41 and Figure 42 show the routing. Test points are available
at the beginning of the trace, the end, and at the output after going through the inverting buffer.
The sockets provided for the inverting buffers are labeled U18 and U17.
Figure 40: Driver Circuit
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Figure 41: Routing for Signal SGTP (in blue)
Figure 42: Routing for signal TP (in blue)
Figure 43 shows the section of the SGTP trace that is routed over a slot in the ground plane.
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Figure 43: SGTP signal routed over a slot in the ground plane
Exercise
To begin this exercise, compare the 74AC04 chip to the 74F04 chip when used as a circuit
driver. Measurements can be taken at the end of the transmission line for both the TP trace and
the SGTP trace. Figure 78 shows the location of the circuit for this exercise on the board.
Figure 44: Driver Circuit Location
The first measurement can be taken for signal TP at header J72.
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Package Differences
This exercise was designed to show differences in signal quality due to package type used.
The chips are all soldered down to the board, so four circuits are provided which are the same.
Figure 82 shows one of these four circuits. The input signal (the clock) goes through the chip,
then down a long transmission line. The traces of interest are labeled “Near” and “Far” and are
routed differently. Measurement points are provided at the start and end of the transmission
line. The measurement points close to the start of the traces for the four circuits are as follows:
Probe points at the start of the
Transmission line
Signal “Near”
Signal “Far”
9_1 D1
9_1 D2
9_2 D1
9_2 D2
9_3 D1
9_3 D2
9_4 D1
9_4 D2
Measurement points at the end of the traces are:
Probe points at the end of the
Transmission line
Signal “Near”
Signal “Far”
9_1 S1
9_1 S2
9_2 S1
9_2 S2
9_3 S1
9_3 S2
9_4 S1
9_4 S2
Figure 45: Package Difference Circuit Topology
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The package type and size used in this exercise are as follows:
The circuit for this experiment is located on the bottom of the board, circled in Figure 46 in
white.
Figure 46: Package Difference Circuit Location
Routing for the SOIC chip is shown in Figure 47 for the “far” signal, and Figure 48 for the “near”
signal.
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Figure 48: SOIC “Near” Trace
Figure 47: SOIC “Far” Trace
Exercise
For this exercise, signals are driven with four chips each of which has a different package. The
signal can be compared for each package type.
Intersymbol Interference
Intersymbol interference signal distortion is a result of previous symbols interfering with the
current symbol. As an example, this could affect the duty cycle.
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To create this effect, this exercise uses a counter which feeds into shift registers. The output is
then driven down a circuit similar to the driver circuit, but with an inductor and capacitor, as
shown in Figure 49. These elements help simulate what the circuit response would look like if a
high speed interface was used.
Figure 49: ISI Circuit Design
Switches are provided which the shift registers use to create the signal See Figure 50.
Figure 50: DIP Switches
Experiment
The circuit for this exercise is located in the center bottom portion of the board, and is circled in
white. See Figure 51.
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Figure 51: ISI Circuit Location
Three probe points are provided for this experiment:
In: J89
Out: J86
TLine: J82
Exercise
Configure the dip switches to create different patterns, and observe the effect the patterns have
on future signals. Duty cycle is one area of interest when observing signal integrity impacts. As
an example of what to expect from toggling the switches, an example configuration is shown in
Figure 52, along with the signal in Figure 53.
Figure 52: Jumper configuration for the ISI exercise
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To trigger with the oscilloscope, it is useful to use output 2 of header J102 (from the
simultaneous switching exercise). This output allows for triggering on a 62.5 kHz signal when
the clock is at 1MHz, and a 500 kHz signal when the clock is set to 8 MHz. This is ideal to
capture waveforms for this exercise.
Figure 53: In vs Tline vs Out using the 1 MHz clock
Compare the input to output signal, and to the transmission line. Does the input always
follow the ouput?
Appendix
1.1: Clock Design
The clock was designed using a binary counter. Each of the four outputs is equivalent to a
clock with a different frequency. Figure A1 shows an example.
Figure A1: Binary counter outputs
1.2: Board Layers
Each of the layers with signals routed can be seen in the following figures
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Figure A2: Top Routing
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Figure A3: Bottom routing
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Figure A4: Signal 1 routing
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Figure A5: Signal 2 Routing
1.3: Clock Drivers
Driver U9:
1_1: Crosstalk circuit 1
1_2: Crosstalk circuit 2
2_1: Crosstalk circuit 2
2_2: Corners and Vias
3: Mystery Traces
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4: Simultaneous Switching
5: Crosstalk circuit 1
7: Decoupling
Driver U14:
6: Driver Circuit
8: LCR T-line
9_1: Package Differences
9_2: Package Differences
9_3: Package Differences
9_4: Package Differences
10: Intersymbol interference
(one pin is a no-connect)
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1.4: Mystery Traces
Routing
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Probe Points
Trace
1
2
3
4
5
6
7
8
Probe Point
1
2
J117
J5
J11
J7
J9
J8
J91
J6
J114
J107
J116
J13
J16
J115
3
J12
J27
J4
1.5: Integrated Circuits
TPS79601DCQG4:
ULTRALOW-NOISE LINEAR REGULATOR
SN74HC191D:
POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER
CD74AC04M:
HEX Inverter, AC-CMOS, 14 Pin, Plastic, SOP
SN65LVDS1DR:
High-Speed Differential Line Driver/Receiver
SN74AC11240DW:
SOIC SO24 package, Octal Buffer/Line Driver with 3−State Outputs, inverted output
SN74AC240PW:
TSSOP Package, Octal Buffer/Line Driver with 3−State Outputs, inverted output
MC74AC240DW:
SOIC SO20 Package, Octal Buffer/Line Driver with 3−State Outputs, inverted output
SN74AC240N:
DIP Package Octal Buffer/Line Driver with 3−State Outputs, inverted output
SN74LV165ARGYRG4:
Counter Shift Registers Parallel-Load 8-Bit Shift Register
MC74HC04ADR2G:
Hex inverter
1.6: Schematic Contents
1.
Education Engagement EV Board
2.
Power Supply and Regulator
3.
Clock Generation
4.
Crosstalk Circuit #1
5.
Crosstalk Circuit #1 - Spares
6.
Crosstalk Circuit #2
7.
Crosstalk Circuit #2 - Spares
8.
Decoupling Circuit
9.
Corners and Vias
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10. Corners and Vias - Spares
11. Mystery Traces
12. Simultaneous Switching Outputs
13. LCR T-Line
14. Driver Circuit
15. Driver Circuit - Spares
16. Package Differences - SOIC / TSSOP
17. Package Differences - DIP / 74AC11240
18. Intersymbol Interference
19. Intersymbol Interface - Output & Spares
20. Mounting holes - TDR Test Point
1.7: Experiment Headers
Experiment 1: Crosstalk 1
J17: Aggressor 1 transmission line test point (beginning)
J18: Aggressor 1 output test point
J19: Victim transmission line enable
J20: Victim transmission line test point (beginning)
J21: Aggressor 2 transmission line test point (beginning)
J22: Aggressor 2 output test point
J24: Aggressor 1 pattern select
J28: Victim pattern select
J29: Aggressor 1 transmission line enable
J30: Aggressor 2 pattern select
J31: Aggressor 1 transmission line test point (end)
J35: Victim transmission line test point (end)
J38: Aggressor 2 transmission line test point (end)
J41: Aggressor 2 transmission line enable
J43: Victim output test point
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Experiment 2: Crosstalk 2
J66: Aggressor 1 transmission line start test point
J37: Aggressor 1 output test point
J64: Victim transmission line start test point (positive)
J65: Victim transmission line start test point (negative)
J40: Aggressor 2 transmission line start test point
J67: Aggressor 2 output test point
J44: Aggressor 2 pattern select
J45: Aggressor 1 pattern select
J46: Victim pattern select
J63: Aggressor 1 transmission line enable
J33: Aggressor 1 transmission line end test point
J36: Victim transmission line end test point (positive)
J39: Victim transmission line end test point (negative)
J68: Aggressor 2 transmission line end test point
J42: Aggressor 2 transmission line enable
J32: Victim output test point
Experiment 3: Decoupling
J78: VCCIN decoupling enable
J70: Clock in test point
J69: SGND: Direct ground
J48: Test point Low
J49: Test point toggle 1
J50: Test point toggle 2
J51: Test point toggle 3
J52 Test point toggle 4
J53: Test point high
Experiment 4: Corners and vias
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J73: Clock in test point
J57: TL transmission line test point (beginning)
J61: TL transmission line test point (end)
J62: TL out test point
J58: V transmission line test point (beginning)
J56: V transmission line test point (end)
J60: V out test point
J59: C transmission line test point (beginning)
J47: C transmission line test point (end)
J55: C out test point
Experiment 5: Mystery Traces
U1: BNC connector test point
J14: Trace selector
Experiment 6: Simultaneous switching
J93: Clock in test point
J87: Counter enable
J90: Count up/down select
J95: RCO: ripple carry over
J100: Min/Max
J88: Input threshold test point
J102: Output test points 0 through 6, and out
Experiment 7: LCR transmission line
U2: BNC connector test point
J26: Stage 1 upper
J25: Stage 1 lower
J110: Stage 2 upper
J109: Stage 2 lower
J2: stage 3 upper
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J3: stage 3 lower
J111: stage 4 upper
J112: stage 4 lower
Experiment 8: Driver comparison and slotted ground
J81: slotted ground transmission line test point (beginning)
J75: slotted ground transmission line test point (end)
J76: slotted ground output test point
J77: transmission line test point (beginning)
J72: transmission line test point (end)
J74: output test point
Experiment 9: Package differences
J105: 9_1_S1 - test point (beginning)
J106: 9_1_S2 - test point (beginning)
J98: 9_1_D1 - test point (end)
J99: 9_1_D2 - test point (end)
J104: 9_2_S1 - test point (beginning)
J103: 9_2_S2 - test point (beginning)
J97: 9_2_D1 - test point (end)
J96: 9_2_D2 - test point (end)
J101: 9_3_S1 - test point (beginning)
J94: 9_3_S2 - test point (beginning)
J80: 9_3_D1 - test point (end)
J79: 9_3_D2 - test point (end)
J83: 9_4_S1 - test point (beginning)
J84: 9_4_S2 - test point (beginning)
J108: 9_4_D1 - test point (end)
J113: 9_4_D2 - test point (end)
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Experiment 10: Intersymbol interference
S1: Dip switches
S2: Dip switches
J89: In test point
J82: Transmission line test point (beginning)
J86: Output test point
Other
Clock frequency selectors
J54: Block 1
J71: Block 2
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