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Design Review 2
Karen Joseph
Mehdi Kabir
Ashley Brinker
ECE 6332: VLSI
Professor Calhoun
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Contents
I. Input Vector Control
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II. MTCMOS Analysis
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III. Dual-Vt Analysis
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IV. Paper Reviews
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V. Reflection and future work
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I. Input Vector Control
Figure 1: Simulation of gate and subthreshold leakage currents in 3-input NAND gate (130nm CMOS) with vector
input of <000>. The top two graphs show the subthreshold leakage in the NMOS transistors. The bottom three
graphs show the gate leakage current through the PMOS transistors.
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Figure 2: The total leakage current as a function of the input vectors in 3-input NAND gate (in 130nm CMOS).
Figure 3: The total leakage current as a function of input vectors in 2-input XOR gate (in 130nm CM0S).
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Figure 4: Schematic of 3-input NAND gate (actual circuit was built with a netlist).
Figure 5: Schematic of 2-input XOR gate (actual circuit was built with a netlist).
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II. MTCMOS Analysis
In this section, we look at the following modified circuit:
For comparison purposes, the input is forced to 111 and sleep is on for leakage current calculation. Below are
the graphs generated from the simulation data across different size technologies. As expected, MTCMOS reduces
leakage current. The MTCMOS places a sleep PMOS transistor and a sleep NMOS with a high Vt than the other
transistors. When the circuit is idle (sleep=1), the circuit is cut off from VDD and ground and the high Vt of the sleep
transistors reduces leakage current. The Vt of the other transistors are kept low, thus ensuring a reasonable delay when
active (sleep=0).
As Vt of the sleep transistors increase, as expected by the leakage current equation, the leakage current will
reduce. However, increasing Vt has its effect on delay.
The following graphs show the change in current as the Vth of the sleep transistors change from 0.4 to 0.8. As
Vth increases, the current decreases. Also, the current decreases across technologies.
Figure A,below, shows the subthreshold current as Vth increases.
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Figure B, below, shows the gate leakage current as Vth increases.
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Figure C, below, shows the total leakage current (subthreshold current + gate current) as Vth increases.
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The following graphs show the subthreshold leakage reduction (Subthreshold current in a regular nand gate –
subthreshold current using MTCMOS) across different size technologies. As the size of the transistor decreases, the
reduction current also decreases.
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The following graphs, below, show the gate leakage reduction (gate leakage current in a regular nand gate –
gate leakage current using MTCMOS) across different size technologies.
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III. Dual VT Analysis
The graph windows below are plots of the leakage current through a 3-input NAND gate using dual-Vt technology for an
input of 000. The outputs were obtained using a variety of Vt values. These plots were also taken using predictive model
technology ranging from 32nm to 130nm. In each graph window, the first plot is the leakage at the drain of first NMOS
transistor (N0), and the following 3 plots are the gate leakage of the PMOS transistors (P0, P1, P2). The table below
shows the approximate results.
Technology Vt
32nm
45nm
65nm
90nm
130nm
0.3
0.4
0.5
0.6
0.7
0.8
0.3
0.4
0.5
0.6
0.7
0.8
0.3
0.4
0.5
0.6
0.7
0.8
0.3
0.4
0.5
0.6
0.7
0.8
0.3
0.4
0.5
0.6
0.7
0.8
N0 leakage
9.07 nA
1.292 nA
412.88 pA
325 pA
318 pA
318 pA
5.36 nA
793.65 pA
333.96 pA
295 pA
290 pA
290 pA
3.49 nA
550.6 pA
295 pA
276.3 pA
275 pA
274.75 pA
2.555 nA
297.56 pA
126.47 pA
115 pA
115 pA
114.5 pA
2.12 nA
187.15 pA
57.49 pA
50 pA
49 pA
49.5 pA
P0 leakage
-7.45 pA
-7.275 pA
-7.239 pA
-7.233 pA
-7.25 pA
-7.25 pA
-5.7 pA
-5.75 pA
-5.55 pA
-5.55 pA
-5.55 pA
-5.55 pA
-4.47 pA
-4.385 pA
-4.371 pA
-4.369 pA
-4.369 pA
-4.369 pA
-1.3 pA
-1.265 pA
-1.26 pA
-1.26 pA
-1.26 pA
-1.26 pA
-383 fA
-378.5 fA
-377.8 fA
-377.7 fA
-377.7 fA
-377.7 fA
P1 leakage
-7.45 pA
-7.275 pA
-7.239 pA
-7.233 pA
-7.25 pA
-7.25 pA
-5.7 pA
-5.75 pA
-5.55 pA
-5.548 pA
-5.55 pA
-5.55 pA
-4.47 pA
-4.385 pA
-4.371 pA
-4.369 pA
-4.369 pA
-4.369 pA
-1.3 pA
-1.265 pA
-1.26 pA
-1.26 pA
-1.26 pA
-1.26 pA
-383 fA
-378.5 fA
-377.8 fA
-377.7 fA
-377.7 fA
-377.7 fA
P2 leakage
-7.45 pA
-7.275 pA
-7.239 pA
-7.233 pA
-7,25 pA
-7.25 pA
-5.7 pA
-5.75 pA
-5.55 pA
-5.548 pA
-5.55 pA
-5.55 pA
-4.47 pA
-4.385 pA
-4.371 pA
-4.369 pA
-4.369 pA
-4.369 pA
-1.3 pA
-1.265 pA
-1.26 pA
-1.26 pA
-1.26 pA
-1.26 pA
-383 fA
-378.5 fA
-377.8 fA
-377.7 fA
-377.7 fA
-377.7 fA
This table shows that as the predictive model increases the leakage in the NMOS transistors and PMOS
transistors decreases. It also shows that as the value of Vt increases the leakage decreases also. Depending on the
predictive model, once the Vt value gets to a certain point the decrease in leakage tends to taper off and settle on that
value as Vt increases.
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Below are the simulation outputs for 45nm Technology across Vt values from .3 to .8. The same was repeated
(graphs not included in this report but can be found on the wiki page) for 32nm, 65nm, 90nm, and 130nm Technologies.
45nm Technology
Vtn = 0.3
Vtp = -0.3
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45nm Technology
Vtn = 0.4
Vtp = -0.4
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45nm Technology
Vtn = 0.5
Vtp = -0.5
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45nm Technology
Vtn = 0.6
Vtp = -0.6
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45nm Technology
Vtn =0 .7
Vtp = -0.7
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45nm Technology
Vtn = 0.8
Vtp = -0.8
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The following graph windows show the delay in transitioning from 000  111 for each predictive model technology at a
Vt of 0.4. The first 3 plots of the window show the transition of the inputs (A, B, C) from 0  1. The last plot show when
the output (Y) transitions. Comparing when Y transitions compared to when the inputs transition gives the delay of the
system. The table below shows the results.
Input
Output
Transistion
Transistion
Technology Complete
Complete
Delay
32 nm
2.01
2.05
0.04
45 nm
2.01
2.0675
0.0575
65 nm
2.01
2.075
0.065
95 nm
2.01
2.1
0.09
130 nm
2.01
2.125
0.115
This table shows that as the predictive model technology increases the delay of the transition also increases.
130nm Technology Delay from 000  111
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32nm Technology Delay from 000  111
Note : The graphs for 45nm, 65nm, and 90nm delay of 000  111 can be found on the wiki.
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IV. Review papers
Rao, R., Burns,J., Brown, R. (2004). Analysis and Optimization of Enhanced MTCMOS Scheme. Proceeding of the 17th
International Conference on VLSI Design.
One of the methods to reduce leakage current is to stack turned-off CMOS in series. One such stacking
scheme is using MTCMOS which uses low-Vth transistors for fast logic operations and high-Vth transistors headers
and footers to reduce subthreshold leakage current while the circuit is idle. While the MTCMOS scheme is effective
in reducing subthreshold leakage, the authors show that a forced stacking scheme always leads to a greater gate
leakage current if the circuit delay is kept constant. The paper continues in quantifying both gate leakage and
subthreshold leakage in terms of the activity factor of the circuit. By doing so, the authors showed that for a given
activity factor, the gate leakage dominates subthreshold leakage. Therefore, to reduce total leakage current, it’s
more important to optimize gate leakage current. Since one of the factors controlling gate leakage is the width of
the transistors, the total leakage of a circuit can be reduced by appropriately sizing the header/footer MTCMOS
transistors compared to the rest of transistors in the stack. The authors concluded the paper with a formula which
gives the optimal sizing ratio for an arbitrary circuit with a given activity factor.
Note: Another paper review is embedded within the next section.
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V. Reflection and future work
Currently, we have examined three separate methods to reduce total leakage in a circuit—input vector control,
MTCMOS and variable threshold CMOS design. The input vector control method was motivated by the fact that in
stacked circuits gate leakage has a much greater contribution to the overall leakage than subthreshold leakage. We were
able to show that by controlling the inputs to simple circuits like a 3-input NAND gate or 2-input XOR gate, we can
significantly reduce the overall leakage through those circuits. Next, we looked at the effects of MTCMOS on total
leakage on a simple 3-input NAND gate. With the use of MTCMOS we were able to reduce not only subthreshold current
but also gate leakage current when used in conjunction with input vector control. We also found that using both header
and footer MTCMOS provided better leakage control than using a header or footer only. Finally, in the variable threshold
CMOS design, we have looked at the effect of changing the threshold voltage on total leakage and switching delay of the
circuit. This was done by modifying the threshold voltage for all the transistors in a 3-input NAND. We found that by
lowering the threshold voltage, we were able to improve the switching delay at the cost of higher total leakage current.
Some of the challenges we faced in our project was learning and using Ocean script. We learned how to
calculate leakage current and verified it with several circuits before using that technique on the analysis shown above.
We were also able to familiarize ourselves with loops in the ocean script to sweep necessary variables. For the MTCMOS
design, we changed the .scs files for the different size technologies to include Vt as a variable, which was then sweeped
in ocean to consider the current variations due to different Vt. For the next step, we plan to use a more complex circuit.
One of the main things we need to figure out is how to determine whether a transistor is on or off and then calculate its
leakage or subthreshold current. We figured out a simple (but tedious in terms of coding) to go through every transistor
in the circuit. We checked this with the TA in office hours and learned that this was one of the best methods possible.
Then next step in our project is to take our results for leakage reduction for simple gates and apply it to a larger,
more complicated circuit—a 16-bit accumulator. The accumulator bit-slice will be composed of a ripple-carry full adder
connected to a register. From our results, we were able to derive the best case input vectors for components of the full
adder. Using this knowledge, we can apply some type of heuristic [1] to estimate the best the case input vector to
reduce the overall gate leakage in the device. We plan to check the estimated best case scenario against a sample of
random input vectors to check the correctness of the input vector. In addition, we are going use MTCMOS design within
the internal nodes of the circuit to give us more input vectors for us to further reduce the leakage current. While figuring
out the optimal case for MTCMOS replacement is beyond the scope of this project, we can use the fast replacement
algorithm in [2] to give us a good idea which gate replacements will be the most beneficial. Finally, since we’ve tabulated
the delays associated with increasing or decreasing the threshold voltage, we plan on using low-Vth transistors on critical
paths for better performance, while using larger Vth on non-critical paths for lower leakage.
Since our proposal, we’ve had to make some changes to our timeline. We had already planned to have started
optimizing the 16-bit adder by this time. However, after researching the optimization methods, we decided it would be
better if we gathered information and analyzed the simpler sub-circuits within the adder. Using the data we gathered,
we can employ the algorithms outlined above to greatly speed up our search for the optimal scenario. In terms of the
work breakdown, we have been able to maintain the plan that was outlined in our proposal.
[1] A. Abdollahi et al (February 2004). Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control. IEEE
Trans. VLSI Systems 2004, 12(2).
[2] Yuan, L., Qu, G. (February 2006). A Combined Gate Replacement and Input Vector Control Approach for Leakage
Current Reduction. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(2).