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Increasing ADC’s Sampling Circuit Reliability with
Respect to Transistor Aging
Ehsan Mazidi
Sahab Ardalan
Center for Analog-Mixed Signal Lab
San Jose State University
San Jose, CA, USA
[email protected]
Center for Analog-Mixed Signal Lab
San Jose State University
San Jose, CA, USA
[email protected]
Abstract—This paper studies the reliability of sampling
circuit in Analog to Digital Convertor (ADC) systems with
respect to transistor aging effects. The main concentration in this
study is current leakage and the effects of aging on current
leakage. The sampling circuit in ADC system suffers from two
types of current leakages. The first one is the switch leakage and
the other one is the gate leakage of the amplifier or load after the
capacitor. In this paper the author explores both types of
leakages and studies the effects of transistor aging on current
leakage. Based on the findings of this study we then propose a
leakage compensation circuit to increase the reliability of the
sampling circuit with respect to aging.
Keywords—ADC Reliability; sampling reliability; current
leakage; transistor aging;
I. INTRODUCTION
High current Leakage in sub-micron CMOS technology is a
growing concern for both analog and digital designers.
However, in VLSI design the main concern is power
consumption, where as in Analog-Mixed Signal (AMS) IC
design, this increased current leakage could lead to wrong data
sampling or loss of data in sensors or wireline transmissions.
Fig. 1 shows the architecture of a typical ADC sampling
circuit.
Fig. 1. Sampling architecture in ADC
As evident in the Fig. 1 the sampling node in the
architecture is connected to two ports, one is the drain node of
PMOS and NMOS in Transmission Gate (TG) before the
capacitor and the other is to the gate node of the differential
amplifier of the load after the capacitor. Based on the
comprehensive study of Roy et al on the current leakage
mechanism [1] there are four different leakages involved in the
current leakage of the sampling circuit. These current leakages
have the potential to change the value of sampled signal. In the
sensitive analog signals such as those found in low voltage
sensors, even the slightest change in the value of input signal
could lead to inaccurate reading of analog signal. This error
could exacerbate through time by the transistor aging effect.
This paper will examine current leakage affecting the sampling
value and transistor aging effect on that, also a compensation
circuit will be presented in order to increase the reliability of
the sampling circuit in sensitive ADC systems.
Section II gives a better understanding of the mechanism of
leakage in CMOS transistor in sub-micron technology. Section
III examines the effects of aging on transistor and subsequent
effects of aging on current leakage. In section IV we introduce
a self-healing circuit in order to compensate the current leakage
both before and after aging.
II. CURRENT LEAKAGE MECHANISMS IN SAMPLING CIRCUIT
There are four different leakage sources affecting sampling
circuit in ADC. Two of those sources are due to drain to source
leakage and the other two are gate leakage.
A. Subthreshold Leakage
One of the leakage sources happens when the gate voltage
is below Vth . Because there is still a small electric field and
mobile carriers in the channel, transistor will experience a
small drift current from drain to source. In this situation there is
a weak inversion current leaking through channel [2].
B. Punchthrough
Due to close proximity of the drain and source in submicron CMOS technology the depletion region at the drainsubstrate and source-substrate junction extends into the channel
unlike the long channel transistors. The close proximity of
drain and source depletion regions allow the carries to punch
through the junction barriers at higher reverse bias voltages.
This phenomenon occurs below the surface of the channel and
will cause the current leakage from drain to source [3].
C. Tunneling Through Gate Oxide
In sub-micron technology in order to achieve higher
operating frequency and lower latency, the gate oxide thickness
have been reduced in an effort to decrease the gate capacitor
and hence decrease time constant τ. This reduction in gate
thickness has made the gate oxide vulnerable to the electron
tunneling phenomenon in which electrons will travel through
(tunnel) the oxide voltage barrier to the other side of the oxide
and into the channel. At this point when electrons go through
gate oxide we have gate leakage [4].
D. Hot Carrie Injection
Due to high electric field near the gate oxide in short
channel transistors, electrons in the transistor channel can gain
enough potential to cross the oxide barrier potential and enter
into oxide layer. This is another type of current leakage that
can happen to gate oxide [5].
The aforementioned leakage mechanisms can cause error in
sampling circuit in ADC systems. However, only current
leakages regarding gate leakage will be affected due to
transistor aging, the reason for which is based on the transistor
aging phenomenon.
III. TRANSISTOR AGING PHENOMENON
The effects of transistor aging were first observed in
eighties. Since then many studies have been conducted on
transistor degradation due to aging. Transistor aging effects
stems from three main causes. These phenomena’s are: TimeDependent Dielectric Breakdown (TDDB), Hot Carrier (HC),
and Negative Bias Temperature Instability (NBTI).
A. Time-Dependent Dielectric Breakdown (TDDB)
Dielectric breakdown can happen due to the large electric
fields across the gate-oxide in nanometer CMOS devices. The
result of this high electric field is the total or partial loss of
gate oxide properties in CMOS devices. This would result in
an increase of the magnitude and noise of the gate current.
Breakdown is a stochastic phenomenon and the time to BD
(𝑡𝐵𝐷 ) can be described with a Weibull probability distribution
[6]:
𝐹(𝑡𝐵𝐷 ) = 1 − 𝑒𝑥𝑝 [− (
𝑡𝐵𝐷 𝛽
𝑡63
) ]
(1)
With β a process-dependent constant and t 63 , the time to
breakdown at the 63% percentile, proportional to the transistor
size and inversely proportional to the applied gate voltage VGS .
B. Hot Carrier (HC)
A large electric field near the drain end of a transistor in
saturation can results in the change of transistor characteristics
such as the threshold voltage 𝑉𝑇𝐻 , the carrier mobility β and
the output conductance g o which is called Hot Carrier (HC)
stress effect. HC effects are, similar to NBTI, shown to be
frequency-independent and are more significant in NMOS
rather than PMOS devices [6].
∆𝑉𝑇𝐻 ∼
1
√𝐿
𝑒𝑥𝑝(𝛼3VGS ) 𝑒𝑥𝑝(𝛼4VDS )𝑡 𝑛𝐻𝐶
(2)
Where 𝑛𝐻𝐶 ≈ 0.5 represents the time exponent of aging
period, and α3 and α4 are technology-dependent voltage
scaling parameters and L is the channel length.
C. Negative Bias Temperature Instability (NBTI)
Negative Bias Temperature Instability (NBTI) recently
gained a lot of attention due to its increasingly adverse impact
in nanoscale CMOS technology. NBTI is temperature
dependent and its effect is typically observed as a shift in
threshold voltage when a negative bias voltage has been
applied to a PMOS gate.
It is believed that NBTI is caused by broken Si-H bonds,
which are induced by positive holes from the channel. Then H,
in a neutral form, diffuses away, and positive traps are left as a
consequence. This raising electric field (EOX ) through the oxide
thickness, which generates interface traps in PMOS transistors,
results in unwanted increase in threshold voltage of the PMOS
transistors. NBTI effect as explained due to its nature is
frequency independent.
The following equations summarize dependencies
involving significant process parameters as well as fitting
parameters, which degrade the circuit operation under the
NBTI phenomenon [7, 8]. These equations were utilized to
simulate aged transistors in DFFs.
∆𝑉𝑡ℎ,𝐼𝑇 ≈ 𝑒
𝑒
𝑇𝐼𝑇𝑇𝐷 𝜀
)[ (𝑉𝐺𝑆 −𝑉𝑡ℎ )]
𝐾∙𝑇
𝜏𝑑
𝑇𝐼𝑇𝐶𝐸
(−
[𝑇𝐼𝑇𝐹𝐷∙𝐸𝑑 (𝑉𝐺𝑆 ,𝑉𝐷𝑆 )]∙𝑡 𝑁𝐼𝑇
∙𝑡
𝑁𝑂𝑇
∙
(3)
𝑇𝑂𝑇𝑇𝐷
𝑇𝑂𝑇𝐹𝐷+ 𝑇
]∙𝑡 𝑁𝑂𝑇
𝐸𝑑 (𝑉𝐺𝑆 ,𝑉𝐷𝑆 )
[
∆𝑉𝑡ℎ,𝑂𝑇 ~ 𝑒
(4)
Equation (3) and (4) show NBTI physical effects in terms
of changes in voltage threshold in oxide trapped (∆Vth,OT ) and
interface trapped (∆Vth,IT ) charges, along with fitting
parameters such as TITFD, TITCE, and other parameters [8].
Through studying the Transistor aging degradation effects
one can realize the most significant effects happen to the gate
thus the current leakage degradation would happen in the gate
leakage.
IV. SELF HEALING GATE LEAKAGE CIRCUIT
The idea behind self-healing circuit is to have a circuit that
can adapt to the changes in the operating situations of the
original circuit. The simple idea behind current leakage
compensation is to recreate the leaking current and reinject that
current into the leaking point in the circuit. In the sampling
circuit the capacitor is where the voltage drops due to current
leakage through gate node. Hence by creating a replicate of the
load/diff-pair, and using it as the reference point in a current
mirror, once can recreate the exact leaking current and then re
inject it into the capacitor at the sampling node. Fig. 2 shows
the architecture for such compensation circuit.
capacitor node. Table II presents the voltage drop for the same
criteria as Table I.
TABLE II.
SAMPLED VOLTAGE DROP
Voltage drop under age
degradation with and
without compensation
Sampled voltage drop
before Compensation
(mV)
Sampled voltage
drop after
Compensation
(uV)
Not aged
2.5
50
Aged
6
70
CONCLUSION
In conclusion this paper has presented a study into the
reliability of sampling circuit in ADC systems in normal
operating environment and also under the effects of transistor
aging degradation. The study shows that transistor aging has
direct impact on gate leakage in the sampling circuit. A selfhealing circuit has been presented to compensate the effects of
leakage under normal and aging effects. The simulation results
presented show that the compensation circuit can almost rectify
the voltage drop due to leakage.
Fig. 2. Current leakage compensation architecture
The current mirror will transfer the generated current which
is the gate leakage current back into the cap in order to
compensate the gate current leakage. The advantage of this
method is that due to aging effect the replicated load circuit
would degrade the same way as the original load would thus
any change and increase to the leakage would also happen to
the compensating circuit, hence the name self-healing.
Table 1 shows a comparison between sampling circuit
employing self-healing current leakage compensation circuit
and a sampler without compensation circuit. The table also
shows the current leakage before and after aging degradation
and compares the compensation circuit effectiveness.
TABLE I.
CURRENT LEAKAGE AND COMPENSATION
Leakage under age
degradation with and
without compensation
Current leakage
before Compensation
(nA)
Current leakage
after Compensation
(pA)
Not aged
1
20
Aged
2.5
26
The current leakage in the gate node of transistor will
translate into voltage drop over the sampled signal at the
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