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Design of SHAKTI Processor
based Safety Systems for
Nuclear Power Plant
By
Satya Rajesh Medidi, M. Manimaran, N. Anil, Ankit Kumar,
Dr. D. Thirugnana Murthy, K. Madhusoodanan
Prof.V. Kamakoti
Indira Gandhi Centre for Atomic Research
Speaker (IGCAR)
IIT-Madras
Agenda
Introduction
• Distributed Architecture of PFBR
• Fault tolerant methods
• Hot standby architecture
• Computer based systems / Real Time Computers
• VME bus based 68020 CPU card
• Component Obsolescence
• SHAKTI CPU card
• Road map
•
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Introduction
•
Instrumentation and Control (I&C) systems provide
protection, control, supervision and monitoring in nuclear
power plants
•
I&C systems are designed as per AERB SG D-10, D-20 &
D-25 safety guides.
•
I&C systems are classified as
◦ Safety Critical Systems (SCS)
 Play principal role in achievement or maintenance of nuclear
power plant safety
◦ Safety Related Systems (SRS)
 Play a complementary role to the Safety Critical systems
◦ Non-Nuclear Safety Systems (NNS)
 Play auxiliary or indirect role in achievement of nuclear power
plant safety
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Introduction

In modern nuclear power plants, computer based systems
(CBS) are extensively used for Instrumentation and
Control systems.

CBS intrinsically contains four important functions:
◦
◦
◦
◦
Scanning the inputs from sensors
Processing logics
Diagnostics
Generation of outputs for actuators/final control elements and
Sending the processed data for storage & display purpose
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Computer Based Systems

Typically the CBS is backplane bus based system
comprises of
◦ CPU card
◦ Analog Input /Output cards
◦ Digital Input /Output cards

No operating System
 Application software is fused in EPROM
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Distributed Architecture of PFBR
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Fault Tolerant Methods

Single Failure Criterion

Fault tolerance can be achieved in two ways

Diversity
◦ Advantage: Common cause failures can be avoided
◦ Disadvantage: Stock inventory will be high

Redundancy :
◦ Cold redundancy
◦ Warm redundancy
◦ Hot redundancy (SRS systems of NPP)
 Dual redundant systems with Switch Over Logic
◦ n-way redundancy with voting logic (SCS systems of NPP)
 Triplicated systems with 2/3 voting logic
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Hot Standby Architecture
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Typical I&C system cabinet
RTC1
RTC2
DI & RO
simulator
AI
simulator
SOLS
Development system at Lab
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Criteria for Processor Selection for
Safety Applications






No bug lists
Availability from more than one vendor
Track record in the market
Compatibility with backplane bus
Preferably proven track record in Safety Applications
Motorola 68020 based CPU card is used in Safety
critical and Safety Related systems of Prototype Fast
Breeder Reactor (PFBR).
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VME CPU Card
CPU
FPP
VME Controller
EPROM
Serial Port
RTC
VME Master Interface
Display
LED Indications
Control Logic
SRAM with ECC
EEPROM
Watchdog Timer
WDT Testability
Local Area Network
: MC68020 @ 25MHz
: MC68882 @ 25MHz
:VIC068A
: 1MB, 16 bit width
: 4 No’s
: 1No Battery backed
: A32:D32, A24:D16, A16:D16
: 4 digit alpha-numeric
:VME access, EEPROM access,WDT, RUN,DBE.
: Altera MAX7256S CPLD
: 2MB, 32 bit width, Battery backed
: 128KB, 8 bit width (For storing configuration data)
: Programmable - milliseconds to seconds
(10 ms – 5 secs),
: on demand, Potential Free Contact O/P for status
: 2 No’s Hardwired TCP/IP Ethernet module
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Block Diagram MC68020 based CPU card
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Component Obsolescence
68020 is obsolete
• The component life cycle is less than product (Reactor) life
cycle
• NPPs designed to operate for 40 to 50 years.
• Electronic components used in CBS becoming obsolete in
10 to 15 years
• 25% Spare inventory to sustain for next 10 years
•
•
Obsolescence of processor used in CPU card creates
demand not only on the hardware but also on the software
used in the system
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Ways to overcome obsolescence






HDL based designs
With open specification
Open tool chain for application development
Verification framework for open specifications
FPGA or ASIC route
Integration with third party peripherals with IP
cores
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Why SHAKTI processor?
Open Specification
Verification Framework
Expertise (IIT-M)
Obsolescence free road map
Backward compatibility
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Courtesy: Prof.V.Kamakoti, IIT-M, Chennai
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Proposed Solution
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Proof of concept
•
To have proof of concept SHAKTI processor based piggy
back board is designed which acts as a snap-in pin to pin
replacement for MC68020 on CPU base board without
altering control glue logic, EDAC logic and VME Interface
logic.
•
To establish hardware compatibility with MC68020 CPU
card, SHAKTI processor is associated with wrapper Logic.
Wrapper logic translates SHAKTI core's read and write
cycles to MC68020 read and write cycles respectively.
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Piggy back Board

SHAKTI Processor and it's associated wrapper logic is being
implemented in Artix 7 family FPGA from Xilinx Inc.

Piggy back board consists of Artix 7 FPGA, associated power
circuitry, reset circuitry, clock circuitry, level translation
circuitry, debug circuitry and pin grid array for connecting to
MC68020 CPU card.

Power, reset and clock for piggy back board are derived from
CPU base board. Power supply sequencing of core and
input/output modules of FPGA is done by power circuitry.
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Interfaces

Joint Test Action Group (JTAG) port and Serial port are
provided on piggy back board for debug purpose.

JTAG port is also used for loading FPGA configuration data
on on-board flash memory of piggy back board.

Uni-directional and bi-directional level translators with
latch-up protection are provided on piggy back board to
enable voltage compatibility across voltage domains of piggy
back board and CPU base board.

To establish software compatibility, the application
programs of MC68020 CPU card is modified accordingly.
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Road Map




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The design of wrapper logic is taken up by IIT-M, Chennai
and is in progress.
Piggy back FPGA board for implementing SHAKTI processor
is under fabrication.
Application program that is intended to work on MC68020
CPU card will be compiled and build with the RISC V toolchain.The same will be flashed in CPU board.
Functionality and performance of the SHAKTI CPU card will
be evaluated with the existing CPU card.
Full scale CPU card will be designed with the same
specifications of existing CPU card.
Thoroughly verified SHAKTI processor based CPU card will
be deployed in CBSs of nuclear power plants.
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Road Map
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References
[1] AERB SG D-1, 2003. Atomic energy regulatory board: safety classification and
seismic categorisation for structures, systems and components of pressurized
heavy water reactors. In: AERB Safety Guide No. AERB/NPP-PHWR/SG/D-1. AERB
SG D-1, Mumbai, India
[2] AERB SG D-25, 2010. Atomic energy regulatory board: computer based
systems of pressurized heavy water reactors. In: AERB Safety Guide No.
AERB/NPPPHWR/SG/D-25.AERB SG D-25, Mumbai, India.
[3] M. Manimaran, A. Shanmugam, P. Parimalam, N. Murali, S.A.V. Satya Murty, 2015.
Software development methodology for computer based I&C systems of
prototype fast breeder reactor Nucl. Eng. Des 292 46–56.
[4] https://riscv.org/ Dt. 01/10/2016
[5] http://rise.cse.iitm.ac.in/shakti.html Dt. 01/10/2016
[6]
Chetal, S.C., Balasubramaniyan, V., Chellapandi, P., Mohanakrishnan, P.,
Puthiyavinayagam, P., Pillai, C.P., Raghupathy, S., Shanmugham, T.K., Sivathanu Pillai,C.,
2006.The design of prototype fast breeder reactor. Nucl. Eng. Des. 236,852–860
[7]https://www.xilinx.com/products/silicon-devices/fpga/artix-7.htmlDt. 01/10/2016
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Acknowledgment
The authors express wholehearted thanks to
• Dr. A.K. Bhaduri, Director IGCAR.
• Members of Electronics and Instrumentation
Group, IGCAR.
• SHAKTI team of IIT-M for their valuable
contribution.
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Thank You
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