Download A Tunable Fabry-Perot-Interferometer for 3

A Tunable Fabry-Perot-Interferometer for 3 - 4.5 µm Wavelength
with Bulk Micromachined Reflector Carrier
Norbert Neumann1, Matthias Heinze1, Steffen Kurth2, Karla Hiller3
1
InfraTec GmbH, Dresden, Germany
Fraunhofer Institute for Reliability and Microintegration, Berlin/Chemnitz,
3
Chemnitz Univ. of Technology, Center for Microtechnologies, Chemnitz
2
ABSTRACT
This contribution deals with the design, fabrication and test of a micro-machined first order FabryPerot Interferometer (FPI) that is intended for use as a tunable infrared (IR) filter in many
applications, including IR spectrometers. To achieve optimal interference conditions within an FPI,
the curvature of its internal mirrors must be minimized while the parallelism between mirrors is
maintained. The approach here minimizes mirror curvature by using relatively thick (300 µm Si)
mirror carriers for the coplanar fixed and movable mirrors of the FPI. Dielectric λ/4 wave
reflectance stacks consisting of deposited alternating layers of silicon dioxide (SiO 2) and
polycrystalline silicon (Si) are used as the mirrors and λ/4 thick SiO2 is used as the antireflection
layer at the backside of the mirrors. The cavity spacing is electrostatically driven and controlled.
Keywords: Spectrometer, Interferometer, Tunable optical filter, Dielectric layer stack
1. INTRODUCTION
In recent years, much effort has been devoted to the development of tunable optical filters based on
Fabry-Perot Interferometers (FPI). These efforts have been driven by the need for a tunable filter in
wavelength division multiplexing of optical communications and in gas analysis in the near
infrared. In some applications at 1.5 µm, for example, self-supporting indium phosphide (InP) / air
gap based Bragg mirrors have been used 1,2. Some of the FPI’s used in the visible spectral range
consist of an evaporated single layer of silver (Ag) as mirrors, deposited on a Si3N4 membrane
supported by a solid thick silicon (Si) rim. This combination provides for high reflectance over a
wide wavelength range but the transmittance in the narrow design bandwidth of interest 3 is limited
to about 20 % due to the absorption of the Ag layers 4. In the infrared, tunable FPI’s based on
dielectric mirrors have been used in spectroscopic chemical analysis and other applications in the
1.6 µm to 1.8 µm and 3 µm to 5 µm regions 5,6. Dielectric mirrors in these devices are typically
constructed of reflectance stacks consisting of thermally evaporated alternating λ/4 wave optical
thickness layer pairs of high and low index materials such as Si / SiO2, InP / air and for longer
wavelength FPI’s, germanium (Ge) / Zinc Sulfide (ZnS) or Ge / Zinc Selenide (ZnSe). Material
pairs chosen must have reasonable transmission in the FPI tunable filter range.
Some of the most important properties of an FPI filter are the in band transmittance at the design
wavelength, its bandwidth or its full width half maximum (FWHM) and the tunable spectral range.
These characteristics are determined by the reflectivity and the phase change of the mirrors and
limited by the curvature and tilt of the mirrors and any non-uniformities in the filter cavity.
Depending on the application, further consideration has to be given, in the design of the FPI, to
reduce susceptibility to mechanical vibration or shock.
1
2. GENERAL DESIGN
The FPI produced (Fig.1) consists of a carrier for the fixed mirror and electrodes (4th wafer), the
movable mirror carrier and suspension (2nd and 3rd wafers) and the upper electrode (1st wafer).
Mirrors of dielectric layer stacks define the cavity in first order configuration. The cavity spacing is
electrostatically tuned and capacitively detected by a closed loop control. The optical active area of
2.2mm x 2.2 mm is located in the center of the driving and detection electrodes, the suspension with
diagonal beams, and the rim of the FPI.
Movable mirror
carrier
Upper electrode
Wafer 1
Cavity and dielectric
layer stacks
spacing
Wafer 2
Air Cavity
Wafer 3
Driving and sensing
electrodes
Wafer 4
Fixed reflector
carrier
Field
stop
Antireflection
layer
Fig. 1. Cross sectional drawing of the FPI
The approach discussed here is based on bulk micro-mechanics. Relatively thick (300 µm) silicon
wafers were used as the carriers for both the fixed and the movable mirror. Wafers were processed
in such a way as to allow for minimal mirror curvature and good parallelism necessary to maintain
uniform cavity size and spacing over the optical active area. In the wavelength range of interest,
absorption loss due to the substrate was eliminated by choosing slightly doped silicon with high
specific resistance in the 3-10 ohm· cm range. The transmittance of a 300 µm thick silicon substrate
in the wavelength range of interest was measured in a Bruker IFS 66 FTIR spectrometer and is
shown in Figure 2. It should be noted that considering the reflectance losses at the Si (n = 3.43) and
air interfaces a transmittance can be calculated by τ = 2n/(n2+1) = 0.537, a measured transmittance
of 0.535 demonstrates virtually no absorption in the low resistivity sample. To confirm the
considerable influence of resistivity on sample transmission, a heavily doped 400 µm Si wafer
(0.01-0.05 ohm· cm) was also measured for comparison.
100
Transmittance [%]
80
Si 300µm, 3...10 Ωcm
60
40
20
Si 300µm, 0.01...0.05 Ωcm
0
1
2
3
4
5
6
7
8
Wavelength [µm]
Fig. 2. Transmittance of slightly and heavily doped silicon
2
3. OPTICAL CONCEPT
The dielectric mirrors of the FPI are quarter wave optical thickness reflectance stacks. These
reflectance stacks consist of vacuum deposited alternating layers of high and low index materials.
Polycrystalline silicon was chosen as the high index and SiO2 for the low index material. The first
reflectance stacks are deposited in the active optical area on the top side of the 4th wafer and the
bottom side of the 3rd beginning with a λ/4 thick SiO2 layer followed by a λ/4 wave layer of
polysilicon. Two versions were built. One version had a second and the other a third quarter
wavelength stack that were deposited in alternating layers on top of the first. In the reflectance
stacks beyond the first, PECVD-SiO2 was used as the low index layer. A thermally grown λ/4 thick
SiO2 layer, with a conformal lateral shape for stress compensation, was deposited to serve as an
antireflection layer on the top side of the 3rd wafer and the bottom of the 4th.
Efforts were made to measure and determine the index of refraction of the materials used to confirm
material properties were not adversely affected by fabrication and deposition processes (See
Table 1) The properties of PECVD-SiO2 and thermally grown SiO2 layers were measured using a
Gaertner L115B ellipsometer. To determine the refractive index of the polycrystalline silicon, layer
thickness was measured by a phase shift interferometer located at the edge of the silicon substrate.
A special sample was then prepared with a free standing stack of silicon and SiO 2 at a certain
distance to a polished Silicon surface (Fig.3). The difference between the virtual height h1 at the
location L1 (under the stack) and h2 at the location L2 (not under the stack) from the same surface
can then be entered into the following formula to determine the refractive index of the silicon:
n Si =
t Si
t Si + t ox − (h1 − h2 ) − t ox
nox
where tSi the thickness of the silicon layer, tox the thickness of the SiO 2, and the refractive index of
SiO2 ( nox ) are known by previous measurements. Over a number of samples, nSi was calculated
with resulting values ranging from 3.30 to 3.42 and an average of 3.37. These results correlate very
well with published values of the index of refraction of polycrystalline silicon (see Table 1).
Fig. 3. Special sample for determination of refractive index of polysilicon
Table 1. Refractive index and quarter wavelength thickness of used material
Material
Refractive index
Refractive index
Quarter-wave optical
(Literature)
(experiment)
thickness (λ0 = 3.8 µm)
polysilicon
276 nm
3,43 (λ = 6 µm) 7
3,37 (λ = 0,55 µm)
PECVD-SiO2,
1,48
642 nm
SiO2, thermally
1,40 8
1,46
650 nm
grown
3
In the wavelength region of interest (i.e., 3.2 µm to 4.8 µm), the reflectance, using the transfer
matrix method, was calculated to be higher than 0.85 in the version with the two quarter wavelength
stacks. In the three quarter wavelength stack version, the reflectance was consistently higher than
0.95 (Figs. 4, 5). To reduce the undesirable ripples in the reflecting wavelength band caused by
multiple reflections from the bottom of the wafer (Fig. 4), the bottom surface of a three quarter
wave stack version was antireflection coated. As expected, the ripples of the in band reflectance
were virtually eliminated and the reflectance was improved (Fig. 5)
1
Reflectance
0.8
0.6
0.4
0.2
0
1
2
3
5
4
Wavelength λ [µm]
7
6
data5
Fig. 4. Layer sequence and calculated reflectance in case of double quarter-wave stacks without
back side antireflection layer
1
Reflectance
0.8
0.6
0.4
0.2
0
1
2
3
5
4
Wavelength λ [µm]
7
6
data4
Fig. 5. Layer sequence and calculated reflectance in case of triple quarter-layer stacks with a back
side antireflection layer
The number of quarter wavelength stacks determines the phase change of the mirrors and the
longest and shortest wavelengths that define the usable tuning range of the interferometer (Table 2).
The phase change increases the necessary deflection of the movable mirror and the driving force to
tune the FPI by 57% in the case of the two quarter wave version and by 85% in three quarter wave
units. The reflectance of each of a number of special Si wafers that were coated with two and three
quarter wavelength stacks was measured in an FTIR spectrometer (Fig.6). The results reconfirm
that the three quarter wavelength stack version offers higher reflectance and flatness in the pertinent
reflection band than the two quarter wavelength stack units.
4
relative to Au layer
1.1
Three λ/4 layer stacks
Reflectance
1
0.9
Two λ/4 layer stacks
0.8
0.7
0.6
0.5
2
3
4
5
Wavelength [µm]
6
7
Fig. 6. Dielectric stack reflectance referenced to evaporated gold (Au)
Table 2. Phase change influenced by thin film mirrors and appropriate cavity spacing
Central
wavelength
3.0 µm
3.4 µm
4.5 µm
3.0 µm
3.4 µm
4.5 µm
Phase
Cavity spacing without
Cavity spacing after
change
phase correction
phase correction
double quarter-wave stacks, design wavelength 3.4 µm
2.90 rad
1.50 µm
1.385 µm
3.14 rad
1.70 µm
1.700 µm
3.58 rad
2.25 µm
2.570 µm
triple quarter wave stacks, design wavelength 3.4 µm
2.80 rad
1.50 µm
1.337 µm
3.14 rad
1.70 µm
1.700 µm
3.68 rad
2.25 µm
2.638 µm
1
1
0.8
0.8
Transmittance
Transmittance
The values for the cavity spacing and the phase correction have been validated by a calculation of
the transmission properties of the interferometer at the design, as well as the shortest (λmin) and
longest (λmax) usable wavelengths. The results (Fig. 7) show that the achievable bandwidth depends
on the location of the center wavelength within the reflectance band of the FPI. As the center
wavelength of the interferometer is tuned to near the maximum usable wavelength of the reflectance
band, the bandwidth deteriorates as the reflection at that wavelength is reduced. The oscillations on
the sides of this pass band are caused by multiple reflections from the back sides of the mirror
carriers.
0.6
0.4
0.2
0
0.6
0.4
0.2
0
2.5
3
3.5
4
Wavelengthλ [µm]
4.5
5
2.85
2.9
2.95
3.00
3.05
3.10
3.15
Wavelengthλ [µm]
a
5
1
1
0.8
Transmittance
Transmittance
0.8
0.6
0.4
0.2
0.6
0.4
0.2
0
0
2.5
3
3.5
4
Wavelengthλ [µm]
4.5
2.25
5
2.3
2.35
3.40
3.45
3.50
3.65
4.60
4.65
Wavelengthλ [µm]
1
1
0.8
0.8
Transmittance
Transmittance
b
0.6
0.4
0.2
0.6
0.4
0.2
0
0
2.5
3
3.5
4
Wavelengthλ [µm]
4.5
5
4.35
4.40
4.45
4.50
4.55
Wavelengthλ [µm]
c
Fig. 7. Transmittance of the FPI with a cavity spacing of 1.337 µm (a) 1.7 µm (b) and 2.638 µm (c)
4. OPTICAL LAYERS DEPOSITION
Careful consideration was given in choosing the materials used as the low and high index optical
layers in the FPI as well as their deposition processes to insure compatibility with those required for
patterning the electrodes and the wafers. Optical layers, without further treatment, would not
survive the Si wet etching process required to define the electrode patterns. Furthermore,
depositing these layers after Si patterning would require extensive processes and tooling to keep the
depositions from obscuring the electrodes for bonding. The low index material chosen was silicon
dioxide (SiO2) with n = 1.4 since it can be deposited using two different processes (see Table 3).
Thermally grown SiO2 is widely used in the MEMS fabrication processes to provide an electrically
isolating layer as well as an etch mask for Si wet etching processes. Thermally grown layers can be
produced to very tight layer thickness tolerances but the oxide growth will reduce Si material
thickness (approx. 0.45 x SiO2 layer thickness). Accordingly, thermal SiO2 was only considered
suitable for the first λ/4 layer (see Figs. 4 and 5). An annealing process of 900 C for 1 hour in
nitrogen, was found to be necessary to protect the thermal SiO 2 during the etching process.
PECVD/SiO 2 does not degrade the thickness of the Si substrate and can be deposited on one side
only. It was therefore the chosen process for the subsequent λ/4 layers. For PECVD/SiO 2 layers,
experiments showed that certain properties, especially the thickness of the layers, were changed
after the annealing processes. Adjustments, therefore, had to be made to achieve the design
parameters after annealing. After annealing, all layer characteristics were found to be stable, but
slightly higher tolerances are required for maintaining layer thickness.
For the high index material, polycrystalline silicon with n = 3.4 was chosen as the most available
and suitable material. The CVD deposition process was used to deposit the Si where required in the
reflectance stacks on both sides and the optical properties were characterized again after the
annealing process.
In all of the samples of units with double and triple layer stacks built, thicknesses were attained to
within 7.4% of the design thickness (see Table 3)
6
Table 3. Fabrication technology and tolerances of the dielectric layers and substrate
Bulk Si
deposition
technology
patterning (wet
etch)
selectivity of
wet etch
intrinsic stress
influence of
annealing
(900°C, 1 h, N2)
tolerances of
optical thickness
ë/4 [%], (n x d),
measured
thermal oxide
none
wet thermal
oxidation,
1100 C, both
sides
KOH 30%, 80 C, buffered HF
solution, via
via oxide or
photo resist mask
nitride mask
high for SiO2,
high for Si,
Si3N4
polysilicon,
Si3N4
considerable,
> 300 MPa
none
none
± 0.25
± 1.5
PECVD oxide
Polysilicon
(non-doped)
PECVD process, CVD process,
650 C, both sides
350 C, single
side
buffered HF
solution, via
photo resist mask
high for Si,
polysilicon,
Si3N4
influenced by
deposition
parameters, low
shrinkage of
thickness (5%)
HNO3/HF/H2O,
via oxide mask
± 2.3
± 7.4
high for SiO2,
Si3N4
considerable,
< 200 MPa
shrinkage of
thickness (0.5%)
Further calculations (Fig. 8) using thin film software show that this deviation from the design
thickness, will only affect the reflectivity at the corners of the FPI tuning range but not in the range
of λ0± 0.5 µm .
Fig. 8. Calculation result of reflectance, three quarter wavelength stacks including tolerances given
in Table 3
5. MECHANICAL DESIGN
The movable mirror carrier consists of wafers 2 and 3. Each wafer is elastically suspended by four
diagonal bending beams located in the corners of each wafer (Fig. 9a). This arrangement in
combination with a parallel spring suspension (Fig. 9b) results in a setup of eight diagonal bending
beams that will provide the necessary vertical movement and the necessary rigidity to minimize any
7
tilting of the movable mirror carrier. The center of gravity of the combined carrier was designed to
be in the middle plane between the two wafers in order to prevent tilting by gravity. The four fixed
electrodes at the top side of layer 4 surrounding the mirror are used for electrostatic driving and
capacitive detection of the cavity spacing (Fig. 9c) The electrodes are separately wired to the
electronics so as to provide the opportunity to detect and remove any tilt of the movable mirror. The
outer movable parts, of wafers 3 and wafer 2, are used as movable electrodes. A negative bias
voltage is applied to the fixed electrodes of wafer 4 and a positive bias voltage to wafer 1, the
movable mirror can be actuated by applying a voltage in the range between these bias voltages to it.
a) SEM picture of wafers 2 and 3
b) parallel spring suspension
c) layout of the
electrodes
Fig. 9 Design of movable mirror carrier and fixed mirror carrier with electrodes
fixed
The spring mass system and the electrode spacing have been dimensioned to provide the full span
of displacement necessary for tuning the FPI between the design λmax and λmin wavelengths given
by Table 2. A larger gap size than the cavity gap was chosen in order to null the electrostatic pull
which results in a 33% deflection in the electrode gap when no voltages are applied. The electrically
conducting polycrystalline silicon layers of the thin film mirror stacks are connected to wafers 3 and
4 respectively to keep these layers free of electrostatic charges.
6. FABRICATION TECHNOLOGY
Double side polished silicon wafers 4” in diameter with a thickness of 300 µm were processed to
form the necessary mirror and electrode carriers. For wafers 3 and 4 that require high transmission
in the IR, lightly doped, high resistivity (10-40 ohm· cm) silicon was used. Silicon of this resistivity
is readily available, of very good quality and can be polished to very tight thickness tolerances
(TTV<1 µm). Wafers 1 and 2 need to have good conductivity and do not have an optical function
therefore silicon with a resistivity of 0.01 to 0.05 ohm· cm was used.
Well established silicon bulk technology processes, in combination with direct wafer bonding, are
used to pattern the wafers and to assemble the FPI. Direct bonding processes can be applied to
surfaces with or without thermal oxide layers, at high or low temperatures 9. No other intermediate
layers are necessary thus allowing necessary adjustments of the small gaps to be done with very
good accuracy.
The processes required to complete wafers 3 and 4 involve both mechanical patterning necessary
for the electrodes, springs and gaps, as well as those for producing the required dielectric layers for
the mirrors. Considerable thought was given and experimentation was done to arrive at the final
processing sequence, for wafers 3 and 4, described in detail in Table 4.
It was found that the dielectric materials in the reflectance stacks could not withstand the relatively
long wet etch process required to remove 240 µm of silicon ( using a 30% KOH solution at 80 C ).
Accordingly the processing of wafer 3 involves first the thermal deposition of a quarter wave layer
of SiO2 that does withstand the wet etching through a nitride mask. The wafer then undergoes the
wet etching process that results in the 60 µm thick membrane that can be further processed using
lithography, and the reflectance stacks are then deposited. Finally, the springs are etched using a
8
low stress PECVD nitride mask layer. The four springs have a 45 degree orientation with respect to
the wafer flat and are defined by {100} planes, which have equal etch rates in vertical and lateral
directions. Etching is continued until a spring width of 100 µm is reached. This can easily be
verified and measured using a microscope. A very well defined geometry of the springs with nearly
perpendicular and flat side walls can be attained by this process. The springs in wafer 2 are
fabricated using the identical process.
Careful bonding of wafers 2 and 3 results in a parallel spring suspension (See Fig. 9). For wafer 4,
oxide masks are first used in a wet etch process to define the necessary electrostatic and optical
cavity. The mask layer is then removed and thermal SiO2 is grown to form the bottom λ/4 layer.
Since this layer also provides the bond surface it is then protected with a nitride layer. The λ/4 wave
stacks are then deposited and patterned as in wafer 3. Metallic (Al) electrodes, wire bonding pads
and an aperture stop are then sputtered on to the wafer. The assembly process of the FPI starts with
the bonding of the wafers 2 and 3 as shown in Table 5. Wet-chemical cleaning ( RCA )is used for
surface activation and optical fiducial marks provide a means to align the wafers to within an
accuracy of about 5 µm. Prior to bonding, wafers 2 and 3 are aligned under slight mechanical
pressure, and the alignment is checked by transmission of infrared light (Fig. 10a). Once alignment
is confirmed, bonding material is applied to one side of the wafer frame and the assembly
undergoes an annealing process at 900 C to cure the bond. Prior to simultaneously bonding wafers 1
and 4 to the wafer 2/3 assembly, special pre-treatment and low temperature annealing must be
applied because of the Al pads on wafer 4. Oxygen plasma activation or rinsing in concentrated
nitric acid can be used as well. The alignment prior to bonding can be done using an optical
fiducial mark system (two step alignment) or simply by using mechanical alignment pins. After
pressing all the wafers into contact with a small force, the entire assembly undergoes an annealing
process at 400 C for several hours. A bond strength of about 50% of that at the full curing
temperature is attained 10. A selective sputter process through a hard mask is applied to create the
necessary wire bond pads on wafers 1, 2, and 3 and the entire assembly is diced into chips. Fig. 10b
shows a view of a test chip after dicing.
9
Table 4. Fabrication technology of wafers 3 and 4 (sketches, not to scale)
Technology flow of wafer 3
Deposition and patterning of ë/4-layer:
thermal oxide
Technology flow of wafer 4
Si wet etching of a part of the optical gap using an
oxide mask
Deposition and patterning of a two-step nitride Si wet etching of optical and electrostatic gap to
final thickness, oxide mask wet etching, Deposition
layer with reoxide layer in between,
Si wet etching (240 µm) to 60 µm membrane
of ë/4-layer: thermal oxide
Nitride wet etching, deposition of PECVD oxide on Deposition and patterning of a nitride layer using
top as an etch stop for poly-Si
reoxide layer
Deposition and patterning of ë/4-layers: poly-Si, Deposition and patterning of ë/4-layers: poly-Si,
PECVD oxide, poly-Si using another PECVD oxide PECVD oxide, poly-Si using another PECVD oxide
as a mask
as a mask
Oxide wet etching (mask layers), Deposition of Oxide wet etching, nitride wet etching
PECVD nitride on both sides, patterning and
(mask layers)
Si wet etching (springs, perforation area)
Nitride wet etching, thin oxide wet etching, wafer Sputter deposition and patterning of Al layers
cleaning for bonding
(electrodes, wire bonding pads on top, aperture stop
on backside)
10
Table 5. Concept of direct wafer bonding
First mounting step: direct bonding of wafers 2 and Second mounting step: direct bonding of wafers 1
3
and 4 simultaneously to the compound
mechanical pressure
mechanical pressure
1
3
2
2
3
4
a) IR transmission picture of wafers 2 and 3 after
bonding, arrows mark the bonded regions
b) SEM view of test chip after dicing (without wafer
1)
Fig. 10. Pictures of fabricated prototypes
7. RESULTS
The FPI has been characterized electrically, mechanically and optically. The capacitance of the
electric field between the fixed electrodes of wafer 4 and the movable electrode of wafer 3 and the
corresponding displacement when a driving voltage is applied was also determined. Because the
silicon substrate of wafer 4 is insulated by a thermally grown SiO2 layer, it is possible to exclude
the capacitance of the electrodes to that substrate to wafer 4 (101 pF – 125 pF each depending on
the wire length between electrode and bond pad) and of wafer 3 to wafer 4 (255 pF) by connecting
to ground of the capacitance meter (HP 4278A). A driving voltage was applied to the fixed
electrodes in order to deflect the movable mirror towards the fixed one during this measurement.
The curves in Fig. 11a show a capacitance change of between 2.91 pF to 3.03 pF depending on the
electrode location and the driving voltage. The deflection (measured curve within Fig. 11 right)
shows the corresponding displacement of the movable mirror towards wafer 4.
11
Mirror displacement [nm]
22
Capacitance [pF]
Electrode 4
20
Electrode 1
18
Electrode 3
16
Electrode 2
14
700
600
500
400
300
200
100
12
2.5
5
7.5
10
Driving voltage [V]
12.5
15
2
4
6
8
10
Driving voltage [V]
12
14
Fig. 11. Result of capacitance measurement of the four separate fixed electrodes and deflection
applying voltage to the driving electrodes
Flatness measurements were done in a customized phase shift interferometer. The flatness of the
mirrors within the optically active area (2200 µm x 2200 µm) of the FPI was measured to be better
than ± 7 nm (Fig 13a). A curvature of less than 0.5% of the design wavelength was achieved. The
tilt due to a possible asymmetric electrostatic force while tuning was measured by subtracting the
topology of the movable mirror from the topology of the fixed mirror. The results depicted in
Figure 13b show a difference in height of about 15 nm across the optical active region. The
transmittance of some initial samples consisting wafers 3 and 4, with two quarter wave reflectance
stacks was measured. The FWHM is about 60 nm with a peak transmittance of about 0.5 (Fig. 14).
These samples however did not have a sufficient antireflection coating and the assumption is that
the single λ/4 antireflection layer is the reason for the relatively low transmittance. Work is
continuing therefore to build units incorporating a multi layer antireflection coating and an active
tilt control. The results of these efforts will be reported in a later technical paper.
Fig. 12. SEM view of the FPI consisting of wafer 3 and wafer 4
12
200
-40
-36
-32
-28
-24
-20
-16
166
-12
-8
-4
0
Height [nm]
132
Height [nm]
98
64
30
-4
-38
-72
-106
-140
Mirror region
Mirror region
Fig. 13. Result of topography measurement by a phase shift interferometer, without deflection (left)
and deviation from straight vertical translation (right)
Transmitance [%]
60
24V 23V
20V 18V 15V 10V
0V
40
20
0
2800
3300
3800
Wavelength [nm]
4300
Fig. 14. Transmittance of the FPI at 2 µm cavity spacing
8. CONCLUSIONS
A FPI fabricated by bulk micro-machining has been presented. Because of the use of thick
(300 µm) mirror carriers it was possible to fabricate very flat mirrors. The mirror tilt and curvature
caused by the deflection of the movable mirror is remarkably low. It has been shown that three
quarter wavelength layer reflectance stacks on silicon substrates are needed and will provide
sufficiently high reflectance within the wavelength range of interest and allow for reasonable
fabrication tolerances. In combination with ongoing efforts to incorporate the parallel spring
suspension design and active tilt control, this should provide units with substantially better in band
transmittance.
13
9. ACKNOWLEDGEMENTS
This research report in this paper was supported by the Saxony State Ministry of Science and Art
contract number 6728/1047. The authors wish to thank Victor Yen for the helpful discussion.
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