Download A Fast, Analytical Estimator for the SEU

Efficient Analytical
Determination of the SEUinduced Pulse Shape
Rajesh Garg
Sunil P. Khatri
Department of ECE
Texas A&M University
College Station, TX
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Radiation
Particle
Strike
What is a radiation particle strike?
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Neutron, proton and heavy cosmic ions
Ions strike diffusion regions
Deposit charge
Results in a voltage spike
Can result in a logical error –
Single Event Upset (SEU) or
Soft Errors
Radiation particle strike is modeled by a current
pulse as
Q
t / t
iseu (t ) 
(e  t / t a  e b )
(t a  t b )
where: Q is the amount of charge deposited
ta is the collection time constant
tb is the ion track establishment constant
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Outline
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Introduction
Previous Work
Approach
Classification of Radiation Particle Strikes
 Our Model
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Experimental Results
Conclusions
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Introduction
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Modern VLSI Designs
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Single Event Upsets (SEUs) or Soft Errors
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Vulnerable to noise effects- crosstalk, SEU, etc
Troublesome for both memories and combinational logic
Becoming increasingly problematic even for terrestrial
designs
Applications demand reliable systems
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Need to efficiently design radiation tolerant circuits
Selectively harden sensitive gates in a circuits
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Gate which significantly contribute to soft error failure rate of
circuit
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Introduction
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3 masking factors determine sensitivity of gates
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Logical and temporal can be obtained without
electrical simulations
Electrical masking need electrical simulations
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Logical, temporal and electrical masking
Depends upon on the electrical properties of all gates
on sensitized path from gate to primary outputs (POs)
Important to consider these factors for efficient
circuit hardening
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Need efficient analysis and simulation approaches
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Analyze circuits early in design flow
Based on the results of the analysis, we can efficiently
achieve required tolerance while minimizing overheads
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SEU Simulation and Analysis
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Electrical masking effects can be determined by
SPICE based simulation of SEU events
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Most accurate circuit simulation possible
Computationally expensive
Too many scenarios required to be simulated
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Amount of charge dumped
State of circuit inputs
Need to simulate all nodes in a circuit
Hence we need an efficient and accurate
approach to determine the shape of the radiation
induced voltage glitch
This is the focus of this talk
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Previous Work
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Device-level simulation: Dodd et. al 1994, etc
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Logic-level simulation: Cha et. al 1996
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Accurate but very time consuming
Not helpful for circuit hardening
Abstract transient faults by logic-level models
Gate-level timing simulators are used
Highly inaccurate
Circuit-level simulation:
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Intermediate between device and logic level simulation
However, this is still very time consuming since a large
number of scenarios need to be modeled
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Previous Work
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Shih et. al 1992 solve transistor non-linear differential
equation using infinite power series
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Dahlgren et. al 1995 presented switch level simulator
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Computationally expensive
Electrical simulations are performed to obtain the pulse width of a voltage
glitch for given R and C values of a gate
Pulse width for other R and C values are obtained using linear
relationship between the obtained pulse width and the new
R and C values
Cannot be used for different values of Q
Mohanram 2005 reports a closed form model for SEU
induced transient simulation for combinational circuits
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Linear RC gate model is used
Ignores the contribution of tb in iseu(t) – we found that this results in 40%
root mean square percentage error in voltage glitch
Both these factors result in higher inaccuracy.
Our approach has a 4.5% error
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Objective
Develop an analytical
model for waveform of a
radiation-induced voltage glitch in combinational
circuits
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Closed form analytical expression for the pulse shape
of voltage glitch
Accurate and efficient
Applicable to
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Any logic gate
Different gate sizes
Different gate loading
Incorporates the contribution of the tb time constant
Can be easily integrated in a design flow
Can be used with a glitch propagation tool to evaluate
the effect (at the circuit Primary Outputs) of a radiation
strike at any internal gate G
So we can find (and harden) sensitive gates in a
design
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Our Approach
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Consider a radiation particle strike at the output of INV1
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Implemented using 65nm PTM with VDD=1V
Radiation strike: Q=150fC, ta=150ps & tb=50ps
M1in
inSaturation
Saturation
M1
M1
in
Saturation
M2in
inSaturation
Saturation
M1
Linear
M2
Models Radiation
Particle Strike
in Cutoff
M2’s
Drain-Bulk
M1 and M2 operate in differentM2
regions
during radiation-induced transients
M2
in Cutoff
diode is ON
We estimate the radiation-induced voltage waveform by modeling these regions
INV1 cannot be modeled accurately by a linear RC model (as was done in several
previous approaches)
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Classification of Radiation Strike
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INV1 can operate in 4 different cases
depending upon voltage glitch magnitude
VGM (=Va)
Case 1: VGM ≥ VDD + 0.6V
 Case 2: VDD+|VTP| ≤ VGM < VDD + 0.6V
 Case 3: 0.5*VDD ≤VGM <VDD+|VTP|
 Case 4: VGM < 0.5*VDD
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Different analytical models are applicable to different
cases to compute pulse waveform of the voltage glitch
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Model Overview
Given a gate G, its input
state, the gates in the fanout
of G and Q, ta and tb
Cell library data Iout(Vin,VDS)
for VGS=1 and 0, CG and CD
Determine the value of VGM
using gate current model for
Vdsat ≤ Va ≤ VDD – V|TP|
No voltage
glitch
Yes
No
If Case==4
Yes
If Case==3
Use Case 3 equations
to estimate the shape
of voltage glitch
No
Determine the value of VGM
using gate current model for
Va ≥ VDD – V|TP|
Use Case 1 equations
to estimate the shape
of voltage glitch
No
Yes
If Case==2
Use Case 2 equations
to estimate the shape
of voltage glitch
Voltage Glitch Magnitude (VGM)
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Load current model of INV with input at VDD
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Differential equation for radiation induced voltage transient
at output of INV1
(1)
Va(t)
Green  Known
Yellow  Unknown
VGM
Again
Integrate
integrate
Equation
Equation
1 from
1 with
Now
V
=
V
(T
)
GM ) and
initial condition GM
(Vdsata, T1Vsat
(0, 0) to (Vdsat, T1sat)
with I Va  K
DS Va
3  K 4  VDS
with I DS  VDS / Rn
Vdsat
Obtain TVGM by
differentiating Va(t) and
solving
(t)/dt
0
If VGM > 0.5*VDD
then dV
there
is a= glitch
Solve for T1sata
T1sat
TVGM
t
If 0.5*VDD ≤ VGM < VDD + |VTP| then Case 3 is applicable otherwise need to resolve
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between Case 1 and Case 2
Derivation for Case 3
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For Case 3: 0.5*VDD ≤ VGM < VDD + |VTP|
PMOS transistor never turns ON
Already know voltage
Va(t)
expressions for time intervals
V
(0 ,T1sat) and (T1sat ,T2sat)
Green  Known
Yellow  Unknown
GM
(1)
Vdsat
Integrate Equation 1 from
T1sat
TVGM
with (Vdsat, T2sat) as initial
condition with
T2sat
t
Va
I DS
 VDS / Rn
Now, the voltage expression is available
for t = T2sat to infinity also
Solve for T2sat
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Resolving Between Cases 1 and 2
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VGM > VDD + |VTP|
Need to re-compute VGM to resolve
between Cases 1 and 2
Va(t)
V
Find T1P when
VDD + |V |
Va(t) = VDD + V|TP|
Green  Known
Yellow  Unknown
GM
TP
Integrate Equation 1 from
Now VGM = Va(TVGM)
Vdsat
with (VDD+V|TP|, T1P) as
initial condition with
Va
I DS
 K 5  K 6 VDS
T1sat
T1P
TVGM
t
Obtain TVGM by
If VDD + V|TP| ≤ VGM <VDD
+ 0.6 then Case
is
differentiating
Va(t) 2and
Solve for T1P
applicable otherwise Case
1 is applicable
solving
dVa(t)/dt = 0
*Details can be found in the paper
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Derivation for Case 2
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For Case 2: VDD + V|TP| ≤ VGM < VDD + 0.6
Diode never turns ON
Green  Known
Already know voltage expressions Va(t)
Yellow  Unknown
for time intervals (0 ,T1sat),
V
(T1sat ,T1P) and (T1P ,T2P)
VDD + |V |
Solve for T2P
Integrate
Equation
from, T2 )
Also
known
for 1(T2
V
P
sat
with (VDD+V|TP|, T1P) as
Solve
for T2sat
V
initial condition with I DS  K 3  K 4  VDS
T1
t
TV
T1
T2
T2
Now integrate Equation 1 with
initial condition (Vdsat, T2sat) similar
to Case 3
Solve for T2
GM
TP
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dsat
a
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sat
P
GM
P
P
Solve for T2sat
sat
Derivation for Case 1
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For Case 1: VGM ≥ VDD + 0.6V
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Diode turns ON and clamps the node voltage
to VDD + 0.6V
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Derivation is similar to Case 2
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For (T1P, T2P) the voltage expression is modified
to min(VDD + 0.6, Va(t))
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Voltage expression for other time intervals are
same as that of Case 2
Experimental Results
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Implemented our model in Perl
Applied our model to INV, NAND2 and NOR3
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For each of these gates, we applied our model
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Using 65nm PTM model card with VDD=1V
Characterized each gate for IDS, CG and CD
For different values of Q, ta and tb
Different gate sizes and loads
Our model is ~275X faster compared to SPICE
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Results could be improved if implemented in a
compiled language
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Experimental Results
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Experimental Results
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Root mean square percentage (RMSP) error for 3X gates
for Q=150fC, ta=150ps and tb = 50ps
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Experimental Results
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RMSP error averaged over all possible input states for
different gate sizes for Q=150fC, ta=150ps and tb = 50ps
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Average RMSP error of our model is 4.5%
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Much lower than 40% error of the model by Mohanram 2005
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Conclusion
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We presented an analytical model to estimate the
shape of the radiation-induced voltage glitch
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Our model is accurate and efficient
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Can be used with glitch propagation tools to estimate
the voltage glitch at POs
Based on this, sensitive gates can be identified and
hardened to improve the radiation tolerance of the
design
This can be done early in the design cycle
RMSP error is 5% compared to SPICE
Our method is 275X faster than SPICE
Our model gains accuracy
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By using the load current model (and avoiding a linear
RC model for the gate)
By including the contribution of tb
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Thank You
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