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EMBEDDED SYSTEMS What in class? 1.1 Definition • Definition for: embedded system • A combination of hardware and software which together form a component of a larger machine. • An example of an embedded system is a microprocessor that controls an automobile engine. • An embedded system is designed to run on its own without human intervention, and may be required to respond to events in real time. • Source: www.computeruser.com/resources/dictionary Applications Areas Application Areas • TV • stereo • remote control • phone / mobile phone • refrigerator • microwave • washing machine • electric tooth brush • oven / rice or bread cooker • watch • alarm clock • electronic musical instruments • electronic toys (stuffed animals,handheld toys, pinballs, etc.) • medical home equipment (e.g. blood pressure, thermometer) •… • [PDAs?? More like standard computer system] Consumer Products Application Areas • Medical Systems – pace maker, patient monitoring systems, injection systems, intensive care units, … • Office Equipment – printer, copier, fax, … • Tools – multimeter, oscilloscope, line tester, GPS, … • Banking – ATMs, statement printers, … • Transportation – (Planes/Trains/[Automobiles] and Boats) • radar, traffic lights, signalling systems, … Application Areas • Automobiles – engine management, trip computer, cruise control, immobilizer, car alarm, – airbag, ABS, ESP, … • Building Systems – elevator, heater, air conditioning, lighting, key card entries, locks, alarm systems, … • Agriculture – feeding systems, milking systems, … • Space – satellite systems, … Application Areas • Facts: – 1997: The average U.S. household has over 10 embedded computers (source: www.it.dtu.dk/~jan) • 1998: 90% Embedded Systems vs. 10% Computers – (source: Frautschi, www.caliberlearning.com) • 2001: The Volvo S80 has 18 embedded controllers and 2 busses (source: Volvo) Automobiles Microcontrollers Microcontrollers • Microprocessor – CPU (on single chip) • Microcontroller • CPU + Timers + I/O (+RAM) (+ROM) • Reduced chip count for board design • Embedded system • Today’s Technology: – Surface Mount Device (SMD) – Ball Grid Array (BGA) Input and Output • Required to communicate with outside world • PC System: – – – – Keyboard Monitor Parallel port (printer port) Serial port + USB • Embedded System: – Sensors (e.g. in automobile: acceleration sensor, seat sensor) – Actuators (e.g. in automobile: valves for airbags) Input and Output • Input / output device implementation can be: • • Memory-mapped • • I/O mapped (ports) • • DMA (direct memory access) INTRODUCTION TO MSP430 MICROCONTROLLERs Outline • • • • • • • • • Key Features of MSP430 MSP430 CPU Architecture MSP430 CPU Registers Memory organization Addressing Modes Instruction Set LPM Interrupts, I/O & Timers USCI Key Features of MSP430 • a low power Microcontroller released by Texas Instruments in the late 1990s. • a 16-bit RISC based mixed signal processor. • with a set of intelligent peripherals like I/O, Timers ADC, DAC, flexible clock and USCI • low cost • lowest power consumption • Ultra low power optimization extends battery life • multiple low power modes of operation Contd.. Extensive interrupt capability relieves need for polling Prioritized nested interrupts Seven source-address modes Four destination-address modes Only 27 core instructions and 24 Emulated Instructions Large register file Efficient table processing Fast hex-to-decimal conversion contd.. • MSP430 requires 0.1 μ A for RAM data Retention, 0.8 μ A for RTC mode operation 250 μA /MIPS for active mode operation. • Low operation voltage (from 1.8 V to 3.6 V). • Zero-power Brown-Out -Reset (BOR) MSP430 CPU ARCHITECTURE • The MSP430 architecture. CPU has a 16-bit RISC • 16-bit data bus and 16-bit address bus • 7 addressing modes • reduced instructions set with instructions • Register file consists of 15 registers only 27 Contd.. • 64 K memory with Flash ROM and RAM • Von Neumann architecture with seperate memory address bus (MAB) and memory data bus (MDB) • Instruction Emulation because of availability of Constant Generators Architecture - MSP430 MSP430 CPU Registers • The CPU of MSP 430 includes a 16-bit ALU and a set of 16 Registers R0 –R15.In these registers Four are special Purpose and 12 are general purpose registers . All the registers can be addressed in the same way. The special Purpose Registers are • PC (Program Counter), SP (Stack Pointer) , SR (Status Register) and CGx (Constant Generator) Registers Memory organization • MSP430 consists of 64K memory which includes Flash /ROM and RAM • Memory addresses are 16 bit • Even address access • Includes IV table and SFRs • The MSP430 CPU includes an arithmetic logic unit (ALU) that handles addition, subtraction, comparison and logical (AND, XOR) operations. ALU operations can affect the overflow, zero, negative, and carry flags in the status register. R0: Program Counter (PC) • The 16-bit Program Counter (PC/R0) points to the next instruction to be read from memory and executed by the CPU. The Program counter is incremented by the number of bytes used by the instruction (2, 4, or 6 bytes, always even). It is important to note that the PC is aligned at even addresses, because the instructions are 16 bits, even though the individual memory addresses contain 8-bit values. R1: Stack Pointer (SP) • The Stack Pointer (SP/R1) is located in R1. • Stack can be used by user to store data for later use(instructions: store by PUSH, retrieve by POP) • Stack can be used by user or by compiler for subroutine parameters (PUSH, POP in calling routine; addressed via offset calculation on stack pointer (SP) in called subroutine) Contd.. • Stack can be used by subroutine calls to store the program counter value for return at subroutine's end (RET) • used by interrupt - system stores the actual PC value first, then the actual status register content (on top of stack) on return from interrupt (RETI) the system get the same status as just before the interrupt happened (as long as none has changed the value on TOS) and the same program counter value from stack. R2: Status Register (SR) The Status Register (SR/R2) is a 16 bit register , and it stores the state and control bits. The system flags are changed automatically by the CPU depending on the result of an operation in a register. The reserved bits of the SR are used to support the constants generator. MSP430 CPU block diagram R2/R3: Constant Generator Registers (CG1/CG2) • Depending on the source-register addressing modes (As) value, six commonly used constants can be generated without a code word or code memory access to retrieve them. This is a very powerful feature, which allows the implementation of emulated instructions, for example, instead of implementing a core instruction for an increment, the constant generator is used. R4 - R15: General–Purpose Registers • These general-purpose registers are used to store data values , address pointers, or index values and can be accessed with byte or word instructions. Addressing modes • • • • • • • The MSP430 supports seven addressing modes for the source operand and four addressing modes for the destination operand . They are Register mode Indexed mode Symbolic mode Absolute mode Indirect register mode Indirect auto incrément mode Immediate mode Register Mode • Register mode operations work directly on the processor registers, R4 through R15, or on special function registers, such as the program counter or status register. They are very efficient in terms of both instruction speed and code space. Ex : MOV R4, R5 Move (copy) the contents of source (register R4) to destination (register R5). Register R4 is not affected. Indexed mode • The Indexed mode commands are formatted as X(Rn), where X is a constant and Rn is one of the CPU registers. The absolute memory location X+Rn is addressed. • Indexed mode addressing is useful for applications such as lookup tables Ex : MOV F000h(R5), R4 Move (copy) the contents at source address (F000h +R5) to destination (register R4) Symbolic mode • Symbolic mode allows the assignment of labels to fixed memory locations, so that those locations can be addressed. This is useful for the development of embedded programs. • MOV XPT, YPT • Move the content of source address XPT (x pointer) to the destination address YPT (y pointer). Absolute mode • Similar to Symbolic mode, with the difference that the label is preceded by “&”. The word following the instruction contains the absolute address. X is stored in the next word. Indexed mode X(SR) is used MOV &XPT, &YPT Move the content of source address XPT to the destination address YPT. Indirect register mode • The data word addressed is located in the memory location pointed to by Rn. Indirect mode is not valid for destination operands, but can be emulated with the indexed mode format @(Rn). Here Rn is used as a pointer to the operand. • MOV @(R4), R5 • Move the contents of the source address (contents of R4) to the destination (register R5). Register R4 is not modified Indirect auto increment mode • Similar to indirect register mode, but with indirect auto increment mode, the operand is incremented as part of the instruction. The format for operands is @Rn+. This is useful for working on blocks of data. • Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for byte instructions and by 2 for word instructions. Ex: MOV @R4+, R5 Move the contents of the source address (contents of R4) to the destination (register R5), then increment the value in register R4 to point to the next word. Immediate mode • Immediate mode is used to assign constant values to registers or memory locations. • MOV #E2h, R5 • Move the immediate constant E2h to the destination (register R5). Instruction set • The MSP430 instruction set consists of 27 core instructions. Additionally, it supports 24 emulated instructions. The core instructions have unique op-codes decoded by the CPU, while the emulated ones need assemblers and compilers to generate their mnemonics. • There are three core-instruction formats: • Double operand (Format I) • Single operand (Format II) • Program flow control – Jump (Format III) Contd.. • The instruction set is orthogonal with few exceptions, meaning that all addressing modes can be used with all instructions and registers. Movement Instructions • There is only the one ‘mov’ instruction to move data. It can address all of memory as either source or destination, including both registers in the CPU and the whole memory map. • Ex : mov . w src , dst Here . w denotes that the operations can use either bytes or words Stack Operations • These instructions either push data onto the stack or pop them off . ex 1: push .w src ; push data onto stack ex 2 : pop .w dst ; pop data off stack. The pop operation is emulated using postincrement addressing but push requires a special instruction because predecrement addressing is not available. Arithmetic and Logic Instructions with Two Operands • add.w src ,dst ; add • addc.w src ,dst ; add with carry • adc.w dst ; add carry bit • sub.w src ,dst ; subtract • subc.w src ,dst ; subtract with borrow • sbc.w dst ; subtract borrow bit • cmp.w src ,dst ; compare , set flags only. The compare operation cmp is the same as subtraction except that only the bits in SR are affected ; the result is not written back to the destination. Arithmetic Instructions with One Operand • All these are instructions are emulated, which means that the operand is always a destination. • Ex: clr.w dst ; clear • dec.w dst ; decrement • decd.w dst ; double decrement • inc.w dst ; increment • incd.w dst ; double increment • tst.w dst ; test (compare with 0) Decimal Arithmetic • These instructions are used when operands are binary-coded decimal (BCD) rather than ordinary binary values. • Ex : dadd.w src , dst ; decimal add with carry. • dadc.w dst ; decimal add carry bit Logic Instructions with Two Operands • The MSP430 has the usual and and exclusiveOR xor instructions but not an explicit inclusiveOR. The and and bitwise test operations are identical except that bit is only a test and does not change its destination. • Ex : and.w src ,dst ; bitwise and . • xor.w src ,dst ; bitwise exclusive or • bit.w src ,dst ; bitwise test , set flags only • bis.w src ,dst ; bit set • bic.w src ,dst ; bit clear Logic Instructions with One Operand • There is only one instruction of this type . invert ‘inv’ instruction , also known as ones complement ,which changes all 0 bits to 1 and 1s to 0. • Ex : inv.w dst ; invert bits Byte Manipulation • These instructions do not need a suffix because the size of. the operands is fixed. • Ex : Swpb src ; swap upper and lower bytes (word only) • Ex : sxt src ; extend sign of lower byte (word only) • The swap bytes instruction ‘swpb’ swaps the two bytes in a word. • The sign extend instruction sxt is used to convert a signed byte into a signed word. Operations on Bits in Status Register • There is a set of emulated instructions to set or clear the four lowest bits in the status register and these can be masked using the constant generator. • Ex: clrc ; clear carry bit. • clrn ; clear negative bit. • clrz ; clear zero bit. • setc ; set carry bit. • setn ; set negative bit. • setz ; set zero bit. • dint ; disable general interrupts. • eint ; enable general interrupts. Shift and Rotate Instructions There are three types of shifts (i) logical shift (ii) arithmetic shift (iii) rotation. They are explained below. Contd.. • Logical shift inserts zeroes for both right and left shifts. • Arithmetic shift inserts zeroes for left shifts but the most significant bit, which carries the sign, is replicated for right shifts. • Rotation does not introduce or lose any bits; bits that are moved out of one end of the register are passed around to the other. • Ex : rla dst ; arithmetic shift left • rra src ; arithmetic shift right. • rlc dst ; rotate left through carry. • rrc src ; rotate right through carry Flow of Control • The most common elementary use of call is for a subroutine that begins at a particular label. • Ex: br src ; branch (go to). • call src ; call subroutine. • ret ; return from subroutine. • reti ; return from interrupt. • nop ; no operation (consumes single cycle) Jumps(Unconditional and Conditional) • jmp fits in a single word, including the offset, but its range is limited to about ±1KB from the current location. • jmp label ; unconditional jump. Contd.. • The conditional jumps are the “decisionmaking” instructions and test certain bits or combinations in the status register. • Ex : jc label ; jump if carry set • jnc label ; jump if carry not set , • jn label ; jump if negative , • jz label ; jump if zero • jnz label ; jump if nonzero. • jge label ; jump if greater or equal , • jl(t) label ; jump if less than Low Power Modes • The MSP430 MCU utilizes six different LowPower Modes, which can disable unused clocks and CPU. This allows the MSP430 to sleep, while its peripherals continue to work without the need for an energy hungry processor. Additionally, the MSP430 is capable of wake-up times below 1 microsecond, allowing the microcontroller to stay in sleep mode longer, minimizing its average current consumption. Contd.. • With the multiple low power modes, there is a notable difference in the amount of power consumed between MSP430 and other microcontrollers. • MSP430 uses up to 70% less power than the PIC24F16KA102 in active mode. In standby mode, the PIC24F16KA102 consumes up to 41% and STM8L151G4 consumes up to 9 times more power than the MSP430. • Multiple low power modes, with flexible clocking system, instant wakeup, and intelligent autonomous peripherals enable true ULP optimization, dramatically extending battery life. Flexible Clocking System • The MSP430 MCU clock system has the ability to enable and disable various clocks and oscillators which allow the device to enter various low-power modes (LPMs). The flexible clocking system optimizes overall current consumption by only enabling the required clocks when appropriate. Contd.. • Main Clock (MCLK) : CPU source that may be driven by the internal Digitally Controlled Oscillator (DCO) up to 25 MHz or with external crystal. • Auxiliary Clock (ACLK) : Source for individual peripheral modules driven by the internal low-power oscillator or external crystal • Sub-Main Clock (SMCLK) : Source for faster individual peripheral modules that may be driven by the internal DCO up to 25 MHz or with external crystal Clock • ACLK: Auxiliary clock. ACLK is divided by 1, 2, 4, or 8 and is software selectable for individual peripheral modules. • MCLK: Master clock. MCLK is divided by 1, 2, 4, or 8 and is used by the CPU and system. • SMCLK: Sub-main clock. SMCLK is divided by 1, 2, 4, or 8 and is software selectable for individual peripheral modules. Power modes • Active Mode : Nothing is turned off (except maybe individual peripheral modules). No power savings. • LPM0 :CPU and MCLK are disabled while SMCLK and ACLK remain active. • LPM1 : CPU and MCLK are disabled, and DCO and DC generator are disabled if the DCO is not used for SMCLK. ACLK is active. Contd.. • LPM2 : CPU, MCLK, SMCLK, DCO are enabled DC generator remains enabled. ACLK is active • LPM3 :CPU, MCLK, SMCLK, DCO are disabled, DC generator is disabled, ACLK is active • LPM4:CPU is disabled, ACLK is disabled, MCLK and SMCLK are disabled DCO’s dcgenerator is disabled Crystal oscillator is stopped Contd.. • It is important to note that the parts of the microcontroller that are shut off, will not operate until they are turned on again by interrupts. CPU Operating modes Interrupts • MSP430 Interrupt structure working • Sources of interrupts are I/O, Timers, reset and external interrupts • Interrupt priorities Interrupt vector Table 11 GPIO • • • • MSP430 I/O Ports 2 8 bit ports port1 and port2 Port1: P1.0 – P1.7 and P2.0 – P2.7 Individual bit configuring as input or output TIMERS • Normally we find two Timers Timer A and Timer B and one Watchdog Timer in MSP430 microcontrollers. • TIMER A: It typically has three channels and is much more versatile than the simpler timers . • Timer A can handle external inputs and outputs directly to measure frequency, time-stamp inputs, and drive outputs at precisely specified times, either once or periodically. There are internal connections to other modules so that it can measure the duration of a signal from the comparator and it can also generate interrupts Timer_A Timer_A is a 16-bit timer/counter with three capture/compare registers • • • • Asynchronous 16-bit timer/counter with four operating modes Selectable and configurable clock source Two or three configurable capture/compare registers Configurable outputs with PWM capability Contd… • Timer B : Is included in larger devices of all families. It is similar to Timer A with some extensions that make it more suitable for driving outputs such as pulse-width modulation. But it lacks a feature of sampling inputs in Timer A that is useful in communication. Watchdog Timer • The main purpose of the watchdog timer is to protect the system against failure of the software, such as the program becoming trapped in an un-intended, infinite loop. Left to itself, the watchdog counts up and resets the MSP430 when it reaches its limit. • The operation of the watchdog is controlled by the 16-bit register WDTCTL. It is guarded against accidental writes by requiring the password WDTPW = 0x5A in the upper byte. USCI • MSP430 is provided with a universal serial communication interface • For serial transmission and reception MSP430x5xx Block Diagram GPIO: • Independently programmable. • Any combination of input, output, interrupt and peripheral is possible. • Each I/O has an individually programmable pull up/pull down resistor. • Many devices can lock pin values during low power mode. • Some devices support touch-sense capability built in to pins. • This GPIO can consist of unified clock system and also having ACLK, SMCLK, and MCLK. • • • • • • • • Timer_ A: It is 16-bit timer/counter Multiple capture/compare registers Generates PWM and other complex waveforms & interrupts Directly trigger GPIO, DMA, and ADC etc. Timer_ B: Multiple capture/compare registers Generates PWM and other complex waveforms & interrupts Directly trigger GPIO, DMA, ADC, and PWM. Timer_ D: Same as B ; with hi-res timin Hardware then performs the following steps to launch the ISR: • Any currently executing instruction is completed if the CPU was active, when the interrupt was requested. MCLK is started if the CPU was off. • The PC, which points to the next instruction is pushed to the stack. • The interrupt with the highest priority is selected if simple interrupts re waiting for service. • The interrupt request flag is cleared automatically for vectors that have a single source. Flags remain set for servicing by software, which applies to the example of TAIFG. • The SR is cleared, which has two effects: • First, further maskable interrupts are disabled because the GIE bit is cleared, Non- Maskable interrupts are remain active. • Second, it terminates any low-power mode. As explained in the section, “Low-power modes of operation” (the SCGO bit is not cleared on the MSP430x4xx family, which means that the frequency-locked loop is not automatically reactivated). Non maskable interrupts: • These are a few small differences in the handling of non maskable interrupts compared with the maskable type. • All the sources share a single vector, which has the highest address and therefore the highest priority except for the reset vector. • Three modules can request a non maskable interrupt. Oscillator Faults:• A failure of a clock,MCLK is particular iks crippling.the clock module detects and recovers from the most likely fault,The failure of an oscillator relies on a vulnerable external crystal. • Each oscillator has flag which raised to indicate a fault,which also sets the OFIFG bit in interrupt flag register IFG 1. • The values are stored in segment A, of the information memory,which is locked by default against programming and erasing... Frequency-Locked Loop,FLL:• The MSP430X4XX family has more sophisticated FL++ clock module. • LFXT1 and XT2 and some more are similar to MSP430F2XX but registers and bits have different names. • the load capacitance for low-frequency crystal is controlled by XCAPXPF bits in FLL-CTLO register • There are no dividers for internal clocks but the external signal from ACLK can divide. • The main difference is of course frequency-locked loop. • This hardware aims to lock the frequency of DCO to LFXT1. • This intern requests a Nonmaskable interrupt if it has enable. • Its also switches MCLK to DCO if it was not already used, which ensures CPU remains active. • Users software can then take appropriate action WATCHDOG TIMER: • The main purpose of the watchdog timer is to protect the system against failure of the software, such as the program becoming trapped in unintended, infinite loop. • Left to itself the watchdog counts up and resets the MSP430 when it reaches its limit. • The code must therefore keep clearing the counter before the limit is reached to prevent a reset. • The operation of the watchdog is controlled by the 16-bit register WDTCTL. • It is guarded against accidental writes by require the password WDTPW=0X5A in the upper byte. • A reset will occur if a value with an incorrect password is written to WDTCTL. • This can be done deliberately if you need tom reset the chip from software. • Reading WDTCTL returns 0X69 in the upper byte. So reading WDTCTL and writing the value back violates the password and causes a reset. Watch dog timer register LOW POWER MODES OF MSP 430 • The MSP430 MCU utilizes six different Low-Power Modes, which can disable unused clocks and CPU. • This allows the MSP430 to sleep, while its peripherals continue to work without the need for an energy hungry processor. • Additionally, the MSP430 is capable of wake-up times below 1µs, allowing the microcontroller to stay in sleep mode longer, minimizing its average current consumption. • The low power modes can be switched by programming the status register. • In addition to the low power modes MSP 430 can also program two other low power modes as LPM 3.5 and LPM 4.5. • These LPM 3.5 and LPM 4.5 are present in microcontrollers which consists the inbuilt voltage regulator. LPM0: CPU and MCLK are disabled while SMCLK and ACLK remain active, I<=85µA. DCO in active. LPM1: CPU and MCLK are disabled, and DCO and DC generator are disabled if the DCO is not used for SMCLK. ACLK is active. LPM2: CPU, MCLK, SMCLK, DCO are disabled, DC generator remains enabled. ACLK is active LPM3: CPU, MCLK, SMCLK, DCO are disabled, DC generator is disabled, only ACLK is active, I<=1µA. BLOCK DIAGRAM OF TIMER BTCNT 1:• This control BTCNT1 takes the input ACLK and provides the clock for the LCD module. • The two BTFRFQ bits selects the value of fLCD (from FACLK/256 to Falck/32 in powers of 2). • LCD_A controller does not need a clock BTCNT1. • It functions as counter only. • BTCNT2 can be used independently where BTSSEL bit selects the clock from ACLK or SMCLK. • For longer intervals, BTCNT2 is clocked from output of BTCNT1 at frequency of Faclk/256. • The bit BTDIV is used to cascade the counters. • BTHOLD bit stops BTCNT2, but stops only BTCNT-1 when BTDIV is also set. • BTCNT2 provides no output but it sets the BTIFG flag when frequency is determined by BTIPX • The frequency ranges from fclk2/256 to fclk/2 of the clock input BTCNT2. Remote Controller of Air Conditioner Using MSP430 • System Description: • This board demonstrates an ultra-low power, general purpose, infrared remote controller solution. • The board uses a FRAM-based MCU MSP430FR4133, which supports features such as real time clock, button scan, infrared encoding, LED backlight, and LCD display. MSP430FR4133: • The features of MSP430FR4133 are • 16-bit RISC architecture up to 16 Mhz • Wide supply voltage range from 1.8 V to 3.6 V • 64-Pin/56-Pin/48Pin TSSOP/LQFP package options • Integrated LCD driver with charge pump can support up to 4x36 or 8x32 segment LCD • Optimized 16-bit timer for infrared signal generation • Low power mode (LPM3.5) with RTC on:0.77 uA • Low power mode (LPM3.5) with LCD on: 0.936 uA • Active mode: 126 uA/MHz • 10^15 write cycle endurance low power ferroelectric RAM (FRAM) can be used to store data • 10-channel, 10-bit analog-to-digital converter (ADC) with built-in 1.5 V reference for battery powered system • All I/Os are capacitive touch I/O Circuit Design • A 4x28 segment LCD is directly connected to the MSP430FR4133 LCD driver pins. • A 4x4 matrix is used to detect 15 buttons. The matrix columns are connected to interrupt-enabled GPIOs (P1) to wake up the MSP430FR4133 from low power mode. • MCU internal pull up/pull down resistors are used as button scan matrix pull up resistors. No external resistor is needed for button detection, and no external circuit is needed for battery voltage detection. • A 32.768 KHz watch crystal serves as the MCU FLL and RTC clock source. • Two chip capacitors, C4 and C6, are used as the crystal loading capacitor. Designers must choose C4 and C6 values carefully according to crystal specification. • Software Description: • The software implements an interrupt-driven structure. In the main loop, the MCU stays in LPM3.5 mode. • Interrupts from the button, RTC, and timer wake up the MCU for task processing. • Inputs from the button are processed in task Key Process (), which handles system status and generates the content for the LCD display and infrared signal. • RTC generates a 3S interval interrupt to inform the system of battery voltage measurement. • Infrared Signal Generation: • There are several kinds of infrared modulation protocols in the industry. This design illustrates pulse distance protocol with data frame format, the most commonly-used format for air conditioner remote controllers. • The space’s width distinguishes logic 1 and logic 0 respectively. The carrier-modulated pulse width is constant. • In this design, space length for 1 is 1690 uS, and 560 uS for digit 0. Modulated pulse width is 560 uS. • TA1 is used to generate an envelope waveform, and each pair of carrier-modulated pulse and space must update the CCR0 and CCR2 once. • The CCR0 depends on the carrier-modulated pulse period plus the space period, while the CCR2 depends on the carrier-modulated pulse period. • To generate 38 kHz carrier with ¼ duty, CCR0 and CCR2 of TA0 are configured according to SMCLK. For example, with a 4 MHz SMCLK, CCR0 and CCR2 are individually configured to be 105 (4,000/38) and 26 (4,000/38/4). Figure 7 shows how the duty setting works. Real Time Clock (RTC): • The basic functions of a real time clock (RTC) are used to display the current time and an alarm clock with calendar functions. • The alarms are basically a CPU interrupts. • Most of the RTC are designed for ultra low power. • The RTC is driven with 32 KHz clock. • There are various RTC like • I) RTC_A (uses ACLK or SMCLK). • II) RTC_B (uses LFXT (32 KHz crystal)). • RTC_A is used on F5529 and provides to use external crystal or internal (on chip) REFO. • RTC_B is used on FR5969 which is driven with Low frequency external crystal. RTC Interrupts: Alarm (RTCA): Generate interrupt if match between time register and alarm register for Minutes Hours Day of the week Day (of the month) Interval timer (RTCTEV): Generates when RTC count events occur. Interrupt can happen for each minute, each hour, midnight, & noon. Pre scalar 0(RT0PS) & 4) Pre scalar 1(RT1PS) : RTC has a capable of generating the time based interrupts from the pre scalar count value when clock rate is divided by 2, 4, 8, 16, 32, 64, 128, 256. Ready (RTCRDY) : Used to tell or notifies the CPU to safe read or write the RTC registers. Oscillator fault: Generates when CPU is running in LPM 3.5, which cannot detect oscillator. Then this interrupt wakes up the CPU and notify that the fault occurred at oscillator. Additional features of RTC: • All RTC’s work in LPM 3 • The RTC_B and RTC_C can be operates in LPM 3.5 due to RTC_B & RTC_C are access the LF crystal directly. • RTC_B / RTC_C provide BCD conversion • RTC_A can be used as 32-bit counter (rather than calendar mode). • Counter mode generates an overflow interrupts. ADC A Low-Power Battery less Wireless Temperature and Humidity Sensor with Passive Low Frequency RFID • Introduction: • Several applications require hermetically sealed environments, where physical parameter measurements such as temperature, humidity, or pressure are measured and, for several reasons, a battery-less operation is required • In such applications, a wireless data and power transfer is necessary • This can be implement with wireless humidity and temperature sensor comprising a SHT21 from Sensrion, a MSP430F2274 microcontroller, and a TMS37157 PaLFI (passive low-frequency interface). • The complete power for the wireless sensor and the MSP430F2274 is provided by the RFID base station (ADR2) reader included in the eZ430- TMS37157 • The application is divided in four steps: • Charge phase: Generate an RF field of 134.2 kHz from the ADR2 reader to the wireless sensor module to charge the power capacitor. • Downlink phase: Send command or instruction to wireless sensor to start measurement. • Measurement and recharge phase: Trigger measurement of temperature, recharge the power capacitor on the sensor device, and trigger humidity measurement. • Uplink phase: Send measurement results via RF interface (134.2 kHz) back to ADR2 reader. • Hardware Description: • MSP430F2274: • The MSP430F2274 is a 16-bit microcontroller from the 2xx family of the ultra-low-power MSP430™ family • The supply voltage for this microcontroller ranges from 1.8 V to 3.6V. The MCU is capable of operating at frequencies up to 16 MHz. • It has internal VLO that operates at 12 kHz at room temperature • It has two timers (Timer_A and Timer_B), each with three capture/compare registers. • An integrated 10-bit analog-to-digital converter (ADC10) supports conversion rates of up to 200 ksps. • The current consumption of 0.7 mA during standby mode (LPM3) and 250 mA during active mode makes it an excellent choice for battery-powered applications. • TMS37157 PaLFI: • The TMS37157 PaLFI(Passive low frequency ) is a dual interface passive RFID product from Texas Instruments. The device can communicate via the RF and the SPI (wired) interfaces. • It offers 121 bytes of programmable EEPROM memory. • The complete memory can be altered through the wireless interface, if the communication/read distances between the reader antenna and the PaLFI antenna are less than 10 cm to 30 cm. • A microcontroller with a SPI interface has access to the entire memory through the 3-wire SPI interface of the TMS37157. • If the TMS37157 is connected to a battery, it offers a battery charge function and a battery check function without waking the microcontroller, and consumes less power of about 60 nA in standby mode and about 70 μA in active mode. • The PaLFI can completely switch off the microcontroller, resulting in an ultralow power consumption of the complete system. • SHT21 Humidity and Temperature Sensor: • The extremely small SHT21 digital humidity and temperature sensor integrates sensors, calibration memory, and digital interface on 3x3 mm footprint. • This results in cost savings, because no additional components are need and no investments in calibration equipment or process are necessary. • One-chip integration allows for lowest power consumption, thus enabling energy harvesting and passive RFID solutions • Interface Between MSP430F2274 and TMS37157 PaLFI Implementing and Programming UART Interface Using MSP430: • In MSP430 serial communication is handled by an on chip peripheral called USCI (Universal Serial Communication Interface). It has two USCI modules names as USCI_A0 and USCI_B0 for handling multiple communication formats. USCI_A0 can be configured to handle IrDA, SPI and UART while USCI_B0 can handle SPI and I2C. • Here we are configure USCI_A0 in MSP430G2553 to handle asynchronous serial communication or commonly known as UART mode. The UART mode uses two pins to transmit (UCA0TXD) and receive data (UCA0RXD). UART PROTOCOL • The TMS37157 is connected to the MSP430F2274 through a 3-wire SPI interface. • The BUSY pin indicates the readiness of the TMS37157 to receive the next data byte from the MSP430F2274. • The PUSH pin is used to wake up the PaLFI from standby mode so that the MSP430F2274 can access the EEPROM of the PaLFI. • CLKAM is used for the antenna automatic tune feature of the PaLFI target board. • Interface Between MSP430F2274 and SHT21: • I2C is used to connect both devices. • The MSP430F2274 contains two communication modules. One is used as UART connection to a host PC, the other one is used to communicate to the TMS37157 • Hardware Changes to Original PaLFI Board • Program Flow • Figure 8 shows the main program flow for the firmware. INTERNET OF THINGS (IOT):- 1. Perception Layer:• Perception layer in an IOT can be divided into perception components layer perception network layer and perception coordination layer. • The perception component layer can be abstracted as sensing components. Sensing components include RFID, barcodes, sensors etc and actuator components include value, switch, relay etc. • Sensing components and actuator components help in realizing signal acquisition and control functions. • Perception network layer includes various buses such as the control area network (CAN) bus, RS-485 bus or wireless networks such as Wireless Sensor Network (WSN), Bluetooth, Wi-Fi etc. It realizes communication connection between perception components or between perception components and IOT gateway. 2. Network Layer:The network layer is responsible for delivering the sensor data from source to destination across multiple links. IP (Internet Protocol) is the network layer protocol of the internet because it provides unique IP address to its devices, the routing of data is done through the network. These devices carry IP packets from one device to another device. 3. Application Layer:The application layer governs the data flow and is responsible for data formatting. The importance of this layer for the IOT is that it has the ability to provide high quality smart services to meet customers’ needs. Adding Wi-Fi capability to Microcontroller:- Features:CC3100 Simple link Wi-Fi consists of Wi-Fi network processor and power management subsystems. Wi-Fi certified chip. Wi-Fi network processor subsystem Featuring Wi-Fi internet-on-a-chip. Dedicated ARM MCU completely offloads Wi-Fi and internet protocols from the external microcontroller. Clock Source 40.0 MHz crystal with internal oscillator. 32.768 KHz crystal or external RTC clock. Package and Operating Temperature 0.5mm pitch, 64pin, 9mm x 9mm QFN. Ambient temperature range: -400C to 850 C. Implementing Wi-Fi Connectivity in a Smart Electric Meter System Description: • A smart meter is an electronic device that records consumption of electric energy in intervals of an hour or less and communicates that information at least daily back to the utility for monitoring and billing. • Smart meters enable two-way communication between the meter and the central system. Unlike home energy monitors, smart meters can gather data for remote reporting. • The e-meter SoC uses the MSP430F67791 device. These devices find their application in energy measurement and have the necessary architecture to support them. • The F677x has a powerful 25-MHz CPU with MSP430CPUx architecture. The analog front-end consists of up to seven independent 24-bit sigma-delta (ΣΔ) analog-to digital converters (ADC). • A 32×32-bit hardware multiplier on this chip can be used to further accelerate math intensive operations during energy computation. • The software energy library supports calculation of various parameters for up to 3-phase energy measurement. • The key parameters calculated during energy measurements are: RMS current and voltage, active and reactive power and energies, power factor, and frequency. • These parameters can be viewed either from the calibration GUI, LCD, or through Wi-Fi using a standard web browser. • For the SimpleLink Wi-Fi transceiver, the CC3100 is used. This simplifies the implementation of Internet connectivity. • The CC3100 device integrates all protocols for Wi-Fi and Internet, which greatly minimizes host MCU software requirements. • Peripherals Setup: • The major peripherals are the 24-bit sigma delta (ΣΔ24_B) ADC, clock system, timer, LCD, watchdog timer (WDT), and so on. ΣΔ24 Setup • The F677x family has up to seven independent sigma delta data converters. For a 3-phase system, at least six ΣΔs are necessary to independently measure three voltages and currents. • The clock to the ΣΔ24 (the modulation frequency, or fM) is derived from system clock configured to run at 16 MHz. The following are the ΣΔ channels associations: • A0.0+ and A0.0– Voltage V1 • A1.0+ and A1.0– Voltage V2 • A2.0+ and A2.0– Voltage V3 • A4.0+ and A4.0– Current I1 • A5.0+ and A5.0– Current I2 • A6.0+ and A6.0– Current I3 Optional neutral channel can be processed via channel A3.0+ and A3.0–. Real-Time Clock (RTC_C): • The RTC_C is a real-time clock module that is configured to give precise one-second interrupts. Based on these one-second interrupts, the time and date are updated in the software as necessary. • LCD Controller (LCD_C): • The LCD controller on the MSP430F677X can support up to 8-mux displays and 320 segments, and is also equipped with an internal charge pump that can be used for good contrast. In the current design, the LCD controller is configured to work in 4-mux mode using 160 segments with a refresh rate set to ACLK/64, which is 512 Hz. • Foreground Process: • Formulae: • Block Diagram: