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United States Patent [191 [11] Patent Number: Mattera et al. [45] [54] PROGRAMMABLE - VOLTAGE - 4,634,892 l/1987 Isbell et a1. ................... .. 307/355 X GENERATOR INTERFACE FOR 4,644,138 2/1987 DECREASING THE MINIMUM VOLTAGE 4,692,598 9/ 1987 Yoshida et a1. ................... .. 219/497 STEP [75] 5,023,801 Jun. 11, 1991 Date of Patent: Walsh . . . . . . . . .. . . . . . . .. 219/ 497 X FOREIGN PATENT DOCUMENTS Inventors= Adriano Matte", Novara; Roberto 0783749 11/1980 U.S.S.R. ............................ .. 364/480 Fornari, Parma; Renato Magnanini, Reggio Emilia; Carolo Paorici, OTHER PUBLICATIONS Pam“; Puck’ zmfot?ivia 5- Peuico; Cichocki, C., O. Osowski, “Realization of Resistive Gm'mm Zuccalh! Parma' an of Italy [73] Assignees: Montedison S.p.A., Milan; Consiglo N-Port Networks Using Operational Ampli?ers”, Elec "(mics Lem-"'5' V01- 14, Noe 13, Jlm- 22, 1973, PP Nazionale Delle Ricerche, Rome, both of Italy 412-414 Primary Examiner—-Joseph L. Dixon [21] App], No; 323,172 [22] Filed: Mar. 15, 1989 _ Attorney, Agent, or Firm-Morgan & Finnegan [57] ABSTRACT _ An interface circuit to the output of a programmable ‘ Related ‘15' Apphcatwn Data [63] . [30] voltage ramp generator for decreasing the minimum Continuation of Ser. No. 867,024, May 27, 1986, abandoned. . . P . . D millivolt. The 1nterface circuit receives an input from Forelgn Apphcatlon nonty ata May 28, 1985 [IT] voltage step of such a generator having two voltage channels and a minimum voltage step greater than 1 each of the two voltage channels (V2, V3), along with Italy ............................. .. 20915 A/85 an inserted voltage (V1)_ The circuit includes a Sum_ [51] Int. 01.5 ............................................ .. G06F 15/20 mine ampli?er for (i) compressing me minimum voltage [52] us. (:1. .................................... .. 364/480; 328/11; step from one voltage channel (V2) by a factor equal to 219/497 or greater than such minimum voltage step, (ii) adding [58] Field of Search ..................... .. 364/480, 481, 557; [56] 324/ 128; 328/146, 147, 11; 307/354, 355, 364, 529, 549, 551; 330/69; 219/494, 497, 499 References Cited pressed voltage, and (iii) subtracting the inserted volt age (V1) (or adding ‘an inserted voltage which is nega tive). The inserted voltage (V1) is equal in magnitude to the maximum output value from the voltage channel that has the voltage compressed (V 2). The output of the U-S' PATENT DOCUMENTS 3,493,782 2/1970 Georgi .............................. .. 328/146 3,922,535 ll/l975 Randolph .... .. 4,008,387 4,079,331 2/1977 3/1978 Green et a1. .............. ,. 364/477 Pinckaers et al. ....... .. . 219/499 X 4,167,663 9/1979 summing ampli?er (V011!) may be represented by: . 364/557X Vu = VV VV V/ a! ( 3 X)+( 2 Y>+< 1 Z) Granzow, Jr. et a1. .......... .. 219/479 Talambiras ................... .. 4’554’439 4:591:994 4,599,572 4,612,463, the voltage from the other channel (V 3) to the com X where X’ Y’ Z=attenuation or amplication factors_ The interface circuit decreases the minimum voltage step at channel V; by a factor Y down to a minimum voltage step Of 1 millivolt 01‘ less. 11 A985 5/1986 7/1986 9/ 1986 6 Claims, 2 Drawing Sheets //V7f/?F»4Ci C/RCU/f : // I mama/mat: “3 ‘'3 I Gi/Vi/e’AfOR VOZMG! --'—-'—' CH2 v2 1-. VI Z I i 3) i {04/7X01 4 f4’ US. Patent June 11, 1991 Sheet 2 of 2 5,023,801 Nb; 1 5,023,801 , 2 . taminating impurities which in turn generally contrib PROGRAMMABLE - VOLTAGE - GENERATOR ute to the formation of lattice defects during the growth INTERFACE FOR DECREASING THE MINIMUM VOLTAGE STEP and cooling of the monocrystal. To achieve a high perfection (instead of a high dislo cation density) and a high purity (instead of impurity) in 5 This is a continuation of co-pending application Ser. No. 06/867,024, ?led on May 27, 1986 now abandoned. a monocrystal, it is necessary to have temperature varia tions down to 01° C. or less in certain stages of the growth cycle. FIELD OF INVENTION This invention relates to electronic devices for use 10 Therefore, there is a need for special programmable with conventional programmable voltage generators generators capable of programming voltage variations and more particularly to such devices which reduce the minimum voltage step to l millivolt or less. of about 1 mV or less to enable the growth of mono BACKGROUND OF INVENTION crystals with a high perfection and purity. By using the interface circuit of this invention with a 15 The conventional programmable voltage generator possible to achieve such minimum voltage steps of l has a minimum voltage step of approximately 10-20 millivolts. Such a minimum voltage step is too large for voltage inputs to a temperature controller used with ovens for growing monocrystals. Temperature controllers for ovens used in growing crystals may require temperature control of some tenths of a degree centigrade. A minimum voltage step of l conventional programmable voltage generator, it is millivolt or less. SUMMARY OF THE INVENTION 20 millivolt or less typically would be needed to achieve a temperature variation of 01° C. or less. Thus, the mini 25 mum voltage step of approximately lO-20 millivolts is a An object of this invention is to provide an interface circuit between a programmable voltage ramp genera tor and a temperature controller for decreasing the minimum voltage step. The programmable voltage ramp generator has two output voltage channels CH2 and CH3 for voltage sig drawback against using a conventional programmable nals V2 and V3, respectively, which are variable be voltage-generator to provide a voltage input to a tem perature controller for ovens used in growing crystals. tween a minimum and a maximum and increasable by One conventional programmable voltage generator is The interface circuit has three input voltages V1, V2, and V3. V2 and V3 are the voltage signals output from the programmable voltage ramp generator. V1 is an inserted voltage. The output voltage, V0,”, of the inter face circuit has minimum voltage stepsél millivolt. the Honeywell DCP 7700. Analagous generators are available from Leeds, Northrup, Eurothon and other companies. The oven generally used in the growth of monocrystals is the CZ type (Czochralski) oven. Hori zontal Bridgman type ovens also are used. The growth 35 minimum values greater than 1 millivolt. technique generally used is the LEC technique. The Honeywell programmable voltage ramp genera Vam= V3+(V2/Y)+V1 tor has the following characteristics: voltage outputs on where Y=attenuation factor 3 independent channels, capability of programming 99 (1) V0“, is obtained by compressing the minimum output temperature segments or settings, and storing of 9 pro 40 voltage variation from the generator channel CH2 by grams. The nine programs de?ne the voltage variation an attenuation factor Y, adding the output voltage of from an initial predetermined voltage value to a ?nal generator channel CH3, and adding an inserted voltage value, while passing through intermediate values in V1 (which is a negative voltage). established periods of time that are more or less pro The attenuation factor Y is equal to or greater than 45 the minimum voltage step of channel CH2. The inserted A problem with the conventional generators is the voltage, V1, equals the maximum output value of chan characteristic of a minimum voltage step of approxi nel CH2 (but of the opposite polarity). mately 10-20 millivolts. Such voltages correspond to minimum programmable temperature variations of apIn particular, the interface circuit includes a summing proximately 1° to 2° C. In particular, such a minimum 50 ampli?er having an output voltage, Vow, de?ned by the temperature variation results in a high number of lattice equation: defects in the growth of a semiconductor type insulat ing or metallic crystal. These defects make the mono V0m=(V3/X)+(Vz/Y)+(V1/Z) (z) crystals obtained rather unsuitable for various applica tions, in particular for those in the electronics ?eld (i.e. 55 where longed. . emitter diodes, microwave devices, lasers, integrated circuits). The Group III-V monocrystals (i.e. GaP and X: an attenuation or ampli?cation factor Y; minimum voltage step of CH2 In?) result in a high dislocation density and often a high 2: an attenuation or ampli?cation factor concentration of impurities. Such monocrystals are not To achieve equation (1) for V0,” of the interface cir stoichiometric and have a low structural homogeneity. 60 cuit, X=Z= l. Inclusions, microprecipitates, etc., may be present. This represents a signi?cant drawback when the monocrys BRIEF DESCRIPTION OF THE DRAWINGS tals are prepared by using a polycrystal as a precursor FIG. 1 is a block diagram of the interface circuit of because the monocrystal will have a high number of 65 this invention between a programmable voltage genera dislocation and impurity defects. Another drawback with a 1° C. to 2° C. (i.e. l0 my to 20 mv) minimum step is that the high concentration of defects is also associated with a concentration of con tor and a temperature controller. FIG. 2 is an electrical schematic of the preferred embodiment of the interface circuit of this invention. 3 5,023,801 4 millivolts (5 volts/Y) with a minimum voltage step of l DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT FIG. 1 illustrates the block diagram of the interface (3) V3 also is variable between 1 volt and 5 volts with minimum voltage increases of 10 millivolts for the circuit 2 between the programmable voltage generator Honeywell DCP7700 programmable voltage generator. millivolt (l0 millivolts/Y). 1 and the temperature controller 3. As illustrated, the Resistor R3 is selected to equal RFsuch that the attenua voltage signal at channel CH3 is input to a summing tion factor X equals 1. circuit without being altered. The voltage signal at For the growth phase of monocrystals, controlled channel CH2, however, is shown to pass through a temperature drops between 01° C. and 40° C. in 0.1“ C. steps may be achieved with V1, V2, and V3 de?ned as above with the respective attenuation factors (X=l, Y: 10, Z: 1). By ?xing V; at 5 volts, the contribution of V1 and V2 to the output voltage is zero (i.e. (5000/l0)——500=0). division circuit prior to being input to the summing circuit. In addition, a voltage V1 is inserted as an input to the summing circuit. The voltage, V1, is designated to be a negative voltage in millivolt units. The output of the interface circuit 2 enters the temperature controller 15 Then by varying V2 at the programmable voltage gen 3. erator from 5 volts down to 1 volt in 10 millivolt steps, Referring to FIG. 2, the summing circuit includes a summing ampli?er. The voltage signals V1, V2, and V3 are de?ned as follows: (1) V1 is a negative voltage necessary for maintaining an output signal which fully compensates the output signal from channel CH2 of the programmable voltage generator 1 and the intrinsic output signal of the sum ming ampli?er. V1 may be attenuated or ampli?ed by a factor Z as a function of the reciprocal of the resistors R1 and R}: as con?gured in FIG. 2. As also shown in FIG. 2, V1 is stabilized by a Zener diode. ' (2) V2 is the output voltage at channel CH2 of the programmable voltage generator. V2 varies between a minimum and a maximum value and has a minimum voltage step greater than 1 millivolt, all as de?ned by the programmable voltage generator 1. V2 is attenuated by a factor Y as a function of the reciprocal of the resis tors R2 and Rpand may be increased in steps of less than or equal to l millivolt over the range of V; as attenu ated. the output voltage from the interface circuit varies‘from 0 volts to —400 millivolts in l millivolt steps (before adding V3). By adding V3, the minimum output voltage may be offset as needed (i.e. during the synthesis phases of the polycrystal starting from the elements for semi conductors obtained with the LEC technique). In such an example, the interface circuit performs the following functions: compress (divide) by a factor of 10 the minimum volt age step of channel 2 bringing the minimum voltage step to a value of l millivolt; add the output voltage of channel 3, unchanged, to the compressed voltage of channel 2; add the negative 500 millivolts, V1, to the total output at channel 2 to bring the operating range of channel 2 between 0 and —0.4 volts. The output voltage of the interface circuit is de?ned in such case by the equation: your: V3+(V2/10)—500 (3) (3) V3 is the output voltage at channel CH3 of the programmable voltage generator. V3 varies between a minimum and a maximum with minimum voltage steps As illustrated in FIG. 2, a preferred embodiment of the interface circuit is shown. greater than 1 millivolt, all as de?ned by the program mable voltage generator 1. V3 is attenuated or ampli?ed ventional programmable voltage generator. R1, R1, R3, by a factor X as a function of the reciprocal of the resistors R3 and RF. CH2 and CH3 are the output channels from a con R4, R5, R15, and R; are resistors. C1 and C2 are capaci tors. P1, P2, and P3 are variable resistors (potentiome ters), the maximum values for which are labelled in The ampli?cation or attenuation factors X, Y, Z are selected such that V; is attenuated, such that V1 and V3 FIG. 2. are ampli?ed, attenuated or left unchanged, and such that V0“, has a minimum voltage step of less than or equal to l millivolt. IC; is an integrated circuit including a zener diode and resistor. The values for the example above are de ?ned below: R1=R3=RF= lO kilo-ohms An example is provided below of a particular applica tion of the interface circuit 2 for the growth and synthe sis of monocrystals with a CZ ADL oven model HPCZ, a Honeywell DCP77OO programmable voltage genera 1C] is a summing ampli?er (i.e. National A725). R2: 100 kilo-ohms RE: 3.9 kilo-ohms R4: 10 ohms tor, and a CAT series 80 temperature controller. In such cases the values of V}, V2, and V3 for achieving mini mum voltage steps of l millivolt are: (1) V1 is approximately —- 500 millivolts and stabilized by a Zener diode to maintain an output signal which R6: 12 kilo-ohms C1=0.O5 micro-farads C2=O.02 micro-farads fully compensates (i) a 500 millivolt maximum signal provided by channel CH2 and (ii) the intrinsic output 60 It is understood that based on the teachings above signal of the ampli?er. Resistor R1 is set equal to R}: one skilled in the art may rede?ne the values assigned such that attenuation factor Z: l. (2) V2 is variable between 1 volt and 5 volts with minimum increases of 10 millivolts for the Honeywell DCP770O programmable voltage generator. Resistor R2 is selected to be equal to R1: times 10 to achieve an attenuation factor of 10 (Y=l0). V2 provides output variations between 100 millivolts (l volt/Y) and, 500 above to attenuate or amplify the voltages V1 and V3 and to alter the attenuation of voltage V; to obtain an output voltage, V0,”, still having a minimum voltage 65 step of less than or equal to l millivolt. In one example of the interface with the component values de?ned as above, a 500 gram monocrystal of InP is melted in a CZ ADL type oven, mod. HPCZ at 1 100° 5 5,023,801 6 C. Voltage variations then are applied to a Honeywell tion factor, V1 is the inserted voltage, and X and Z are DCP77OO programmable voltage generator. It is ob attenuation or ampli?cation factors, and wherein X, Y, served that for output voltage variations of l millivolt there is a corresponding melt temperature variation of approximately 0.1” C. The temperature is measured and Z are de?ned to achieve a minimum voltage step for V0,‘, of less than or equal to l millivolt. 4. An interface circuit between a programmable volt age generator providing two channels variable between a minimum voltage and a maximum voltage by incre ments of greater than one millivolt and a voltage using precision thermocouples for high temperatures of the Platinum/Platinum-Rhodium type (13%). In comparison, under the same conditions absent the interface circuit, the minimum voltage variation is l0 millivolts and the minimum temperature variation ob responsive temperature-controlled oven for growing monocrystals, comprising: served is 1° C. What is claimed is: 1. An interface circuit between a programmable volt means for obtaining a compressed voltage by divid ing a ?rst voltage from the programmable voltage generator by an attenuation factor equal to or age generator providing two channels variable between a minimum voltage and a maximum voltage by incre greater than the minimum voltage increment for said ?rst voltage; ments of greater than one millivolt and a temperature means for obtaining a summed voltage by adding a controller, comprising: means for obtaining a compressed voltage by divid ing a ?rst voltage from the programmable voltage generator by an attenuation factor equal to or greater than the minimum voltage increment for said ?rst voltage; means for obtaining a summed voltage by adding a second voltage from the programmable voltage 25 generator to said compressed voltage; and means for adding an inserted voltage equal in magni tude and opposite in polarity to the maximum volt age for said ?rst voltage to said summed voltage; wherein the interface circuit provides incremental voltage changes for temperature control to the second voltage from the programmable voltage generator to said compressed voltage; and means for adding an inserted voltage equal in magni tude and opposite in polarity to the maximum volt age for said ?rst voltage to said summed voltage to obtain a temperature-control voltage; wherein the interface circuit provides incremental voltage changes in the temperature-control voltage to the voltage-responsive temperature-controlled oven of less than one millivolt responsive to more mental voltage changes from the programmable voltage generator of greater than one millivolt. 5. An interface circuit according to claim 4, further temperature controller of less than one millivolt including a summing ampli?er having three input volt responsive to incremental voltage changes from the programmable voltage generator of greater by the equation: ages, V1, V2 and V3, and an output voltage Vmnde?ned than one millivolt. 2. An interface circuit according to claim 1, further 35 including a summing ampli?er having three input volt where V; and V3 are the ?rst and second voltages from the programmable voltage generator, Y is the attenua tion factor, and V1 is the inserted voltage. ages, V1, V2 and V3, and an output voltage Vomde?ned by the equation: 6. An interface circuit according to claim 4, further including a summing ampli?er having three input volt ages, V1, V2, and V3, and an output voltage Vmde?ned where V; and V3 are the ?rst and second voltages from the programmable voltage generator, Y is the attenua tion factor, and V1 is the inserted voltage. by the equation: 3. An interface circuit according to claim 1, further 45 including a summing ampli?er having three input volt where V; and V3 are the ?rst and second voltages from ages, V1, V2, and V3, and an output voltage VMde?ned the programmable voltage generator, Y is the attenua tion factor, V1 is the inserted voltage, and X and Z are by the equation: 50 where V2 and V3 are the ?rst and second voltages from attenuation or ampli?cation factors, and wherein X, Y, and Z are de?ned to achieve a minimum voltage step for V0,“ of less than or equal to 1 millivolt. 1'! the programmable voltage generator, Y is the attenua 55 60 65 * Ill Ill *