Download (standby) power. - TI Training

Low Standby ACDC Power
Converter Design
Tony Liu
Analog FAE
[email protected]
USB Chargers, Small Adapters and Aux
power
• Different application requirements
– Cell phone & tablet battery chargers, 5~20 W
– Low power adapters, 10~30 W
– Medium-power adapters, 30~65 W
– AUX (standby) power.
• Must meet different standard requirements
– Energy Star efficiency requirement
– 5-Star rating for standby power
– Regulation and transient response
– EN55022 EMI standard
• Often conflicting design targets
– High efficiency vs. low standby
– High output power vs. small size
– High performance vs. low cost
Efficiency and Standby Power Requirement
• Recent directives from
EC Code of Conduct
and US Dept. of Energy,
for example, are driving
minimum efficiency
requirements higher.
• EC CoC drives standby
power requirements to
new lows, such as Tier 2
in January 2016.
• 5-Star rating system
allows 5 stars placed on
chargers with no-load
power less than 30 mW.
Progression of Standby Power
• Mobile phone consortium established the 5-Star rating system to
encourage development of chargers with lower standby power.
• Recent marketing efforts are driving the target to 10 mW and below.
• This target is being applied not only to cell phone chargers, but video
displays and other appliances, too.
Origin of “Zero-Power” Designation
• National environmental agencies around the world refer to standards
developed by international commissions when setting local policy.
• IEC 62301 “Household Electrical Appliances – Measurement of Standby
Power” standardizes measurement methods of standby power in various
appliances and electronic equipment.
– Performance parameters of measurement equipment are specified
– Test conditions and procedures are specified
– Clause 4.5 regards measurements of less than 5 mW as zero power
• Clause 4.5 of IEC 62301 has become the basis for a “Zero-Power” marketing
campaign as the ultimate target for no-load standby dissipation in electronic
devices and appliances.
Progression Towards Zero-Power ~ 2006
PRIMARY
+
RSU
CBULK
RSNUB
CSNUB
N1
VBULK
SECONDARY
+
N2
COUT
VOUT
ROUT
-
RDD
CDD
VAC
“Green-Mode” Quasi-Resonant
Flyback Controller
Standby less than 200 mW
NB
ROVP1
Standby Power vs. Input Voltage
Input Power vs Input Voltage at No Load
UCC28600
1
SS
STATUS
8
220 mW
230
CSS
210
191 mW
FEEDBACK
FB
OVP
7
3
CS
VDD
6
190
ROVP2
M1
4
GND
OUT
5
TL431
Input Power (mW)
2
170
140 mW
150
130
110
90
CBP
100nF
RPL
RCS
70
50
50
Major standby loss paths
142 mW
85 100 115
150
200
230 250 265
Input Voltage (Vac)
Input Power vs Input Voltage at no Load
6
Simplify the Flyback: Opto FB Vs PSR
• SSR
• PSR
+
VOUT
COUT
CB2
CB1
+
CB2
CB1
Secondary
Primary
–
VAC
Secondary
NP
NS COUT
–
Primary
VAC
RF1
CONTROLLER
CONTROLLER
Auxiliary
Auxiliary
VDD
RF2
HV
VDD
RF3
CDD
RS1
VS
DRV
RS1
CC1
VS
TL431
RS2
HV
CDD
NA
DRV
RS2
CS
CS
RF4
RF6
RCS
RCS
FB
GND
GND
VOUT
PSR Benefits and Limitations
• Benefits
• Opto-coupler and TL431 circuits are eliminated
• Less parts = lower cost, smaller adapter, higher reliability
• Easier to use – internal loop compensation
• Limitations
• Transient Response performance linked to no-load power
performance.
• Lower minimum frequency gives lower no-load power dissipation.
• Lower minimum frequency means a longer response time to load transient from
no-load to full load.
• Transient response can be improved by the addition of a secondary
side wake up circuits (IC).
Progression Towards Zero-Power ~ 2011
Example 1
UCC28700 DCM PSR
Flyback Controller
Example 2
UCC28710 DCM PSR
HV-Input Flyback Controller
Standby less than 30 mW
+
CB1
CB2
Standby less than 10 mW
VREG
Ns
Np
RPL
COUT
VBLK
RCB
VOUT
VREG
CB2
CB1
+
VBLK
Ns
Np
RPL
COUT
RSTR
–
UCC28710
SOIC-7
UCC28700
SOT23-6
VAUX
Na
VAUX
D2
D2
VDD
VDD
RS1
–
VAC
VAC
Na
CDD
RS1
DRV
VS
RS2
CDD
HV
DRV
VS
CS
CS
TBD
RLC
RS2
RCS
GND
Test Data from 5-W charger:
24.3 mW @ 230 Vac
Major standby loss paths
TBD
RLC
RCS
GND
Test Data from 5-W charger:
7.8 mW @ 230 Vac
RCB
VOUT
Features Enabling Zero Standby Power
 Bias Supply
 Integrated high-voltage switch eliminates constant start-up current
 High operating bias voltage, up to 35 V  high NAUX/NSEC ratio
 Wide UVLO hysteresis allows VDD to drop as low as ~8 V during standby
without triggering UVLO
 Dynamic IC Power Management
 Very low bias current during standby (~50 uA)
 IC has low power wait-state between pulses at fSW < 28 kHz to reduce IC
consumption to < 1 mW in standby
 Wake-up capability ensures rapid response to sudden load steps while in
standby condition
 Wide Power-Control Dynamic Range
 Switching frequency extends from 83 kHz down to 30 Hz
 3 : 1 variation in primary peak current
Example: Zero-Power 2014
Simplified schematic diagram of 10-W, 5-V charger example.
VBULK
CB1
VOUT
NP
CB2
UCC24650
SOT-23-5
NS
VSEC
VAC
VAUX
NA
VDD
RS1
VDD
ENSR
GND
COUT
RPL
DS
UCC28730
SOIC-7
DA
WAKE
IOUT
HV
CVDD
M1
DRV
RLC
VS
CS
CBC
RS2
RCBC
GND
RCS
Test Data from 10-W charger:
2.9 mW @ 230 Vac
Ground-referenced output diode is required for simple implementation.
Wake signal is impressed across secondary winding and sensed at VS input.
Control Law
Control-Law Profile in Constant-Voltage (CV) Mode
IPP
(peak primary current)
IPP(max)
83.3 kHz
fSW
IPP
fSW
FM
AM
FM
IPP(max) / 3
28.34 kHz
27.33 kHz
fSW(min) =
30 Hz
1.92 kHz
0 V 0.75 V
0.8 V
1.3 V
2.2 V 2.65 V 3.1 V 3.55 V
4.85 V
5V
Control-Law Voltage, Internal - VCL
Control Law for IC limits maximum frequency to ~83 kHz, and uses 4 levels of lowfrequency modulation to handle light-load regulation. (Frequencies shown are ideal.)
The peak primary current varies over a 3-to-1 ratio for power levels between 4% ~ 100% of
rated power, depending on the maximum frequency chosen for design.
Power Control Dynamic Range for DCM
Flyback
1
P  I L f
in
Pin_min 
1
Ipk_min 2L p fS_min
2
Pin _
max
Pin _
min
2
pk
2
 Ipk _ max

I
 pk _ min
p S
2
 fS _ max

 f
 S _ min
24990
83.3 kHz
30 Hz
3
10-W design example at 230 VAC
fsw_min
IC loss
Coss (50p F) loss
Other losses
Total
~100 Hz
~1 mW
~0.5 mW
~1.4 mW
~2.9 mW
Wide dynamic range of control achieves low standby power
because extra-low frequency minimizes switching loss.
Low Standby and Transient Response
 Low switching frequency allows zero-power in no-load condition, but
transient response can be severely limited
 Using primary side control (PSR), the output voltage is only sensed
during the switching cycle
 Worst transient response happens at the minimum switching
frequency
5000
0.5A, 0.2V
0.5A, 0.4V
0.5A, 0.6V
0.5A, 0.9V
Required Ouptut Capacitor (uF)
4500
4000
3500
3000
2500
2000
1500
1000
500
COUT
I o

Vo  f s _ min
0
500
1000
1500
2000
2500
Switching frquency (Hz)
Without “Wake-Up” capability, the minimum switching frequency
must be >1 kHz to keep a reasonable output capacitor value.
3000
Wake-Up is Necessary for Zero-Power
Example : UCC28730 + UCC24650
• UCC28730 can function to zero-power without UCC24650
– But, will have extremely bad transient response due to long intervals
between sampling of the output voltage
– Or, output capacitor must be unrealistically HUGE to limit Vout droop
until controller responds to the higher load
• UCC24650 detects the rapid voltage change due to load-step and wakes
up the UCC28730
– Output voltage is stored each switching cycle
– If voltage falls -3% below the stored reference, a wake-up signal is sent
to the primary controller
– UCC28730 immediately cancels sleep mode and supports the higher
load
– Wake-up IC allows much smaller output capacitance, even when
frequency is very low
Wake-Up Response
IOUT
Heavy Load Step
VNOM
VOUT
Wake Threshold
IWAKE
Wake-up pulse generated by
sinking current out of VSEC
VSEC
Wide spacing between power
cycles during no-load condition
makes PSR “blind” to load
changes between pulses.
Heavy load-step causes output
voltage droop, but Wake-Up
circuits can detect this and
wake-up the PSR to keep Vout
within regulation limits.
PSR IC responds with
3 pulses in Transition Mode,
followed by normal voltage-loop
response. Usually, this is at the
CC limit until regulation is reestablished.
VAUX
VS
Wake-up signal detected by primary
controller; switching initiated
Compare No-Wake to Wake-Up
Response to 2-A load step with Wake
function disabled. Vout drops below
1 V before control-loop can respond
to restore regulation.
Response to 2-A load step with Wake-Up
function. Vout droops only -0.20 V from
5.2 V before control-loop responds to
restore regulation within 2 ms.
Cout = 540 uF. (Blue = VS input)
Cout = 540 uF.
Wake-Up Response Waveform Details
WAKE-UP
-3%
droop
threshold
Here, wake-up response limits output
droop to ~200 mV below the no-load
regulation level.
Vout = 100 mV/div, 5.1-V DC-offset.
Expanded view shows initial multi-TMpulse response to a wake-up event.
Blue trace is the VS waveform (using
low-capacitance probe).
Small disturbance is the wake-up signal!
Vout = 100 mV/div, 5.1-V DC-offset.
No-Load Loss Accounting:
“Static” Component Losses
Static leakage currents
VBULK
CB1
VOUT
NP
CB2
UCC24650
SOT-23-5
NS
VSEC
VAC
VAUX
NA
VDD
RS1
CVDD
M1
GND
RPL =
open
Secondary-side “static” losses =
schottky + COUT leakages at 5.05V.
Measurement = 155µA => 0.783mW
DRV
RLC
CS
CBC
RCBC
ENSR
COUT
HV
VS
RS2
VDD
DS
UCC28730
SOIC-7
DA
WAKE
IOUT
GND
RCS
Primary-side “static” losses =
bridge + CBULK + start-up JFET +
MOSFET at 325V, +13µWBRDG
Measurement = 1.52µA => 0.510mW
No-Load Loss Accounting:
“Active” IC Bias Losses
IC bias currents
IDD
VBULK
CB1
NP
CB2
UCC24650
SOT-23-5
NS
VSEC
VAC
VAUX
NA
DA
IDD
RS1
VDD
ENSR
GND
IOUT
COUT
RPL =
open
DS
UCC28730
SOIC-7
VDD
WAKE
VOUT
HV
CVDD
M1
Secondary-side UCC24650 at 5.05V:
DRV
RLC
VS
Target = ~55µA => 0.278mW
CS
CBC
RS2
RCBC
GND
(55 max, 41 typ)
RCS
Primary-side UCC28730 at ~12V:
Wait-State
Target = ~60µA => 0.720mW
(60 max, 50 typ)
No-Load Loss Accounting:
Frequency-Dependent Losses
Switching and conduction losses
VBULK
CB1
VOUT
NP
CB2
UCC24650
SOT-23-5
NS
VSEC
VAC
VAUX
NA
VDD
RS1
VDD
ENSR
GND
COUT
RPL =
open
DS
UCC28730
SOIC-7
DA
WAKE
IOUT
HV
CVDD
M1
Diode Voltage Drops
DRV
RLC
VS
CS
Transformer Wire & Core Losses
CBC
RS2
RCBC
GND
RCS
Leakage Inductance
Switched-node Capacitance
Resistive Losses
Issues Complicating Z-P Achievement
Obvious issues
and non-obvious issues
VBULK
CB1
VOUT
NP
CB2
UCC24650
SOT-23-5
NS
VSEC
VAC
VAUX
NA
VDD
RS1
CVDD
GND
RPL =
open
Leakage currents too high
M1
DRV
RLC
RCD snubber instead
of TVS clamp
CS
CBC
RCBC
ENSR
COUT
HV
VS
RS2
VDD
DS
UCC28730
SOIC-7
DA
WAKE
IOUT
GND
EMI-filter X-cap dissipation!
X-cap discharge resistors
RCS
Switched-node
capacitance too high
External Standby Loads
High power designs with bigger
parasitic components
Conclusions
• “Zero-Power” began as, and still is, a marketing program and not a regulatory
requirement. Claims of zero power consumption while in standby mode can be a
marketing advantage for consumer products.
• By default, qualification for “Zero-Power” designation requires an average standby
dissipation of <5 mW when measured at 230 Vac.
• Achievement of Z-P status requires a controller set that minimizes its own contribution to
standby power, yet operates in a way to minimize system-level losses without turning off
completely.
• UCC28730 and UCC24650 together require only ~1 mW to remain “active” during
standby, ready to respond to sudden heavy load steps.
• System-level design involves strict attention to every possible loss contributor to ensure
that the collective standby losses (including any standby loads) fall below 5 mW.
Evaluation of Modified 12-V 3.3-A Module
(40 W rating)
 UCC28730 PSR Controller
 replaces UCC28710
 same output regulation, wake-up capable
 UCC24650 Wake-Up Output Monitor
 designed to work with negative-leg diode
 adapter circuit added to work with positive-side diode
 Major Goals Achieved for Low-cost PSR System
 Fast Response to Heavy Load Step with Wake-Up Signaling
 Very Low Dissipation (< 10 mW) in Stand-by Mode
Evaluation Board Photo
0.97VNOM
VBULK
CB1
VOUT
NP
CB2
UCC24650
SOT-23-5
NS
VSEC
VAC
VAUX
NA
VDD
RS1
VDD
ENSR
GND
RPL
DS
UCC28730
SOIC-7
DA
WAKE
IOUT
COUT
HV
CVDD
UCC28730:
30Hz to 83kHz
M1
DRV
RLC
VS
CS
CBC
RS2
RCBC
GND
RCS
When Wake-Up signal is detected,
switching resumes at fMAX, IPK,MIN
Less Than 10 mW Stand-by Loss Across
Different Line Conditions
< 10-mW stand-by power can be achieved over full line
range!
 Measured PIN @ 325 Vdc = 6.97 mW,
Estimated PIN @ 230 Vac = 7.65 mW
 Measured PIN @ 163 Vdc = 6.26 mW,
Estimated PIN @ 115 Vac = 6.89 mW
Note: AC loss is typically ~10% higher than DC loss in stand-by conditions.
Transient Response Without Wake-Up
12.24 V
Infinite
Persistence:
ΔVOUT = -5.84 V
for 0 A - 3.5 A
load-steps, with
COUT = 3044 µF
V, I Zero Ref
VINPUT = 325 Vdc
Output Voltage
2 V/div
6.4 V
Output Current
1 A/div
3.5 A Load-Step
4 ms/div time sweep
Here is a composite screen-capture of repetitive load steps, showing the wide
range and random amplitudes of voltage droops.
Fast Transient Response With Wake-Up
VINPUT = 230V AC
Infinite
Persistence:
ΔVOUT = -1V
for 0 A – 3.5 A
load-steps, with
COUT = 3044 µF
V, I Zero Ref
11.7 V minimum peak
Output Voltage
0.2 V/div
Output Current
1 A/div
3.5 A Load-Step
4 ms/div time sweep
Here is a composite screen-capture of same repetitive load steps, showing
consistently fast response due to UCC24650 wake-up signaling.
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