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Transcript
LV8907UW Sensor-less Three-phase Brushless DC Motor Controller, with Gate Drivers, for Automotive Overview The LV8907 is a high performance, AEC-Q100 qualified, sensor-less three-phase BLDC motor controller with integrated gate drivers for driving external N-MOSFETs. An on-chip two-stage charge pump provides required gate voltage for a wide range of low RDS(ON) type external N-MOSFETs. The device offers a rich set of system protection and diagnostic functions such as over-current, over-voltage, short-circuit, under-voltage, over-temperature and many more. It supports open-loop as well as closed-loop speed control with user configurable startup, speed setting and proportional/integral (PI) control coefficients, making it suitable for a wide range of motor and load combinations. With a built-in linear regulator for powering external circuits, a watchdog timer, and a LIN (Local Interconnect Network) transceiver, the LV8907 offers a very small system solution. The LV8907 stores system parameters in embedded one-time programmable (OTP) non-volatile memory in addition to RAM system memory. An SPI interface is provided for parameter setting and monitoring the system status. With the operating junction temperature tolerance up to 175ºC and electrically LIN compatible control signals (PWM and Enable), the LV8907 is an ideal solution for stand-alone BLDC motor control systems. www.onsemi.com PACKAGE PICTURE SQFP48K 7 mm x 7 mm MARKING DIAGRAM Features AEC-Q100 qualified and PPAP capable. Operating junction temperature up to 175ºC Operating voltage range from 5.5V to 20V with tolerance from 4.5V to 40V Embedded proprietary sensor-less trapezoidal and pseudo-sinusoidal commutation Supports open-loop as well as closed-loop speed control Integrated gate drivers for driving six N-MOSFETs Two-stage charge pump for continuous 100% duty cycle operation 5V/3.3V regulator, LIN transceiver and Watchdog timer applications using an external microcontroller. Configurable speed settings and PI control coefficients Various system protection features including: o Shoot through protection using configurable dead-time o Drain-source short detection o Cycle-by-cycle current limit and over-current shutdown o Over-voltage and under-voltage shutdown o Over-temperature warning and shutdown o Input PWM fault detection LV8907 YMALN 48 1 Y: M: A: LN: production year production month assembly location lot number ORDERING INFORMATION Ordering Code: LV8907UWR2G Package SQFP48K Shipping (quantity/packing) 2500 per tape & reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF Typical Applications Automotive pumps (Fuel, Oil, and Hydraulic) Fans (HVAC, Radiator, Battery Cooling, LED Headlight Cooling) White goods and industrial BLDC motor control © Semiconductor Components Industries, LLC, 2016 April 2016- Rev. 0 1 Publication Order Number: LV8907UW/D LV8907UW LV8907 BLOCK DIAGRAM VS VCC V3RI V3RO LIN_PWMIN CHP CP1N CP1P CP2N CP2P VGL LV8907 5V / 3.3V Regulator Internal Regulator LIN Transceiver / PWM Input TXD Charge Pump COM Back EMF Detection Watchdog Timer OTP OSC System Registers RXD UH CSB UOUT SCLK VH SI System MOSFET SO Control Pre-driver EN and VOUT WH Or Sensor-less PWMIN Commutation WOUT Gate Driver UL FG VL WAKE WL SUL DIAG VS CHP VGL Voltage Monitor TEST VS Thermal Shutdown Logic VDS Monitor SVL SWL Protection Logic + + - RF + - 200 mV 100 mV RFSENS TH LGND AGND PGND Figure 1: LV8907 Block Diagram www.onsemi.com 2 LV8907UW APPLICATION BLOCK DIAGRAMS + VBAT CHP CP1N CP1P CP2N CP2P VGL VS VCC V3RI V3RO COM PWMIN LIN_PWMIN TXD UH RXD UOUT CSB VH SCLK VOUT LV8907 SI WH SO WOUT EN UL PWMIN VL FG WL DIAG SUL WAKE SWL SVL Key RF TEST TH LGND AGND RFSENS PGND V3RO Figure 2: Example of Standalone Configuration + VBAT LIN VS LIN_PWMIN CHP CP1N CP1P CP2N CP2P VGL V3RI V3RO COM VCC UH TXD UOUT RXD VH CSB VOUT LV8907 SCLK MCU SI WH WOUT SO UL VL EN PWMIN WL SUL FG SVL DIAG SWL Key WAKE RF TEST TH LGND AGND PGND RFSENS V3RO Figure 3: Example of LIN Based Control Configuration www.onsemi.com 3 LV8907UW SWL WL WOUT WH SVL VL VOUT VH SUL UL UOUT UH PIN ASSIGNMENTS 36 25 37 24 PGND COM VGL NC CHP RF LV8907 SQFP48K(7×7) CP1N CP1P CP2P CP2N VS NC RFSENS TH NC TEST 7mm x 7mm WAKE NC EN LIN_PWMIN V3RO NC V3RI LGND 48 13 1 FG Figure 4: LV8907 Pinout www.onsemi.com 4 DIAG SI SO CSB SCLK NC AGND PWMIN TXD RXD VCC 12 LV8907UW PIN DESCRIPTION Pin Name Pin No VCC 1 RXD 2 TXD 3 PWMIN 4 AGND CSB SCLK SI SO 5 6, 14, 16,18, 21, 23 7 8 9 10 FG 11 DIAG LGND LIN_ PWMIN TEST 12 13 TH 19 RFSENS 20 RF 22 COM 24 SUL SVL SWL UL VL WL UOUT VOUT WOUT UH VH WH PGND 33 29 25 34 30 26 35 31 27 36 32 28 37 VGL 38 CHP 39 CP1N 40 CP1P 41 CP2P 42 CP2N 43 NC 15 17 Description 5V or 3.3V regulator output pin. (Selected by internal register setting) Power supply for microcontroller. Connect capacitor to AGND for stability. Open drain logic level output of LIN_PWMIN received data. Use pull-up to a voltage less than or equal to VS. Logic level input of transmit data for LIN_PWMIN. Digital level PWM input pin for direct drive or speed register selection details. Input polarity can be programmed for either active high or active low. Analog GND pin. Page 16 18 18 16 No Connections Active low SPI interface chip selection pin. SPI interface clock input pin. Active high SPI interface serial data input pin. Open drain SPI interface serial data output pin. Open drain back-EMF transition output pin. The frequency division ratio is selectable via register settings. Programmable open drain diagnostic output. LIN Block GND pin. Must be connected to AGND on the PCB. LIN transceiver input/output. Register selectable as high voltage PWM input with a VVS/2 threshold. Factory test pin. Connect to GND. Thermistor input pin for power stage temperature detection. If the input voltage is below the threshold voltage, an error is triggered. The error threshold is programmable. To disable tie to V3RO. Shunt resistance reference pin. Connect this pin to the GND side of the Shunt resistor with Kelvin leads. Output current detect pin. Connect this pin to higher terminal of the shunt resistor with Kelvin leads. COM input pin. Connect this pin to the motor neutral point if available. This point may be derived from a resistive network with 1k resistors to the phases. Current return path for low-side gate drive. Short circuit shutoff level is measured between this pin and its corresponding phase pin. Gate driver output pin for the low-side Nch Power FET. Use gate resistors for wave-shaping. Current return path for high-side gate drive and reference for high-side short circuit shut-off. Gate driver output pin for the high-side Nch Power FET. Use gate resistors for wave-shaping. GND pin for the charge pump. Power supply pin for low-side gate drive. Connect decoupling capacitor between this pin and GND. Power supply pin for high-side gate drive. Connect decoupling capacitor between this pin and VS. Charge transfer pin of the Charge pump (1N). Connect capacitor between CP1P and CP1N. Charge transfer pin of the Charge pump (1P). Connect capacitor between CP1P and CP1N. Charge transfer pin of the Charge pump (2P). Connect capacitor between CP2P and CP2N. Charge transfer pin of the Charge pump (2N). Connect capacitor between CP2P and CP2N. www.onsemi.com 5 20 20 20 20 18 18 18 19 19 19 14 18 18 18 18 16 16 16 16 16 16 LV8907UW Pin Name VS Pin No 44 WAKE 45 EN 46 V3RO 47 V3RI 48 Description Power supply pin. WAKE pin. “H” = Operating mode, “L” or “Open” = Sleep mode. In Sleep mode all gate drivers are high-impedance. To protect the power stage, pull-down resistors on the gate lines may be required. Motor stage Enable pin. “H” = Normal enabled mode; “L” or “Open” = Standby mode. In Standby mode all gate drivers driven low. Motor freewheeling. 3V regulator output pin. Connect capacitor between this pin and AGND. 3V regulator input pin (internally connected to ccontrol, and logic circuits). Connect to V3RO pin. www.onsemi.com 6 Page 15 15 15 16 16 LV8907UW PIN CIRCUIT VS VS VS V3RO VCC V3RI TH RFSENS PWMIN SCLK 100kΩ SI TEST EN TYPE2: V3RO, VCC TYPE1: V3RI, TH, RFSENS TYPE3: PWMIN, SCLK, SI, TEST, EN VS VS VS RXD SO FG DIAG V3RO WAKE 30kΩ TXD CSB TYPE4: RXD, SO, FG, DIAG 100kΩ TYPE6: WAKE TYPE5: TXD, CSB CHP VGL COM UH VH UL WH VL UOUT WL VOUT 60kΩ 60kΩ SUL WOUT SVL SWL TYPE7: UH, VH, WH, UOUT, VOUT, WOUT TYPE9: COM TYPE8: UL, VL, WL, SUL, SVL, SWL CHP VGL VS CP2P CP1P 30kΩ LIN_PWMIN VGL VS VS CP2N CP1N LGND PGND PGND TYPE10: VGL, CP1P, CP1N, PGND TYPE11: CHP, CP2P, CP2N, PGND www.onsemi.com 7 TYPE12: LIN_PWMIN, LGND LV8907UW 20uA 20uA VS RF VS RFSENS TYPE13: RF, RFSENS www.onsemi.com 8 20uA 20uA LV8907UW ABSOLUTE MAXIMUM RATINGS (Note 1) Parameter Pins VS Ratings −0.3 to 40 Unit V CHP −0.3 to 40 V VGL VR3I, VR3O −0.3 to 16 −0.3 to 3.6 V V VCC −0.3 to 5.5 V Digital I/O voltage1 WAKE,EN −0.3 to 40 V Digital I/O voltage2 CSB, SCLK, SI, PWMIN, TXD, TEST −0.3 to 5.5 V DIAG, FG, SO, RXD −0.3 to 40 V LIN_PWMIN Voltage differential between Pins are 60V or less RF −40 to 40 V −3 to 3.6 V RFSENS −0.3 to 1.0 V TH −0.3 to 3.6 V UOUT, VOUT, WOUT, COM −3 to 40 V High-side output UH, VH, WH −3 to 40 V Low-side output UL, VL, WL −3 to 16 V SUL, SVL, SWL −3 to 3.6 V Voltage between HS gate and phase UH-UOUT,VH-VOUT,WH-WOUT −0.3 to 40 V Voltage between LS gate and source UL-SUL, VL-SVL, WL-SWL −0.3 to 16 V 50 400 10 mA Open drain output current UH,VH,WH,UL,VL,WL pulsed (duty5%) DIAG, FG, SO, RXD Thermal Resistance (RθjA) with Board (Note 2) 47 ESD Human Body Model AEC Q100-002 2 °C/W kV ESD Charged Device Model AEC Q100-011 Supply voltage Charge pump voltage (high side) Charge pump voltage (low side) Logic power supply 5V Regulator voltage Digital output voltage LIN bus voltage RF input voltage RFSENS input voltage TH input voltage Voltage Tolerance Low-side Source output voltage Output current Storage temperature Junction temperature mA 750 V −55 to 150 °C −40 to 150 °C 150 to 175 °C Note 1: Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Note 2: 76.2 × 114.3 × 1.6mm, glass epoxy board Note 3: Operation outside the Operating Junction temperature is not guaranteed. Operation above 150°C should not be considered without a written agreement from ON Semiconductor Engineering staff. (Note 3) www.onsemi.com 9 LV8907UW ELECTRICAL CHARACTERISTICS Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 6.0V≤VS≤20V. Typical values at 25°C and VS=12V unless specified otherwise. (Note 4) Parameter Supply-voltage range Supply current into VS Operational junction Temperature Symbol Condition VS Min Typ Max Unit 6 12 20 V Device fully functional. 5.5 20 V Full logic functionality, driver stage off. 4.5 40 V Is1 V3RO=V3RI 15 25 mA Is2 Sleep Mode 40 80 µA 150 °C −40 Topj OUTPUT BLOCK (UH, VH, WH, UL, VL, WL) Low-side output On-resistance 1 Low-side output On-resistance 2 High-side output On-resistance 1 High-side output On-resistance 2 RON(L1) “L” level Io=10mA 6 15 Ω RON(L2) “H” level Io=-10mA 12 22 Ω RON(H1) “L” level Io=10mA 6 15 Ω RON(H2) “H” level Io=-10mA 12 22 Ω 19.5 20.5 kHz 0.2 % 3.465 V VS=6.0 to 20V 50 mV Io=5mA to 25mA 50 mV DRIVE OUTPUT BLOCK (PWM BLOCK) Drive output PWM frequency fPWMO Output PWM Duty cycle resolution ΔPWMDUTY PWMF=0 Low frequency mode PWMF=0 Low frequency mode 18.5 (Note 5) 3V CONSTANT VOLTAGE OUTPUT Output voltage V3RO Voltage regulation ΔV3R1 Load regulation ΔV3REG2 Current Limit IV3RO 3.135 Not for external loads > 5mA 50 4.75 3.3 mA VCC 5V CONSTANT VOLTAGE OUTPUT Output voltage VC5RO VS=6.0 to 20V Voltage regulation ΔVC5R1 Load regulation ΔVC5R2 Current Limit IVCC5V 5.00 5.25 V VS=6.0 to 20V 50 mV Io=5mA to 25mA 50 mV 50 mA VCC 3V CONSTANT VOLTAGE OUTPUT Output voltage VC3RO Voltage regulation ΔVC3R1 Load regulation ΔVC3R2 Current Limit IVCC3V3 3.135 3.3 3.465 V VS=6.0 to 20V 50 mV Io=5mA to 25mA 50 mV 50 mA LOW-SIDE GATE VOLTAGE OUTPUT (VGL Pin) Low-side output voltage1 VGLH1 6.0 < VS ≤ 8.0V Io=−10mA 8.0 12.0 14.0 V Low-side output voltage2 VGLH2 8.0 < VS ≤ 20V Io=−10mA 10.0 12.0 14.0 V www.onsemi.com 10 LV8907UW Parameter Symbol Condition Min Typ Max Unit SSCG=0 49.6 52.1 54.6 kHz HIGH-SIDE OUTPUT VOLTAGE (CHP Pin) Internal charge pump oscillator frequency FCP Boost voltage1 VGHH1 6.0 < VS ≤ 8.0V Io=−10mA VS +6.0 VS +12.0 VS +14.0 V Boost voltage2 VGHH2 8.0 < VS ≤ 20V Io=−10mA VS +9.0 VS +12.0 VS +14.0 V 1000 Hz 220 ms 18.5 kHz PWMIN INPUT PIN in low frequency mode Input PWM frequency range fLPWM PWM signal timeout TLPWMIN 5.3 210 PWMIN INPUT PIN in High frequency mode Input PWM frequency range fHPWM 0 DIGITAL INPUT PIN (CSB, TXD) High-level input voltage VIH1 Low-level input voltage VIL1 Input hysteresis voltage VIHYS1 0.1 Pull-up resistance. RDVI1 15 V 0.8×V3RO 0.2×V3RO V 0.35 0.6×V3RO V 30 60 KΩ DIGITAL INPUT PIN (SCLK, SI, PWMIN, TEST) High-level input voltage VIH2 Low-level input voltage VIL2 Input hysteresis voltage VIHYS2 0.1 Pull-down resistance RDVI2 50 High-level input voltage VIH3 2.5 Low-level input voltage VIL3 V 0.8×V3RO 0.2×V3RO V 0.35 0.6×V3RO V 100 200 KΩ WAKE INPUT PIN Internal Pull-down resistance RDVI3 50 V 100 0.6 V 200 KΩ EN INPUT PIN High-level input voltage VIH4 Low-level input voltage VIL4 Input hysteresis voltage VIHYS4 0.1 Pull-down resistance RDVI4 50 V 0.8×V3RO 0.2×V3RO V 0.35 0.6×V3RO V 100 200 KΩ 0.2 V 10 µA DIGITAL OUTPUT PIN (SO, FG, DIAG, RXD) Output voltage VOL Output leakage current ILOLK Io=1mA pull-up current www.onsemi.com 11 LV8907UW Parameter Symbol Condition Min Typ Max Unit 90 100 110 mV 180 200 220 mV +10% V 0.075 V CURRENT LIMIT / OVER-CURRENT PROTECTION (RF, RFSENS) Current limit voltage Over-current detection Voltage threshold VRF1 VRF2 Voltage between RF and RFSENS Voltage between RF and RFSENS EXTERNAL THERMAL PROTECTION (TH) Threshold Voltage Falling Hysteresis range VTH0 THTH[1:0]=00 VTH1 THTH[1:0]=01 VTH2 THTH[1:0]=10 VTH3 THTH[1:0]=11 VTHHYS 0.35 −10% 0.30 0.25 0.20 0.025 0.05 THERMAL PROTECTION Thermal warning temperature Thermal warning temperature hysteresis Thermal shutdown temperature Thermal shutdown temperature hysteresis (Junction temperature) (Note5) TTW0 TSTS=0 125 TTW1 TSTS=1 150 TTWHYS (Junction temperature) (Note5) °C °C 25 (Junction temperature) (Note5) TTSD0 TSTS=0 150 TTSD1 TSTS=1 175 TTSDHYS (Junction temperature) (Note5) °C °C 25 VOLTAGE MONITORING (VS, CHP, VGL, VCC) VS under-voltage detection VS under-voltage detection hysteresis VSLV 4.8 VSLVHYS 0.1 VS Over-voltage detection VSHV Over-voltage detection hysteresis CHP under-voltage detection CHP under-voltage detection hysteresis VGL under-voltage detection VGL under-voltage detection hysteresis VCC3.3 under-voltage detection VCC3.3 under-voltage detection hysteresis VCC5.0 under-voltage detection VCC5.0 under-voltage detection hysteresis 20 VSHVHYS 0.5 CHPLV 0.2 VGLLV 4.5 VGLLVHYS 0.2 VCLVHYS3 VCLV5 VCLVHYS5 1.0 VS+4.5 CHPLVHYS VCLV3 0.25 REGSEL=0, VCCEN = 1, VCLVPO=0 REGSEL=0, VCLVPO=0 REGSEL=1, VCCEN = 1, VCLVPO=0 REGSEL=1, VCLVPO=0 www.onsemi.com 12 0.4 0.4 2.3 0.1 0.25 3.8 0.1 0.25 5.1 V 0.4 V 24 V 1.5 V VS+5.5 V 0.7 V 5.5 V 0.7 V 2.7 V 0.4 V 4.2 V 0.4 V LV8907UW Parameter Symbol Condition Min Typ Max Unit LIN_PWMIN PIN (LIN TRANSMITTER) LIN output current bus in dominant state LIN output current bus in recessive state Short circuit current limitation Internal Pull-up resistance Ibus_pas_dom Ibus_pas_rec Ibus_lim Rslave Driver OFF Vbus=0V,VS=7V & 18V −1 mA Driver OFF Vbus=VS,VS=7V & 18V Driver ON Vbus=VS, VS=7V & 18V 40 VS=7V & 18V 20 30 20 uA 200 mA 47 kΩ LIN_PWMIN PIN (LIN RECEIVER & PWMIN) High-level input voltage Vbusdom VS=7V & 18V 0.6×VS VS V Low-level input voltage Vbusrec VS=7V & 18V 0 0.4×VS V Input hysteresis voltage Vbushys VS=7V & 18V 0.05×VS 0.2×VS V 0.396 0.5 0.5 0.581 0.417 0.5 0.5 0.59 AC characteristics LIN_PWMIN PIN Duty cycle 1 D1 Duty cycle 2 D2 Duty cycle 3 D3 Duty cycle 4 D4 Propagation delay bus recessive to RXD=high Propagation delay bus dominant to RXD=low Symmetry of receiver propagation delay THrecmin=0.422VS THdommin=0.284VS VS=7.6V…18V, tbit=50µs D1=tBusrecmax/(2*tbit) THrecmax=0.778VS THdommax=0.616VS VS=7.0V…18V, tbit=96µs D1=tBusrecmin/(2*tbit) THrecmin=0.389VS THdommin=0.251VS VS=7.6V…18V, tbit=96µs D1=tBusrecmax/(2*tbit) Trx_pdr VS=7V & 18V 6 µs Trx_pdf VS=7V & 18V 6 µs Trx_sym trx_pdr-Trxpdf 2 µs 22.5 µs 22.5 µs 4 µs 27 µs 27 µs 5 µs 62 µs Normal Slope rise time 12 Normal Slope fall time 12 L1,L2 (Note 6) VS=12V,LINSLP=0 T_fall_norm 12 L1,L2 (Note 6) VS=12V,LINSLP=0 symmetry of Normal Slope 12 T_sym_norm 12 L1,L2 (Note 6) T_rise_norm 3 VS=12V,LINSLP=0,L3 (Note 6) Normal Slope fall time 3 T_fall_norm 3 VS=12V,LINSLP=0,L3 (Note 6) symmetry of Normal Slope 3 T_sym_norm 3 VS=12V,LINSLP=0,L3 (Note 6) T_rise_low VS=12V,LINSLP=1,L3 (Note 6) Low Slope rise time −2 VS=12V,LINSLP=0 T_rise_norm 12 Normal Slope rise time 3 THrecmax=0.744VS THdommax=0.581VS VS=7.0V…18V, tbit=50µs D1=tBusrecmin/(2*tbit) −4 −5 Low Slope fall time T_fall_low VS=12V,LINSLP=1,L3 (Note 6) 62 µs Note 4: Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Note 5: Not tested in production. Guaranteed by design. Note 6: Load conditions Rbus/Cbus: L1=1kΩ/1nF, L2=660Ω/6.8nF, L3=500Ω/10nF Typical Operating Conditions www.onsemi.com 13 LV8907UW DETAILED FUNCTIONAL DESCRIPTON • • • The LV8907 integrates full sensor-less brushless DC motor commutation and Proportional/Integral (PI) speed control. A robust startup algorithm combined with OTP registers for important system parameters make this IC a solution of choice for many BLDC applications which need to turn a motor in one direction only such as pumps, fans, etc. No detailed BLDC commutation knowledge is necessary. In case of system errors such as a missing control signal, or a watchdog error, the LV8907 includes auto-run settings. If one of those errors occur and connection to the microcontroller is lost, the motor can continue running at a pre-defined fixed duty cycle of 25%, 50%, 75% or 100%. Building a BLDC application with the LV8907 is even simpler than building a DC motor. Only a PWM pulse train is necessary to control the motor – either directly or via speed control. Switch-only applications are also possible. Speed and error information can be fed back to the control unit via FG and DIAG outputs. Motor Commutation Motor position is detected using the BEMF of the un-driven phase of a rotating three-phase motor relative to its neutral point connected to COM. Once an adequate BEMF level has been detected voltages applied via PWM to the other two phases of the motor maintain rotation. The digital equivalent of the BEMF signal appears at FG. If more complex operation and flexibility are required the LV8907 can be combined with a small microcontroller. The LV8907 implements motor commutation and includes all necessary support circuitry for the microcontroller such as: • Integrated watchdog timer. LIN Transceiver. External Temperature Sensor. Two different PWM patterns can be selected via register MRCONF12 to match motors with trapezoidal or sinusoidal BEMF. 5V/3.3V Power supply. Figure 5: Trapezoidal vs. Sinusoidal Drive @ 50% Duty cycle (CH1&3=Phase Voltage, CH2=Phase Current, CH4=Speed signal FG) Figure 5 shows a comparison of a motor driven with normal trapezoidal commutation (left) vs. one driven with sinusoidal drive. With sinusoidal drive each phase is driven 150 electrical degrees with soft transitioning. This results in sinusoidal drive current with lower total harmonic distortion, reducing both torque ripple and noise. Trapezoidal drive results in a higher voltage across the motor phases and may be preferable for high torque and high speed operation. positioning and allows for higher motor speeds at the expense of efficiency. Advancing commutation can be done dynamically by a companion microcontroller. Maximum Motor Speed Open-loop operation is motor parameter dependent. The most critical parameters depend on load and motor inertia. They are initial commutation frequency and PWM duty cycle (which affects motor flux density). Motor Startup BEMF is used for rotor position sensing but for BEMF generation the motor has to be rotating. A stopped motor will initially be driven open-loop until BEMF can be detected. The maximum physical motor speed of the application is limited by the internal clock to approximately 48000 electrical RPM. If this is exceeded the LV8907 coasts the motor until BEMF detection and drive can resume. In the LV8907, the initial commutation frequency is programmed with register STOSC. Flux density is regulated by limiting startup current with a current ramp. During this ramp the current limit is increased in 16 steps from 0 to the maximum current defined by the external shunt. The ramp time from 105ms to 6.72s is Commutation Angle Adjustment In trapezoidal commutation mode it is possible to advance the commutation angle by up to 28 electrical degrees as defined in register LASET. Early commutation adjusts the rotor magnetic field www.onsemi.com 14 LV8907UW defined in register SSTT. Register SSTEN allows to disable the current ramp if necessary. Fixed motor speed will be applied until either a valid BEMF has been detected in all three phases or the startup timer expires. A high level on WAKE > 2.5V (max.) activates the IC from sleep mode which enables the internal linear regulator at V3RO. Once the voltage on V3RO as sensed on V3RI has passed the power on reset (POR) threshold the system oscillator starts, and after 32 counts of the system clock (3.2µs typical) releases the internal digital reset which simultaneously starts the external regulator VCC and the charge-pump, and loads the system register contents from OTP into the internal registers. During the entire wake-up sequence of 8ms (typ.) DIAG is masked for charge-pump and VCC under-voltage. After wake-up is complete, the IC enters Standby mode and DIAG is activated to display internal errors. During Standby mode full SPI access is possible. A high on EN takes the LV8907 from Standby to Normal mode. Normal mode allows motor control and SPI access is limited. A low on EN disables the motor stage regardless of the PWM input and returns the part back to Standby mode. The IC is shut down by taking WAKE below 0.6V (min.). WAKE has priority over the state of EN, if EN hold functionality is desired; it needs to be implemented with an external diode from EN to WAKE. Motor Lock This timer begins after the end of the current ramp and can be programmed from 420ms to 6.72s in register CPTM. If the timer expires a locked rotor error is flagged. In automatic retry mode, the LV8907 will restart after standby mode for time of eight times of CPTM. Spin-up of Rotating Motors The LV8907 can perform free-wheeling detection before applying the open loop spin-up algorithm described above. If the motor is already turning in the right direction the IC will continue with closed loop commutation. If the motor is turning in the wrong direction, the IC will wait for the motor to stop and then perform open-loop startup. There are two scenarios where this behavior might not be desirable: 1. 2. Fast Startup is required Free-wheeling detection takes up to one electrical revolution of the motor, which may be inacceptable for some applications. In this case free-wheeling detection can be disabled by setting FRREN. See section “Fast Startup” on page 18. System States LV8907 has three operating modes. The operating modes are controlled by WAKE and EN. Sleep mode Sleep mode is a power saving mode. All circuits are powered down, charge pump is inactive and the SPI port is unusable. Activating WAKE allows the transition from the sleep mode to either Standby or Normal mode. Wind-milling backwards Should the motor be driven by some external force as it is freewheeling in the wrong direction the LV8907 will potentially wait forever. Should start-up under these conditions be required, free-wheeling detection must be disabled as well. Standby mode In Standby mode the OTP content has been transferred into the master-register. In this mode all outputs are turned off. Any internal writable register that is not locked can be configured by SPI interface. Normal mode In normal mode, outputs can be controlled and all blocks are active. All registers can be read through the SPI interface. Chip Activation, Shutdown and System States After power up of VS and WAKE above 2.5V the LV8907 wakes up. Standby mode is entered after VS has exceeded 5.5V (min.). Mode WAKE EN Internal bias Logic VCC Charge pump Drivers Sleep L × Disable Reset Disable Disable High-Z Standby H L Enable Active Enable Enable Low Normal H H Enable Active Enable Enable Enable Supply Voltage Transients falls below its under-voltage lockout level of 2.2V. The VCC regulator must be configured for 3.3V if low transient operation is desired. The LV8907 is well suited to operate during typical automotive transients. It is fully functional during start-stop transients, as it maintains all specified parameters for supply voltages from 6V < VS < 20V. If the supply voltage falls below 5V, for example during cold-cranking, under-voltage error is flagged, but digital functionality is maintained until the internal regulator If over-voltage protection is enabled in MRCONF10 an over-voltage error is indicated if the supply rises beyond 20V(min). In both under- and over-voltage error modes, the power stage drivers UH, VH, WH and UL, VL, and www.onsemi.com 15 LV8907UW WL go low, turning the external power stage high-impedance and letting the motor freewheel. The LV8907 will re-engage the motor after conditions have returned to normal. mode and can be configured via register VCCSEL to provide 5V or 3.3V. Under-voltage error is flagged if the output voltage drops below 4.2V in 5V operation, or 2.7V in 3.3V operation. System Power Supplies The VCC regulator can be enabled or disabled with register VCCEN. Three power supplies are integrated into the LV8907: • An internal 3.3V regulator provides power to the digital and interface section. • The VCC regulator can be configured to provide 5V or 3.3V to an external processor and other loads. • A dual stage charge-pump allows 100% duty cycle operation and maintains full enhancement to the power stage at low input voltages. Charge Pump Circuit for CHP and VGL LV8907 has an integrated charge pump circuit for low-side and high-side pre-driver supply. Low side drive voltage at VGL is 12V(typ.) and high side drive voltage at CHP is VS+12V(typ.). For functionality see Figure 6. Under-voltage protection for the low side drivers activates if VGL falls below 4.8V in which case the output FET’s will be turned off and VGL under-voltage error is flagged in register MRDIAG. Over-voltage protection for the high side drivers activates if VS becomes greater than 20V(min). In that event the driver stage is disabled, over-voltage error is flagged in register MRDIAG, and both VGL and CHP are discharged to prevent output circuit destruction. Internal Regulator V3RO, V3RI The internal regulator is supplied from VS, provides 3.3V at V3RO. V3RI is connected to the power supply inputs of the control and logic circuit blocks. V3RO and V3RI need to be connected externally and bypassed to the GND plane for stability. V3RO must not be used for external loads. The charge pump circuit operates nominally at 52.1KHz. A SSCG function is provided to add a spread-spectrum component for EMI reduction. VCC Regulator The VCC regulator may power external loads up to 50mA(max). VCC becomes active during Standby CCP1 CCP2 CVGL Current limitation Voltage clamping CCHP VS CP1P CP1N VGL CP2P CP2N CHP VS Supply for LS Pre-Drivers Buf Supply for HS Pre-Drivers Buf Figure 6: Charge Pump Circuit VGL(V) CHP(V) CHP 20V 12V VS VGL 12V VS 8V VS(V) 4.8 6.0 V V 8.0 V VS CP ON under voltage CHP=VS+VGL VS(V) 4.8 6.0 V V 21V CP ON CHP=VS+VGL VS over voltage VS under voltage CP ON 8.0 V 21V CP ON VGL=12V VS over voltage Figure 7: High Side and Low Side Gate Voltages 2. 3. INPUT PWM and SPEED CONTROL The LV8907 provides three speed control methods through the input PWM signal: 1. Direct PWM pass-through www.onsemi.com 16 Indirect PWM translation Closed loop speed control LV8907UW Direct PWM Pass-through Closed loop speed control The input PWM frequency and duty cycle are directly fed to the power stage. This allows a companion microprocessor direct control over duty cycle and output frequency up to 18.5kHz. No input frequency detection takes place in this mode, so 100% and 0% duty cycle can be applied. NOTE: It is important not to exceed 18.5kHz to maintain reliable back-EMF detection. When the register bit PWMF is set 1, this control method is selected. For stand-alone operation, the LV8907 offers a PI controller for motor speed which is activated by clearing bit SCEN. Frequencies above 1kHz are ignored and frequencies below 5.3Hz(typ.) are considered as 0% or 100% duty cycle (no frequency). The output PWM frequency is fixed to 19.5kHz (typ.). LV8907 provides nine target speed values which are stored in registers FGT0 to FGT8. In speed control mode the input PWM duty cycle is encoded as a selector for these registers as shown in Figure 9. A duty cycle hysteresis allows for stable register selection. Indirect PWM Translation This is the preferred mode for stand-alone operation. In this mode the input PWM signal is compared against minimum and maximum PWM frequency thresholds to allow for more robust operation. Frequencies above 1kHz are ignored and frequencies below 5.3Hz(typ.) are considered as 0% or 100% duty cycle (no frequency). The duty cycle of the PWM input signal is measured with a resolution of 9 bits. There is an inherent delay to detect and utilize this duty cycle information, the motor will not start. The delay time is determined by 100% TAGET SPEED REGISTER FGT7 1 𝑇𝑇𝑃𝑃𝑃𝑃𝑃𝑃 × �1 + �. If faster start-up is necessary, see 8 section “Fast Startup” below. If no frequency is detected after 210ms (typ.) the PWMPO flag is set in system warning register MRDIAG1. Even without PWM input the LV8907 can run as described below in section “Fast Startup”. If a valid frequency was detected, the LV8907 evaluates the input duty cycle and translates it into an output duty cycle as shown in Figure 8. The output PWM frequency is fixed to 19.5kHz (typ.). Output Duty Cycle [%] FGT6 FGT5 FGT4 FGT3 FGT2 FGT1 FGT0 0% 0 3 12.5 25 37.5 50 62.5 75 87.5 97100 INPUT PWM DUTY CYCLE [%] Figure 9: Target Speed Register Selection by Input PWM Duty Cycle A duty cycle of 50% with a variation band of 6.25% for example will select the motor speed value stored in the 4th speed register FGT4. This allows for non-linear speed curves. When using a companion microcontroller it is possible to write to the speed register in real time during operation to achieve finer RPM resolution. For more information see section “Target speed setting” on page 33. 100 The Control algorithm 50 The LV8907 controls the motor speed by comparing the selected target speed to the actual motor speed and incorporating a PI controller with configurable gains for the P and I components which are stored in register MRSPCT0 and MRSPCT1 respectively. 0 Ramping of Speed Control Values 0 10 20 30 40 50 60 70 80 90 100 Input Duty Cycle [%] While tight control is required for optimal speed tracking, it may be undesirable during large input changes as it may lead to sudden supply loading, increasing noise and motor wear. To limit the slope of the control signal, register STEPSEL imposes a ramp on an input step to slew the speed response of the motor. Figure 8: Duty Cycle Translation Input duty cycles lower than 15% are considered a motor-off command and will also reset the error registers. Input to output duty cycle translation is described by the following formula: 𝑑𝑑𝑂𝑂𝑂𝑂𝑂𝑂 = upward downward FGT8 0 , 100 , 10 (𝑑𝑑 − 15) , 7 𝐼𝐼𝐼𝐼 Decreasing motor speed too fast results in energy recuperation back into the system. To limit over-voltage during energy recuperation, the variable DWNSET allows either 1. to distribute the recuperation energy over a longer period of time or 2. to prevent energy recuperation entirely. 0 ≤ 𝑑𝑑𝐼𝐼𝐼𝐼 ≤ 15 15 < 𝑑𝑑𝐼𝐼𝐼𝐼 < 85 85 ≤ 𝑑𝑑𝐼𝐼𝐼𝐼 ≤ 100 www.onsemi.com 17 LV8907UW LIN_PWMIN direct PWM LIN Transceiver PWM command duty cycle LINIO 0 PWMIN 1 1 polarity PWMON 0 period 1 Duty Cycle Encoder 0 T=1/F Ramp Imposer PI speed controller PWMF SCEN PWMFL, FLSEL[1:0] PWMZP, ZPSEL[1:0] PDTC PDTSEL[1:0] FGTG0[6:0] ··· FGTG8[6:0] speed STEPSEL[2:0] PX[2:0], PG[2:0] DWNSET[1:0] IX[2:0], IG[2:0] Abnormal duty cycle d etected or Initial duty cycle for ‘fast start-up’ sequ en ce WDTEN WDTP WDT[5:0] WDTSEL[1:0] 19.5kHz PWM Generator Fixed Duty Cycle Generator 0%, 25%, 50%, 75% or 100% watchdog Figure 10: PWM Command Flow and Related Registers removed. For some potentially destructive faults such as over-current, FET-short circuit and locked rotor conditions, it is possible to latch the fault condition. For more information on system diagnostics see section “System Errors and Warnings” on page 20. Fast Startup It may be desirable to have the motor start immediately after EN goes high and not wait for PWM input duty cycle evaluation. Two register settings enable motor operation during this evaluation time: bit PDTC determines if the motor should be running during this time at all, and PDTSEL selects a motor duty cycle of 25, 50, 75 or 100%. This is used as the initial value of the duty cycle command for the closed loop speed control mode. To guarantee smooth transition from fast startup to PWM operation it is important to apply a comparable external PWM duty cycle at startup. Also make sure that free-run detection is disabled (FRREN=1) to improve start-up speed. LIN Transceiver LIN_PWMIN can be used as a local interconnect network (LIN) 2.2A compatible LIN transceiver by setting the LINIO bit and connecting an external microcontroller to RXD and TXD. The microcontroller must handle the LIN communication and control the LV8907 through EN, PWMIN and the SPI interface. The LIN transceiver can be switched to low slope mode to reduce electromagnetic emissions by setting LINSLP=1. For more information on the automotive LIN bus protocol consult publicly available documentation. Abnormal Duty Cycle Operation (100% or 0%) For normal duty cycle controlled operation the PWM signal is expected to have a frequency between 5.3Hz and 1kHz. If no frequency is detected, the LV8907 will flag PWMO error and enter 0% or 100% duty cycle mode depending on the level of the PWM signal (all low or all high). Operation during this mode can be selected to be either no motor operation, or motor operation at a fixed motor duty cycle of 25, 50, 75 or 100% as defined by the variables PWMFL and FLSEL or PWMZP and ZPSEL. These PWM values do not enter into the speed control loop. Gate Drive Circuit The gate drive circuit of the LV8907 includes 3 half-bridge drivers which control external N-Channel FETs for the motor phases U, V and W. The high side drivers UH, VH, WH switch their gate connection either to CHP or the respective phase connection UOUT, VOUT and WOUT. The low-side drivers are switched from VGL to the corresponding source connection SUL, SVL, SWL. Both high and low side switches are not current controlled. Slope control has to be implemented with external components. Speed Feedback FG Current shoot-through protection of the bridge-drivers is implemented by a dead-time counter that delays the turning- on of the complementary switch. The dead-time can be programmed from 100ns < tFDTI < 3.2us into 5bit parameter FDTI. The motor speed is shown at open drain output FG where the transitions are direct representations of the BEMF signal transitions on the motor. The relationship between motor rotation and FG pulses is defined in register FGOF. To protect against external shorts the drain-source voltage of the active external Power FETs is monitored as well. 4 bit register FSCDL selects a short-circuit shutoff voltage 100mV < VFSCLD < 1.6V. To suppress false triggering during the rising edge of FET activation, a four bit masking time can be programmed in FSCDT. Fault Output DIAG A low on open drain output DIAG indicates a system fault and a shutdown of the driver stage. Per default all system faults self-recover when the fault condition is www.onsemi.com 18 LV8907UW Current Limit and Over-current Shutoff a current limit blanking time 0.1us < tCLMASK < 1.6us can be programmed into register CLMASK. An integrated current sense amplifier implements current limiting and over-current shutoff by measuring the motor phase current across a single shunt between RF and RFSENS. During soft-start this current limit is ramped from 0 to 100mV in 16 steps during a programmable time 105ms < tSSTT < 6.71s as defined in register SSTT. Figure 11 on page 19 shows a summary of the current limit and the over-current shutoff, and the descriptions for each function are in the following sections. Over-current Shutoff If the bit OCPEN is set and the voltage between RF and RFSENS exceeds VRF2 = 200mV(typ.), the LV8907 goes into over-current shutoff and all gate drivers are driving low turning the power FETs high-impedance. To suppress switching transients an over-current shutoff blanking time 0.2us < tOCMASK < 3.2us can be programmed into register OCMASK. Cycle-by-cycle Current Limit If the voltage between RF and RFSENS exceeds VRF1=100mV(typ.), the active bridge is turned off until the next PWM period. To suppress switching transients Current Cycle-by-cycle Purpose Limiter Short to VS Protector Short to GND Protector Flag None OCPO FSPO FSPO Sense point Sense Resistor VRF Sense Resistor VRF FET VDS FET VDS Threshold 100mV 200mV configurable configurable Turn-off PWM FET Recovery Next PWM cycle All FET 52.4ms later All FET 52.4ms later The short protection can be latched by register setting.. OCPLT: for OCPO FSPLT: for FSPO (3) FET VDS is determined by the register FSCDL[3:0]. 0.1 to 1.6[V] step 0.1 (2) (1) (2) (2) Figure 11: Current Limit vs. Over-current Shutoff V3RI Temperature Sensing The LV8907 measures internal die temperature and implements internal thermal warning and shutoff. It is also possible to protect external devices by monitoring the voltage at pin TH. Internal and external over-temperature can shut down the driver section. TH Internal Over-temperature Measurement NTC thermistor A thermal warning is issued if the internal temperature of the device reaches approximately 25°C below the over-temperature shutoff level. The shutoff level is selected by bit TSTS as 150°C or 175°C(min). Figure 12: Example Circuit for External Temperature Sensing External Over-temperature Shutoff An analog comparator triggers external over-temperature error if the voltage at pin TH falls below the two bit programmable level 0.2V < VTHTH < 0.35V as defined by register THTH. For external temperature measurement connect a resistor between V3RO and TH and an NTC between TH and AGND. The programmed threshold voltage at VTHTH should be reached at the intended thermal shutdown temperature of the external component to be protected. During the over-temperature condition, the gate drivers are disabled and a flag, THPO in MRDIAG0 is set. Watchdog Operation The LV8907 includes a watchdog timer to monitor a companion microcontroller and disable the motor if the microcontroller stops working properly. Bit WDTEN enables and disables the watchdog timer. Access to this bit can be blocked – see section “OTP Registers” on page 37 for details. The enabled watchdog will issue an error whenever the watchdog time 1.64ms < tWDT < 104.96ms expires. A write of 00h to register MRST resets the watchdog timer. www.onsemi.com 19 LV8907UW A watchdog timeout can result in either a motor stop, or motor operation at four predefined duty cycles (25%, 50%, 75%, 100%) as defined by WDTP and WDTSEL. The duty cycle is directly applied to the power stage, not through the speed selection registers. The microprocessor is not re-set. Errors that may cause serious damage such as short-circuit, over-current and locked rotor can be latched by enabling the corresponding latch bit in MRCONF10. In this case the LV8907 will keep the output stage disabled until the latch is cleared by one of the following actions: • Power on reset. • EN low. • Low frequency PWM less than 15% duty cycle. • SPI write of FFh to MRRST. If bit DLTO is set ONLY latched errors will cause a transition of DIAG. To detect the other less serious errors and warnings, the diagnostic registers MRDIAG0/MRDIAG1 have to be read regularly via SPI access. System Errors and Warnings All system errors and most warnings cause a transition on DIAG. The polarity of this transition can be selected in bit DIAGSEL. The ability of stand-alone applications without microcontroller to react to errors and warnings is limited. For this case various auto-retry strategies are implemented. If a companion microcontroller exists, more complex error handling is possible and DIAG should be connected to an interrupt input of the microcontroller. Error OCPO VSLVPO VSOVPO CHPLVPO VGLLVPO FSPO THPO CPO Description Over-current Error VS Under-voltage VS Over-voltage CHP Under-voltage VGL Under-voltage FET Short Circuit TH Over-temperature Locked Rotor Latchable Bit 0 1 2 3 4 5 6 7 Maskable Table 1) Error Register: MRDIAG0[7:0] X X X X X X X X Self Recovery when latch function turned off After 52.4ms (typ.) the motor will re-start. Motor is re-started when voltage recovers. Motor is re-started when voltage recovers. Motor is re-started when voltage recovers. Motor is re-started when voltage recovers. After 52.4ms (typ.) the motor will re-start. Motor is re-started when temperature recovers. Wait 8 tCPTM periods (see “Motor Lock” on page 15) See register MRCONF10 for error activation and masking and MRCONF11 for latching options. Warning THWPO 1 THSPO 2 WDTPO Description Junction Temp. Warning Junction Over-temperature Watchdog Timeout 3 4 STUPO SPCO Startup Operation Loss of speed lock 5 6 7 Internal Use VCLVPO PWMPO VCC under-voltage PWM Input Fault Blankable Bit 0 DIAG Table 2) Warning Register: MRDIAG1[7:0] X X X X X X X X Effect The IC has exceeded the warning temperature but stays in Normal operation. The IC has exceeded the shutoff temperature. Drivers are shut down during over-temperature. Driver stage is shut off or continues with pre-selected duty cycle (25, 50, 75, 100%). The motor is running open loop. Target speed and actual speed are more than 6.25% different. Driver stage off. No PWM signal detected. Driver stage is shut off or continues with pre-selected duty cycle (25, 50, 75, 100%). *An “X” in column “DIAG Blank” means that it is possible to prevent a warning from triggering DIAG see register MRCONF10 for details. SPI Interface In the LV8907 the SPI interface is used to perform general communications for status reporting, control and programming. www.onsemi.com 20 LV8907UW (1) Communications must be full duplex and simultaneous. It is not allowed to send one transaction and then read data on a second transaction as the status register information will be updated on the first transaction and then be out of date for the second. Some systems break transactions into separate read and write operations which is not acceptable with the LV8907. (2) It is important the system master uses the clock and data polarities and phases as shown above. Both the clock and data on some systems can be inverted for various reasons but must arrive at the LV8907 per the above drawing. Common errors include SCLK inversion such that the leading edge arrives as a downward transition rather than a rising edge, or having the data to clock phase incorrect. Data phase must be such that the data only changes during a clock falling edge and is completely stable during a clock rising edge. This means a good margin of one half of a bit time exists to eliminate transmission delay hazards. Figure 13: SPI Format SPI communications with the LV8907 follows established industry standard practices including the use of WEN and start and stop bits as shown above. Data is transferred MSB first and both clock and data are transferred as ‘true’ data with the higher level indicating a logical 1 or true state. If WEN is LOW, the register data is transferred from LV8907 to the microcontroller. If WEN is HIGH, the register data is transferred from the microcontroller to the LV8907 register. The first byte returned on all transactions is always the status register, GSDAT, and contains information such as the busy flag during programming operations. There are two items to be especially careful of with the general communication scheme: GSDAT[7:0] Bit 7 6 ORBEN 0 STUPO x 5 4 3 2 SACF DIAGS LATCH OBSY x 0 0 1 Bit 0 SMOD[1:0] 0 0 1 1 x 0 1 0 1 0 1 x 1 1 0 1 0 1 1 • The following SPI failures are detectable and reported collectively in GSDAT as general SPI failures: • • • • Any access to an address which are outside the defined address space. The number of SCLK transitions is not 16 within one word transfer. Any access to MRCONF, MRACS, ORCONF, ORACS while OBSY=1 (during write operations) Write access to MRODL register while OBSY=1 (during write operations.) • • • www.onsemi.com 21 Sleep mode (MRACK[7:0]=FFh) Device start up time Standby mode Normal mode (MRACK [7:0]=55h) Normal Operation OTP busy with read/write access Latched shutdown condition Failure Condition Last SPI access OK Last SPI access failed* Motor in Startup mode Motor in Normal drive mode OTP integrity test mode Write access to any of the main registers after setting MSAENB=1 (Implies MRxxxx registers are locked). Write access to any of the OTP registers after OSAENB=1 (Implies ORxxxx registers are locked). . Write access attempt to a read only or locked register. SI signal changed at positive edge of SCLK. (Incorrect data/sclk phase setup) LV8907UW SPI Timing 90% 90% CSB 10 % 10 % Tcss 1 / Tfck Tckn 90% SCLK 10% SI Tckp 10 % 10% Tsis Tsih 90% 90% 10 % 10% Tcsh Tcsp 90 % Tcssod SO 90% 10% Tcksod 90 % 90% 10% 10% Tcssoz Tcssoo Figure 14: SPI Timing Chart Tj=-40 to 150°C, VS=4.5 to 20V Pull-up resistance of SO pin=2.4kΩ, Output load of SO pin=30pF Symbol Tfck Tckp Tckn Tcss Tcsh Tcsp Tsis Tsih Tcssod Tcksod Tcssoo Tcssoz Comment SCLK clock frequency SCLK high pulse width SCLK low pulse width CSB setup time CSB hold time CSB high pulse width SI setup time SI hold time CSB fall edge to SO delay time SCLK fall edge to SO delay time CSB fall edge to SO data out time CSB rise edge to SO Hi-Z out time Min Typ Max 500 950 950 950 950 1900 450 450 950 950 0 950 www.onsemi.com 22 Unit kHz ns ns ns ns ns ns ns ns ns ns ns LV8907UW REGISTER DESCRIPTION SPI Register Map The SPI interface allows read access to the entire address space. The MASTER registers can only be written in Standby mode and then only if the write lock bit MSAENB has never been set high. Addr Register Description Write Enable Standby Mode Normal Mode IC Setup Register 00h MRCONF0 Main function Free-run Detection ON/OFF setup MSAENB 01h MRCONF1 PWM Input Specification MSAENB 02h MRCONF2 03h MRCONF3 04h MRCONF4 Activation frequency setup MSAENB 05h MRCONF5 Current limit detection timing setup / Over-current detection setup MSAENB 06H MRCONF5 For Internal Use Only MSAENB 07h MRCONF7 08h MRCONF8 09h MRCONF9 0Ah MRCONF10 0Bh MRCONF11 0Ch MRCONF12 Soft-start EN setup / FG output setup / Dead time setup PWM undetected operation mode setup Soft-start setting Sync rectification setup Protection setup FET short Protection SSCG Protection setup Locking Protection Overheat protection WDT setup MSAENB MSAENB MSAENB MSAENB MSAENB Error / warning masks and DIAG output setup Speed FB operation setup at deceleration WDT protection operation setup Latch setup Lead angle setup Silent drive setup STEP at the time of changing Speed FB target revolution MSAENB Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read Read Read Read Read Read Read Read Read Read Read MSAENB Read / Write Read Always OK Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Read / Write Speed Control Setup 10h MRSPCT0 Proportional Gain Setup Always OK 11h MRSPCT1 Integral Gain Setup Always OK 12h MRSPCT2 3.125% Input PWM Always OK 13h MRSPCT3 12.5% Input PWM Always OK 14h MRSPCT4 25% Input PWM Always OK 15h MRSPCT5 37.5% Input PWM Always OK 16h MRSPCT6 50% Input PWM Always OK 17h MRSPCT7 62.5% Input PWM Always OK 18h MRSPCT8 75% Input PWM Always OK 19h MRSPCT9 87.5% Input PWM Always OK 1Ah MRSPCT10 96.875% Input PWM Always OK www.onsemi.com 23 LV8907UW Addr Register Write Enable Description Standby Mode Normal Mode Read Read Read Read System Diagnostics and Test 20h MRACS Lock Bits for OTP and Main Register write 30h MRACK SPI Operation Diagnostics - 31h MRODL OTP data READ Always OK 32h MRRST For WDT/Protection Reset Always OK 33h MRORB For OTP Zapping check Always OK 34h MRDIAG0 Protection status check 35h MRDIAG1 Protection status check 38h TEST1 Production test register 1 Read / Write Read / Write Read / Write Read / Write - Read Read - Read Read D1 D0 Read Read … 3C TEST5 Production test register 5 OTP Memory Section 40h ORCONF0 Default states of MRCONF0 – MRCONF12 … 4Ch ORCONF12 transferred upon startup 50h ORSPCT0 Default states of MRSPCT0 – MRSPCT10 … 5Ah ORSPCT10 transferred upon startup 60h ORACS Default states of MRACS Motor Configuration Register Overview ADDR[6:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Register Name MRCONF0 MRCONF1 MRCONF2 MRCONF3 MRCONF4 MRCONF5 MRCONF6 MRCONF7 MRCONF8 MRCONF9 MRCONF10 MRCONF11 MRCONF12 D7 D6 D5 D4 D3 D2 FRMD FRREN SCEN PWMF REGSEL VCEN LINSLP FLSEL[1:0] ZPSEL[1:0] PWMFL PWMZP PDTC SSTEN FGOF[1:0] FDTI[4:0] PDTSEL[1:0] SSTT[5:0] STOSC[7:0] CLMASK[3:0] OCMASK[3:0] Internal Use Only SYNCEN PPDOSEL FSCDT[1:0] FSCDL[3:0] SSCG CPTM[3:0] THTH[1:0] WDTEN WDTP WDT[5:0] VCLVPEN CPEN THWEN THPEN FSPEN OVPEN OCPEN DWNSET[1:0] WDTSEL[1:0] CPLT FSPLT OCPLT STEPSEL[2:0] SLMD LASET[3:0] www.onsemi.com 24 LINIO PWMON TSTS DIAGSEL DLTO LV8907UW MRCONF0 Address = 00h Standby Mode: Normal Mode: Read/Write Read Only Bit 7 6 5 4 3 2 1 Bit 0 FRMD FRREN SCEN PWMF REGSEL VCEN LINSLP LINIO The following table shows the configuration summary based on the combination of SCEN and PWMF. FRMD: Forward / reverse selection The physical motor rotation direction depends on the wiring of the three phases. FRMD=1 reverses the motor direction. FRREN: Free-run detection enable Decides if the LV8907 does a BEMF detection before attempting to start the motor open-loop excitation and commutation. FRREN=0 Motor will start with a BEMF detection. FRREN=1 Motor will start open loop with startup parameters. SCEN PWMF Speed control Input PWM frequency range [Hz] Output PWM frequency 0 0 closed loop 5.3 to 1000 19.5 [kHz] 1 0 indirect translated 5.3 to 1000 19.5 [kHz] 0 1 up to 18500 1 1 direct pass-through direct pass-through same as input same as input up to 18500 REGSEL: VCC Voltage selection (5V/3.3V) REGSEL=0 VCC output set to 3.3V. REGSEL=1 VCC output set to 5V. SCEN: Speed feedback control enable This bit selects the LV8907 internal speed feedback control or PWM pass-through. Speed feedback control is active when SCEN=0. RPM is selected from input duty cycle as shown in Figure 9 on page 17. SCEN=1: The closed loop speed control is inactivated. VCEN: VCC regulator enable VCEN=0 VCC is off. VCEN=1 VCC is active. LINSLP: LIN slope mode setup PWMF: PWM input frequency selection To improve EMI performance the LIN switching slope can be reduced. LINSLP=0 Normal LIN rise-time. LINSLP=1 Rise time increased by 1/3. Decides the PWM input frequency range and PWM translation configuration. PWMF=0: Indirect PWM translation or closed loop speed control. Valid PWM input frequency from 5.3Hz to 1kHz. PWMF=1: Direct PWM pass-through. Valid PWM input frequency up to 18.5kHz. In this mode the PWM frequency is directly fed to the power stage. Internal closed loop speed control cannot be used. LINIO: External input system selection LV8907 has an embedded LIN physical layer which can also be used as a PWM input channel. LINIO=0 LIN_PWMIN is in PWM input mode. LINIO=1 The LIN transceiver is active and the PWM signal is taken from PWMIN. MRCONF1 Address = 01h Bit 7 Standby Mode: Normal Mode: 6 FLSEL[1,0] 5 4 ZPSEL[1,0] Read/Write Read Only 3 2 1 Bit 0 PWMFL PWMZP PDTC PWMON FLSEL: 100% PWM input duty cycle motor operation ZPSEL: 0% PWM input duty cycle motor operation If 100% PWM input duty cycle was detected (no PWM frequency) and PWMFL is set, the motor is driven with the duty cycle programmed into FLSEL as shown in the following table. If 0% PWM input duty cycle is detected (no PWM frequency) and PWMZP is set, the motor is driven with the duty cycle programmed into ZPSEL as shown in the following table. FLSEL[1] 0 0 1 1 FLSEL[0] 0 1 0 1 Motor Duty Cycle[%] 25 50 75 100 ZPSEL[1] 0 0 1 1 ZPSEL[0] 0 1 0 1 Motor Duty Cycle[%] 25 50 75 100 PWMFL: Operation mode selection at PWM input duty cycle = 100% If 100% PWM input duty cycle was detected the motor will be PWMFL=0: turned off. PWMFL=1: driven with the duty cycle defined by FLSEL. www.onsemi.com 25 LV8907UW PWMZP: Operation mode selection at PWM input duty cycle = 0% PDTC=0: turned off. PDTC=1: driven with the duty cycle defined by PDTSEL (MRCONF3[7,6]) If 0% PWM input duty cycle is detected the motor will be. PWMZP=0: turned off. PWMZP=1: driven with the duty cycle defined by ZPSEL. PWMON: PWM input signal level Decides whether the PWM input signal is active low, or active high. PWMON=0: PWM input signal is active high. PWMON=1: PWM input signal is active low. PDTC: Fast Startup operation mode During the first 200ms after EN high, while the PWM signal is still being measured, the motor can be either MRCONF2 Address = 02h Standby Mode: Normal Mode: Bit 7 6 5 SSTEN 4 3 Read/Write Read Only 2 FGOF[1,0] 1 Bit 0 FDTI[4:0] SSTEN: Soft-start function enable Soft-start (current ramp) allows slow startup of motors with higher inertia. The soft-start algorithm ramps the current limit from 0 to max current in 16 steps during soft-start time tSST which is programmed in register MRCONF3. SSTEN=0 Soft-start is OFF. SSTEN=1 Soft-start is active. FGOF: FG signal output frequency selection The FG signal is a representation of a successfully detected back-EMF transition which occurs three times during every electrical revolution. It is possible to divide that frequency as described in the following table. Note that soft-start typically begins after duty cycle detection. If no duty cycle operation is selected (PDTC=1) Soft-start will begin after reset. FGOF[1] 0 0 1 1 FGOF[0] 0 1 0 1 FG output mode One transition per back-EMF detection. One pulse per electrical revolution. One transition every two BEMF det. One pulse every two elec. Revolutions. temporarily on at the same time causing large current spikes. Register FDTI defines a dead time during which both drivers will be kept off during these transitions. FDTI: Dead time setting During phase switching between supply and GND it is possible for both low- and high-side drivers to be FDTI[4] 0 0 FDTI[3] 0 0 FDTI[2] 0 0 1 1 1 1 FDTI 1 1 FDTI[1] FDTI[0] 0 0 0 1 1 1 0 1 Dead time[us] 3.2 3.1 3.2 - FDTI/10 0.2 0.1 MRCONF3 Address = 03h Bit 7 Standby Mode: Normal Mode: 6 5 4 3 PDTSEL[1,0] Read/Write Read Only 2 1 Bit 0 SSTT[5:0] table, as soon as EN is high. This feature is bridging the initial 200ms of operation until a valid PWM duty cycle can be decoded. PDTSEL: Fast Start-up motor operation. If bit PDTC is set the motor is driven with the duty cycle programmed into PDTSEL as shown in the following www.onsemi.com 26 LV8907UW PDTSEL[1] PDTSEL[0] Motor Duty Cycle[%] 0 0 0 1 25 50 1 0 75 1 1 100 increases the value from 6.25mV to 100mV to switch over the current limit value. The soft start can be set from 0.1s < tSSTT < 6.71s as shown in the table below: SSTT: Soft-start time setting Soft-start allows startup of motors with higher inertia by ramping the current. The soft-start algorithm divides the current limit voltage 100mV (Typ.) into 16 sections and SSTT[5] 0 0 SSTT[4] 0 0 SSTT[3] 0 0 1 1 1 1 1 1 SSTT[2] 0 0 SSTT 1 1 SSTT[1] 0 0 SSTT[0] 0 1 1 1 0 1 Soft-start time[s] 0.105 0.21 0.105 · (1 + SSTT) 6.615 6.72 MRCONF4 Address = 04h Bit 7 Standby Mode: Normal Mode: 6 5 4 3 2 1 Bit 0 STOSC[7:0] 0 0 0 0 0 0 0 0 1 1 1 1 STOSC 1 1 1 1 This register defines the rotation frequency fSTOSC at which the motor should be turned during open-loop startup. If a BEMF signal can be detected the IC will commutate to the next energization pattern by using the zero-crossing as its reference. If no BEMF can be Read/Write Read Only Startup commutation period [ms] 0.82 0.82×(1+STOSC) 209.92 detected the IC will commutate to the next energization pattern with the frequency programmed into STOSC. Open-loop startup continues for the time programmed into CPTM (MRCONF8[6:3]) If no BEMF is detected during that time a locked rotor error is indicated. MRCONF5 Address = 05h Bit 7 Standby Mode: Normal Mode: 6 5 4 3 Read/Write Read Only 2 CLMASK[4:0] 1 OCMASK[4:0] CLMASK: Current limit mask time setting In order to prevent noise and glitches from causing false current limiting, a mask time can be programmed. CLMASK[3] 0 0 1 1 CLMASK [2] CLMASK [1] 0 0 0 0 CLMASK 1 1 1 1 CLMASK [0] 0 1 OCMASK: Over-current detection Mask time setting The time to detect over-current can be programmed with OCMASK. www.onsemi.com 27 0 1 Mask Time[us] 0.1 0.2 0.1+CLMASK/10 1.5 1.6 Bit 0 LV8907UW OCMASK[3] 0 0 OCMASK [2] OCMASK [1] 0 0 0 0 OCMASK 1 1 1 1 1 1 OCMASK [0] 0 1 Mask Time[us] 0.2 0.4 0.2 · (1+OCMASK) 3.0 3.2 0 1 MRCONF6 Address = 06h Bit 7 Standby Mode: Normal Mode: 6 5 4 3 Read/Write Read Only 2 SROFFT[3-0] 1 Bit 0 CRMASK[3-0] Internal use only. MRCONF7 Address = 07h Standby Mode: Normal Mode: Bit 7 6 5 SYNCEN PPDOSEL 4 3 Read/Write Read Only 2 FSCDT[1:0] FSCDL[3:0] Defines synchronous rectification mode for the output stage. In synchronous rectification the high and low side switches are always switched in complementary mode = if one switch is on, the other one is off . In a-synchronous rectification both complementary switches may be off and the motor current is circling through the body diodes. SYNCEN=0 Synchronous rectification is ON. SYNCEN=1 Synchronous rectification is OFF. FSCDT: FET Short protection detection time setting By monitoring FET Vds, the time from FET’s ON signal output until detecting Shorted status can be set with D5 and D4 of MRCONF7. Please refer to the table below for settable time: FSCDT[1] 0 0 1 1 PPDOSEL: DIAG output selection at PWM input abnormality D6 of the main register MRCONF7 can be used to reflect abnormal detection result to DIAG pin at the time of PWM input abnormal detection (0% or 100% detection). PPDOSEL=0 PWM abnormal input detection result is reflected to DIAG pin when FSCDL[2] 0 0 1 1 1 1 Bit 0 PPDOSEL=1 and it is not reflected to DIAG pin when. SYNCEN: Synchronous rectification enable FSCDL [3] 0 0 1 FSCDT [0] Detection time[us] 0 1 0 1 3.2 6.4 9.6 12.8 FSCDL: FET Short protection detection voltage setting Vds voltage to detect FET Short status can be set with D3~D0 of MRCONF7. Please refer to the table below for available voltages: FSCDL [1] 0 0 FSCDL [0] 0 1 1 1 0 1 Vth[V] 0.1 0.2 0.1+FSCDL/10 1.5 1.6 FSCDL MRCONF8 Address = 08h Bit 7 Standby Mode: Normal Mode: 6 5 SSCG 4 3 CPTM[3-0] Read/Write Read Only 2 1 THTH[1,0] SSCG=0: Spread spectrum OFF SSCG=1: Spread spectrum ON SSCG: Charge Pump Spread Spectrum The Charge pump may have radiation noise issues due to switching at 52.1kHz(typ.). By activating SSCG it is possible to disperse frequency components of the charge pump switching frequency. The frequency will vary 20%. www.onsemi.com 28 Bit 0 TSTS LV8907UW CPTM: Open Loop Startup Timeout CPTM register the motor is turned off and a locked rotor is flagged. In Auto recovery mode the motor will remain off for eight times the Open Loop Startup Timeout before another startup is attempted. A locked rotor protection circuit is embedded in order to protect IC and Motor during locked rotor conditions. A locked rotor is detected by counting the time the IC is in Start-up mode (without back-EMF detection) If no back-EMF is detected for the time programmed into CPTM [3] 0 0 CPTM [2] 0 0 1 1 1 1 CPTM [1] 0 0 CPTM 1 1 CPTM [0] 0 1 0 1 threshold level (shown in the table), the external over-temperature protection is activated, the output gate driver stage is turned off and the THPO error flag is set. THTH: Threshold for External Thermometer Input LV8907 has an embedded comparator to monitor the external power FET’s temperature using an external thermistor. If the voltage at TH drops below the THTH[1] 0 0 1 1 Detection/Restart time[s] 0.42 / 3.36 0.84 / 6.72 0.42 · (1+CPTM) / 3.36 · (1+CPTM) 6.3 / 50.4 6.72 / 53.76 THTH [0] 0 1 0 1 VTH[V] 0.35 0.30 0.25 0.20 TSTS=0: Over-temperature warning occurs at 125℃(typ.), shutdown at 150℃(typ.). TSTS=1: Over-temperature warning occurs at 150℃(typ.), shutdown at 175℃(typ.). TSTS: Junction temperature warning and shutoff levels The LV8907 monitors its own junction temperature to protect against over-temperature damage. Two different warning and shut-off levels can be selected: MRCONF9 Address = 09h Standby Mode: Normal Mode: Bit 7 6 WDTEN WDTP 5 4 3 Read/Write Read Only 2 1 Bit 0 WDT[5:0] WDTEN: Watchdog enable WDTP: Operation against watchdog timeout This bit can enable or disable the watchdog. For increased system robustness it is possible to permanently lock access to this bit. See OTP section for more details. WDTEN=1 Watchdog is active. WDTEN=0 Watchdog is disabled. Operation mode against watchdog time can be selected. WDTP=0 Motor off. WDTP=1 Motor is driven with the PWM duty cycle as defined by WDTSEL (MRCONF11[5,4]). WDT: Watchdog timer setting The end time of the watchdog timer is defined by register WDT. WDT [5] 0 0 WDT [4] 0 0 1 1 1 1 WDT [3] WDT [2] 0 0 0 0 WDT 1 1 1 1 WDT [1] 0 0 WDT [0] 0 1 1 1 0 1 www.onsemi.com 29 Detection Time[ms] 1.64 3.28 1.64 · (1+WDT) 103.32 104.96 LV8907UW MRCONF10 Address = 0Ah Standby Mode: Normal Mode: Read/Write Read Only Bit 7 6 5 4 3 2 1 Bit 0 VCLVPEN CPEN THWEN THPEN FSPEN OVPEN OCPEN DIAGSEL • • • xEN: Error and warning mask The higher seven bit in this register allows enabling and disabling of various errors and warnings. A one in the register masks the error, a zero activates the protection. The following errors and warnings can be masked: • VCLVPEN = 0: VCC Under-voltage protection enabled • CPEN = 0: Motor block protection enabled • THWEN = 0: Thermal warning output enabled • THPEN = 0: Thermal protection enabled FSPEN = 0: FET short protection enabled OVPEN = 0: Over-voltage protection enabled OCPEN = 0: Over-current protection enabled DIAGSEL: Diagnosis output polarity selection This bit selects the polarity of the DIAG signal DIAGSEL=0 The DIAG pin is active low. DIAGSEL=1 The DIAG pin is active high and draws pull-down current when off. MRCONF11 Address = 0Bh Bit 7 Standby Mode: Normal Mode: 6 DWNSET[1,0] 5 4 WDTSEL[1,0] 3 2 1 Bit 0 CPLT FSPLT OCPLT DLTO • DWNSET: Mode setting at the time of speed feedback deceleration During speed control mode, motor deceleration can lead to energy recuperation and temporary voltage spikes. DWNSET allows for various degrees of energy recuperation: • Normal Mode Results in a tightest control and maximum energy recuperation. The application circuit has to be able to absorb the energy generated. DWNSET[1] 0 0 1 1 • DWNSET [0] 0 1 0 1 Read/Write Read Only Sync OFF Mode The motor is essentially not driven until it has reached the target speed. This does not feed any energy back into the supply, but may take a long time if motor inertia is high and losses are low. Slow Response Mode This mode is essentially imposing a slow deceleration ramp on the control speed. The energy recuperated is similar to Normal Mode but spread over a longer period of time reducing the voltage overshoot. Mode Normal Mode Sync OFF Mode Slow Response Mode (PROT/32) Normal Mode When Drive mode is selected the motor duty cycle is defined by WDTSEL as shown in the table below. WDTSEL: Operation mode selection after a Watchdog timeout Bit WDTP (MRCONF9[6]) defines if a Watchdog timeout causes Halt mode (0% drive) or Drive mode. WDTSEL[1] 0 0 1 1 WDTSEL[0] 0 1 0 1 Duty[%] 25 50 75 100 CPLT=0 Auto recover after a motor block. CPLT=1 Latch the IC off after a motor block. xPLT: Protection Latch selection The faults of the motor block, FET Short and over-current can cause intolerable large-current. To prevent repeated current flow during re-try attempts, it is possible to latch these errors. The LV8907 will remain disabled until the latch is cleared by the register MRRST. FSPLT=0 Auto recover after a FET short. FSPLT=1 Latch the IC off after a FET short. OCPLT=0 Auto recover after over-current. OCPLT=1 Latch the IC off after over-current. www.onsemi.com 30 LV8907UW DLTO: Diagnostic output mode selection DLTO=0: Trigger DIAG for any non-masked error or warning. DLTO=1: Trigger DIAG only for latched errors as defined by xPLT above. Selects which errors/warnings will actually trigger a DIAG transition. MRCONF12 Address = 0Ch Standby Mode: Normal Mode: Bit 7 6 5 4 STEPSEL[2-0] 3 SLMD Read/Write Read/Write* 2 1 Bit 0 LASET[3-0] *Note: This register is writeable in Normal mode. is allowed to change. This limit is defined by STEPSEL in register MRCONF12[7-5]. STEPSEL: Ramp imposed on speed control changes In speed control mode, large steps in motor target speed can cause excessive current spikes, noise and wear on the mechanical components. The LV8907 allows to impose a limit on the difference between target speed and actual speed such that every electrical revolution only a fraction of the previous rotational (PROT) speed Note: During closed loop speed control optimization and/or evaluation, it might be useful to turn off this ramp imposing (STEPSEL[2:0]= 0b000). Figure 15 shows the RPM ramping response to an input step for six different ramp settings for instance. Target Speed Transistion by Setting of the Register STEPSEL Example Case of 1000rpm to 5000rpm Vice Versa PROT PROT/2 PROT/4 PROT/8 PROT/16 PROT/32 6000 Target Speed (rpm) 5000 4000 3000 2000 1000 0 0 20 40 60 80 100 the Number of Electrical Cycle (FG counts) 120 140 Figure 15: Speed Control Input Ramp of Different STEPSEL Settings STEPSEL[2] 0 0 0 0 1 1 1 1 STEPSEL[1] 0 0 1 1 0 0 1 1 STEPSEL[0] 0 1 0 1 0 1 0 1 Step Mode PROT (Current electrical speed at FG) PROT/2 PROT/4 PROT/8 PROT/16 PROT/32 PROT PROT SLMD=0 Trapezoidal drive with 120 degrees energization. SLMD=1 Sinusoidal drive with 150 degrees energization. SLMD: Sinusoidal vs. trapezoidal drive mode selection This bit selects whether the motor phases are driven with a trapezoidal or pseudo-sinusoidal signal. www.onsemi.com 31 LV8907UW back-EMF signal. This helps to achieve back-EMF field-weakening for higher rotational speeds and to compensate for delays in high speed operation. LASET: Lead angle setting In trapezoidal drive mode it is possible to advance the commutation point towards zero-crossing of the LASET [3] 0 0 LASET [2] 0 0 1 1 1 1 LASET [1] 0 0 LASET [0] 0 1 1 1 0 1 Lead Angle[deg] 0 1.875 LASET · 1.875 26.25 28.125 LASET Speed Control Register Overview Register Name MRSPCT0 MRSPCT1 MRSPCT2 MRSPCT3 MRSPCT4 MRSPCT5 MRSPCT6 MRSPCT7 MRSPCT8 MRSPCT9 MRSPCT10 ADDR[6:0] 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah D7 D6 - D5 D4 PX[2:0] IX[2:0] Closed loop motor rotation speed controller (PI) is provided. The block diagram is shown in Figure 16. Where, TAG: target speed (period) PROT: previous speed feedback (period) Int: previous sum K: scaling factor 𝑉𝑉𝑉𝑉 𝐾𝐾 = 128 × 512 + Pg FGT0[6:0] FGT1[6:0] FGT2[6:0] FGT3[6:0] FGT4[6:0] FGT5[6:0] FGT6[6:0] FGT7[6:0] FGT8[6:0] D2 D1 PG[2:0] IG[2:0] Drive Voltage Px K Ig D0 Proportional Gain can be set with PX and PG of MRSPCT0 where the total gain is the product of both components PG and PX. Integral Gain can be set with IX, and IG of MRSPCT1 respectively. These P and I parameters can be changed while a motor is running (i.e. EN = HIGH). MRSPCT0 must be written, followed by writing MRSPCT1 through SPI. To update the P and I parameters of the control logic block simultaneously, MRSPCT0 code is suspended until MRSPCT1 is written. The calculation operates every FG cycle. The period is measured by 104kHz clock. Speed control loop gain setting TAG - D3 Ix Int PROT Figure 16: PI Speed Controller Block Diagram www.onsemi.com 32 LV8907UW PX, IX [2] 0 0 0 0 1 1 1 1 PX, IX [1] 0 0 1 1 0 0 1 1 PX, IX [0] 0 1 0 1 0 1 0 1 Gain 1 2 4 8 16 32 64 0 PG, IG [2] PG, IG [1] PG, IG [0] Gain 0 0 0 1 0 0 1 7/8 0 1 0 6/8 0 1 1 5/8 1 0 0 4/8 1 0 1 3/8 1 1 0 2/8 1 1 1 1/8 The proportional gain is a product of PX and PG, and the integrator gain is a product of IX and IG. Value 0.125 0.250 0.250 0.375 0.500 0.500 0.500 0.625 0.750 0.750 0.875 1.000 1.000 1.000 1.000 1.250 1.500 1.500 1.750 2.000 2.000 2.000 2.000 2.500 3.000 3.000 3.500 4.000 4.000 4.000 4.000 5.000 6.000 6.000 7.000 8.000 8.000 8.000 8.000 10.000 12.000 12.000 14.000 16.000 16.000 16.000 20.000 24.000 24.000 28.000 32.000 32.000 40.000 48.000 56.000 64.000 Px Ix Factor x1 x1 x2 x1 x1 x2 x4 x1 x1 x2 x1 x1 x2 x4 x8 x2 x2 x4 x2 x16 x2 x4 x8 x4 x4 x8 x4 x16 x32 x4 x8 x8 x16 x8 x8 x16 x32 x64 x8 x16 x16 x32 x16 x16 x32 x64 x32 x32 x64 x32 x32 x64 x64 x64 x64 x64 Setting 0 0 1 0 0 1 2 0 0 1 0 0 1 2 3 1 1 2 1 4 1 2 3 2 2 3 2 4 5 2 3 3 4 3 3 4 5 6 3 4 4 5 4 4 5 6 5 5 6 5 5 6 6 6 6 6 Pg Ig Factor x1/8 x2/8 x1/8 x3/8 x4/8 x2/8 x1/8 x5/8 x6/8 x3/8 x7/8 x1 x4/8 x2/8 x1/8 x5/8 x6/8 x3/8 x7/8 x1/8 x1 x4/8 x2/8 x5/8 x6/8 x3/8 x7/8 x2/8 x1/8 x1 x4/8 x5/8 x3/8 x6/8 x7/8 x4/8 x2/8 x1/8 x1 x5/8 x6/8 x3/8 x7/8 x1 x4/8 x2/8 x5/8 x6/8 x3/8 x7/8 x1 x4/8 x5/8 x6/8 x7/8 x1 Setting 7 6 7 5 4 6 7 3 2 5 1 0 4 6 7 3 2 5 1 7 0 4 6 3 2 5 1 6 7 0 4 3 5 2 1 4 6 7 0 3 2 5 1 0 4 6 3 2 5 1 0 4 3 2 1 0 Thus, there are some duplication with responding to the combination of X and G. Target speed setting There are two ways of setting a target speed with speed control active (SCEN=0): 1. By using a companion microprocessor to write the speed value directly into the Speed Control Register via SPI. 2. By applying a low frequency PWM input which selects a target speed from the Speed Control Register. www.onsemi.com 33 LV8907UW SPI Speed Control There is a hysteresis of 6.25% duty cycle around each typical value resulting in the duty cycle thresholds depicted in Figure 9 on page 17. The motor speed is defined as ERPM (Electrical Revolutions Per Minute). To calculate the physical rotational speed RPM of the motor divide ERPM by the number of pole pairs of the motor. Each of the nine registers (FGT0[6:0] to FGT8[6:0]) selected by the input PWM above has 7 bits to program ERPM in a piecewise exponential function. For SPI speed control the companion microprocessor should apply a fixed duty cycle PWM signal to the LV8907 PWMIN pin. An input duty cycle of 12.5% would then select speed register MRSPCT3 as shown in the table below. By writing RPM values to register MRSPCT3 via SPI, the speed can be controlled directly. PWM Speed Control PWM input frequency must be in Low frequency mode (PWMF=0). In this mode the PWM input duty cycle is measured and used to select a target speed from the Speed Control Registers MRSPCT2..10. Note that 0% and 100% input duty cycle will be flagged as a “PWM Input Fault” Input Duty Cycle(%) Register (center value of the range) 0 0% Duty Operation* (3.125) MRSPCT2 12.5 MRSPCT3 25 MRSPCT4 37.5 MRSPCT5 50 MRSPCT6 62.5 MRSPCT7 75 MRSPCT8 87.5 MRSPCT9 (96.875) MRSPCT10 100 100% Duty Operation* *See page 18: Abnormal Duty Cycle Preset Target Speed RPM in Electrical Cycle 400 Register FGTx[6:0] Speed Index Code 4 (0x04) … one step 200 … … one step 1 … 13,200 68 (0x44) … one step 400 … … one step 1 … 17,600 79 (0x4F) … one step 800 … … one step 1 … 24,000 87 (0x57) … one step 2,000 … … one step 1 … 40,000 95 (0x5F) Operation (100% or 0%) FGT: Target Speed Setting Target Speed [Electrical RPM] 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 0 16 32 48 64 80 96 Register Code [count] 112 128 Figure 17: Speed Register Contents vs. Electrical RPM www.onsemi.com 34 LV8907UW MRACS Address = 20h Standby Mode: Normal Mode: Read Only Read Only Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 OSAENB MSAENB This read-only register controls SPI access to the Master Registers and OTP Registers. Its contents are transferred from OTP Register ORACS at device startup. OSAENB=1: Write access denied. OSANEB: OTP Register access enable Controls write access to the Master registers. OSAENB=0: Write access permitted. OSAENB=1: Write access denied. MSANEB: Master Register access enable Controls write access to the OTP registers. OSAENB=0: Write access permitted. MRACK Address = 30h Standby Mode: Normal Mode: Read Only Read Only Bit 7 6 5 4 3 2 1 Bit 0 0 1 0 1 0 1 0 1 This read only register is used to check IC and SPI interface. 55h is read from this register in standby and normal mode, FFh during sleep mode. MRODL Address = 31h Bit 7 0 Standby Mode: Normal Mode: 6 0 5 4 3 2 1 Bit 0 0 MRODL[7:0] 0 0 0 0 0 Read/Write Read Only OTP download A write access of 00h to this register initiates a copy operation of OTP data to the Master Register. This register is blocked if OBSY is high. MRRST Address = 32h Standby Mode: Normal Mode: Bit 7 6 5 4 3 2 1 Bit 0 0 1 0 1 0 1 MRRST[7:0] 0 0 1 1 0 1 0 1 0 1 • This register is used to reset the watch dog timer or the error latch. • Read/Write Read/Write Reset Watchdog Timer Reset Error Latch Writing 00h to this register will reset the watch dog timer. Writing FFh will reset the protection latch. MRORB Address = 33h Standby Mode: Normal Mode: read/write read Only Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 ORBEN ORBLV This register modifies the OTP readout threshold. After programming the OTP registers should be verified by reading them with the readout thresholds set low and high to detect false zeros and ones. See “OTP Programming” on page 38. ORBEN: Selects the margin read mode. ORBEN = 0: Normal mode. ORBEN = 1: Margin read mode. ORBLV: Selects the OTP readout threshold. ORBLV = 0: Low level margin check ORBLV = 1: High level margin check www.onsemi.com 35 LV8907UW MRDIAG0 Address = 34h Standby Mode: Normal Mode: Read Only Read Only Bit 7 6 5 4 3 2 1 Bit 0 CPO THPO FSPO VGLLVPO CHPLVPO VSOVPO VSLVPO OCPO Registers MRDIAG0 and MRDIAG1 indicate the system errors and/or warnings. VGLLVPO: VGL Low voltage protection output The voltage at VGL has dropped below 5.5V(max). The drivers are disabled to protect against low gate enhancement. CPO: Locked rotor protection output No back EMF was detected during the entire open-loop startup time as programmed in CPTM on page 29. Either the rotor is blocked, or startup parameters are not correct. The drivers are disabled. CHPLVPO: CHP Low voltage protection output The voltage between VS and VCP has dropped below 5.5V(max). The drivers are disabled to protect against low gate enhancement. THPO: Thermal protection output The external temperature sensor input TH threshold was triggered. If the voltage at pin TH is lower than programmed in THTH on page 29 the drivers will shut down. Tie TH to V3RO to disable this function. VSOVPO: VS Over-voltage protection output The voltage at VS has exceeded 20V(min). The driver stage and the charge pump are disabled to protect against over-voltage at the charge-pump. FSPO: FET Short protection output The drain-source voltage threshold across one of the external power FETs has been exceeded during operation. The threshold voltage is programmed in register FSCDL. Errors are suppressed for a blanking time as programmed in register FSCDT. For the high-side FETs this voltage is measured between pin VS and the corresponding phase connection UOUT, VOUT, WOUT. For the low-side FETs it is measured between the phase connection and the pins SUL, SVL and SWL. Make sure to minimize potential voltage drops in the sense paths. VSLVPO: VS Low voltage protection output The voltage at VS has fallen below 5.1V(max). The driver stage is disabled to protect against internal threshold issues. VOCPO: Over-current protection output The voltage between current sense pins RFSENS and RF has exceeded 200mV for longer than the over-current limit mask time programmed in OCMASK in register MRCONF5 on page 27. The driver stage is disabled to protect against damage. MRDIAG1 Address = 35h Standby Mode: Normal Mode: Read Only Read Only Bit 7 6 5 4 3 2 1 Bit 0 PWMPO VCLVPO - SPCO STUPO WDTPO THSPO THWPO Registers MRDIAG0 and MRDIAG1 indicate the system errors and/or warnings. This flag indicates open-loop startup operation. No back EMF has been detected, yet. PWMPO: PWM input abnormal protection output WDTPO: Watch dog timer protection output The PWM input does not oscillate with the appropriate frequency or is steady high (100%) or low (0%). Depending on the settings in register MRCONF1 on page 25 the driver stage will turn off, or operate at a predefined duty cycle (emergency mode). The watchdog has timed out. This flag will be high if the watchdog was not re-set during the time defined by MRCONF9 on page 29. If the watchdog is enabled the driver stage will either be off or run in emergency mode with the settings defined by MRCONF11 on page 30. VCLVPO: VCC reduced voltage protection output Flag WDTPO is high even if the watchdog is disabled. VCC under-voltage error. Depending on the setting of MRCONF0 on page MRCONF0 VCC is either 5V(typ.) or 3.3V(typ.). Under-voltage is flagged if VCC falls below 4.2V(max.) or 2.7V(max.) respectively. THSPO: Junction temperature thermal protection output SPCO: The IC temperature is too high and the drivers are shut off. The over-temperature shutoff level is defined by MRCONF8 on page 28 to be either 150ºC(min.) or 175ºC(min.). Speed error out of the range SPCO = 0, when the absolute value of the speed error is 1 equal to or less than target × THWPO: Junction temperature thermal warning output 16 The IC temperature has exceeded the warning level. The over-temperature warning level is defined by MRCONF8 on page 28 to be either 125ºC(min.) or 150ºC(min.). SPCO = 1, when the absolute value of the speed error is 1 greater than target × 16 STUPO: Start-up status output www.onsemi.com 36 LV8907UW OTP Registers block programming of the OTP section by setting the OSANB bit in the ORACS Register of the OTP. The OTP Registers contain the default values of the system registers. These registers are always readable via SPI in either Standby or Normal modes. During device startup these default values are copied from the OTP bank (SPI addresses 40h to 60h) to the Master register bank (SPI addresses 00h to 20h). The OTP registers should only be programmed once during IC initialization, during normal operation only the Master Registers are accessed and modified. It is possible to ADDR[6:0 ] 40h 41h 42h 43h 44h 45h 47h 48h 49h 4Ah 4Bh 4Ch 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 60h _ _ _ _ _ _ Bank OTP Register 0d[0] 0d[1] 0d[2] 0d[3] 0d[4] 1d[0] 1d[2] 1d[3] 1d[4] 2d[0] 2d[1] 2d[2] 2d[3] 2d[4] 3d[0] 3d[1] 3d[2] 3d[3] 3d[4] 4d[0] 4d[1] 4d[2] 4d[3] 4d[4] _ _ _ _ _ _ ORCONF0 ORCONF1 ORCONF2 ORCONF3 ORCONF4 ORCONF5 ORCONF7 ORCONF8 ORCONF9 ORCONF10 ORCONF11 ORCONF12 ORSPCT0 ORSPCT1 ORSPCT2 ORSPCT3 ORSPCT4 ORSPCT5 ORSPCT6 ORSPCT7 ORSPCT8 ORSPCT9 ORSPCT10 ORACS _ _ _ _ _ _ For detailed information on the content of the OTP see the corresponding Master Register descriptions in the previous section. Master registers from 30h to 35h shown below are autonomous and have no equivalent position in the OTP as they report various internal data and status information. Function …corresponds to… WRITE protection SPI Status Register Initiates a bank write Watchdog Reset Margin read checks Diagnostic Flags Diagnostic Flags www.onsemi.com 37 Master Register ADDR[6:0] MRCONF0 MRCONF1 MRCONF2 MRCONF3 MRCONF4 MRCONF5 MRCONF7 MRCONF8 MRCONF9 MRCONF10 MRCONF11 MRCONF12 MRSPCT0 MRSPCT1 MRSPCT2 MRSPCT3 MRSPCT4 MRSPCT5 MRSPCT6 MRSPCT7 MRSPCT8 MRSPCT9 MRSPCT10 MRACS MRACK MRODL MRRST MRORB MRDIAG0 MRDIAG1 00h 01h 02h 03h 04h 05h 07h 08h 09h 0Ah 0Bh 0Ch 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 20h 30h 31h 32h 33h 34h 35h LV8907UW START OTP data download The OTP register data is typically transferred into the main registers at device startup (From sleep to standby transition). This operation takes up to 110us. A high OBSY flag in the first returned byte during a SPI transaction indicates this. Set LV8907 standby Apply VS > 14V Write Data Set mode to L side read check Figure 18: OTP data download timing at startup An OTP download can also actively be initiated by writing 00h to register MRODL. This command requires monitoring the OBSY flag. Don't perform specific register access (MRCONF, MRSPCT, ORCONF, ORSPCT, ORACS) until the OBSY flag is cleared. Verify Set mode to H side read check Verify Set mode to Normal Figure 19: OTP data download timing after an MRODL command OTP Programming Overall Verify Figure 20 shows overall of the OTP memory write and verify flow. It consists of preparation, write and three times of data integrity verification. END Figure 20 OTP Memory Write and Verify Flow OTP Programming The OTP registers can be programmed in Standby mode only while the write lock bit OSAENB is set 0. And, the supply voltage at pin VS must be more than 14V. The actual write operation to the OTP memory will be done, when the state change from 0 to 1 is commanded. Once the bit state is changed to 1, it cannot be change back to 0. The number of writing is limited to one per bit. The OTP memory consists of five memory banks. The bank contains five register bytes. The bank is filled by five SPI write transactions. When the last address register in each bank is received, the busy-flag OBSY will be set and those five bytes will be programmed permanently into the corresponding OTP bank. The OBSY flag will be reset at the end of the write cycle. OBSY is in GSDAT register. To get GSDAT, SPI accesses to the register MRACK is recommended. MRACK doesn’t interfere with the programming operation. MRCONF, MRSPCT, ORCONF, ORSPCT, ORACS registers cannot be accessed during an OTP write cycle. Figure 21: OTP programming timing www.onsemi.com 38 LV8907UW OTP data integrity verification The programming takes 25ms maximum. To simplify operation, a waiting for 25ms plus margin can be applicable instead of a polling of the flag OBSY. (Figure 22) In order to verify that the OTP programming operation was successful. It is strongly recommended to do an OTP margin check: To do this, the OTP registers are downloaded into the main register bank with minimum and maximum readout thresholds. This OTP download is forced by writing 00h to register MRODL. The readout threshold is set in register MRORB. OTP Margin read check sequence after programmed: 1. Set OTP readout threshold “low” by setting ORBEN=1 and ORBLV=0 in register MRORB 2. Execute OTP download command by writing 00h to MRODL. 3. Verify that the main register contents are consistent with the programmed OTP data. 4. Set OTP readout threshold “high” by setting ORBEN=1 and ORBLV=1 in register MRORB 5. Execute OTP download command by writing 00h to MRODL. 6. Verify that the main register contents are consistent with the programmed OTP data. 7. Return OTP threshold to normal by setting ORBEN=0 and ORBLV=0. 8. Execute OTP download command. 9. Verify that the main register contents are consistent with the programmed OTP data. START WRITE DATA Write data to address 40h, 41h, 42h, 43h, 44h Wait for 25ms or more Write data to address 45h, 46h, 47h, 48h, 49h Wait for 25ms or more Write data to address 4Ah, 4Bh, 4Ch, 50h, 51h Wait for 25ms or more Write data to address 52h, 53h, 54h, 55h, 56h Locking OTP register contents MSAENB bit and OSAENB bit of ORACS register are used in order to prevent write-access of main- and OTP registers respectively. CAUTION: Inadvertent writing of these bits will permanently lock the corresponding register blocks from any further write access. Should only be set at end of development cycles. Wait for 25ms or more Write data to address 57h, 58h, 59h, 5Ah, 60h Wait for 25ms or more END Figure 22 OTP Memory Write Operation ORACS Address = 60h Standby Mode: Normal Mode: Read/Write Read Only Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 OSAENB MSAENB This register is used in order to permanently prevent write access to the OTP and/or main registers. This register data is transferred into MRACS register. OSAENB D[1]: Controls write access to the OTP registers. OSAENB=0: Write access permitted. OSAENB=1: Write access denied. MSAENBD[0]: This bit is used in order to prevent write access to the main registers. MSAENB=0: Write access permitted. MSAENB=1: Write access denied. www.onsemi.com 39 LV8907UW PACKAGE DIMENSIONS SPQFP48 7x7 / SQFP48K CASE 131AN ISSUE A ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. 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