Download eWLB (embedded Wafer Level BGA) Technology

“eWLB (embedded Wafer Level BGA) Technology:
Dawn of a New Age of Thin and 3D Package
Technology”
by
Seung Wook Yoon, Yaojian Lin, Chow Seng Guan,
and Pandi C. Marimuthu
STATS ChipPAC LTD
Singapore
[email protected]
Originally published in the International Wafer Level Packaging
Conference Proceedings,” San Jose, California, November 5 – 7, 2011.
Copyright © 2011. The material is posted here by permission of the SMTA
- The Surface Mount Technology Association.
By choosing to view this document, you agree to all provisions of the
copyright laws protecting it.
EWLB (EMBEDDED WAFER LEVEL BGA) TECHNOLOGY: DAWN OF A
NEW AGE OF THIN AND 3D PACKAGE TECHNOLOGY
Seung Wook Yoon, Yaojian Lin, Chow Seng Guan,
and Pandi C. Marimuthu
STATS ChipPAC LTD
Singapore
[email protected]
ABSTRACT
The drive for small form factor and foot print area
packages is being fueled by consumer and hand held
electronic applications that today constitute greater than
50% of semiconductor revenue. Small form factor, foot
print areas and cost effective technology are mandatory
characteristics for packages in hand held electronic
applications. Demand for Wafer Level Packages (WLP) is
being driven by the need to shrink package size and
height, simplify the supply chain and provide a lower
overall cost by using the infrastructure of a batch process.
eWLB (embedded Wafer Level Ball Grid Array) has
been introduced into production to allow for higher ball
count WLP, by extending the package size beyond the
area of the chip. There is also great opportunity related to
a 3D variation of eWLB which would allow for mounting
of components or another package on the top surface with
thinner profile. 3D or PoP eWLB is envisioned as an
exciting technology which will open up the floodgates for
system level integration utilizing very thin stacked eWLB
packages as building blocks in mobile applications.
This paper reports developments that are aimed to extend
the low profile application space of eWLB technology.
eWLB packaging is demonstrated to be thin and 3D
packaging solution for mobile and portable electronics.
Thinning process details and mechanical characterization
are to be discussed with board level reliability results of
various package sizes in comparison to standard eWLB.
In addition, warpage behavior and package strength are to
be presented. Innovative package structures that provide
dual advantages of both form factor reduction and
enhanced package reliability are reported. Successful
reliability characterization results on thin and 3D eWLB
package configurations are reported that demonstrate
eWLB as an enabling technology for low profile, 3D, fine
pitch, high density advanced silicon integration.
I. INTRODUCTION
WLP applications are expanding into new areas and are
segmenting based on I/O count and device. The
foundation of passive, discrete, RF and memory device is
expanding to logic ICs and MEMS. The WLP segment
has matured over the past decade, with numerous sources
delivering high-volume applications across multiple wafer
diameters and expanding into various end-market
products. With infrastructure and high volumes in place,
a major focus area is cost reduction.
One of the most well known examples of a FO-WLP
structure is eWLB technology [1]. This technology uses a
combination of front- and back-end manufacturing
techniques with parallel processing of all the chips on a
wafer, which can greatly reduce manufacturing costs. Its
benefits include a smaller package footprint compared to
conventional leadframe or laminate packages, medium to
high I/O count, maximum connection density, as well as
desirable electrical and thermal performance. It also offers
a high-performance, power-efficient solution for the
wireless market[2]. Furthermore, next generation 3D
eWLB technology enables 3D IC and 3D SiP (System-inPackage) with vertical interconnection. 3D eWLB can be
implemented with through silicon via (TSV) applications
as well as IPD, MLCC or discrete component embedding.
II. eWLB TECHNOLOGY
eWLB technology is addressing a wide range of factors.
At one end of the spectrum is the packaging cost along
with testing costs. Alongside, there are physical
constraints such as its footprint and height. Other
parameters that were considered during the development
phase included I/O density, a particular challenge for
small chips with a high pin count; the need to
accommodate SiP approaches, thermal issues related to
power consumption and the device's electrical
performance (including electrical parasitic and operating
frequency) [3].
The obvious solution to the challenges was some form of
WLP. But two choices presented themselves: Fan-out or
Fan-in. FO-WLP is an interconnection system processed
directly on the wafer and compatible with motherboard
technology pitch requirements. It combines conventional
front- and back-end manufacturing techniques, with
parallel processing of all chips. There are three stages in
the process. Additional fab steps create an interconnection
system on each die, with a footprint smaller than the die.
Solder balls are then applied and parallel testing is
performed on the wafer. Finally, wafers are sawn into
individual units, which are used directly on the
motherboard without the need for interposers or underfill.
(a)
dielectric structures resulting in flip chip becoming
narrower in terms of packaging process margin,. In
addition, there is a big trend in being environmentally
friendly, driving lead free and halogen free, or green,
material sets. With ultra low-k and interconnects pitch
becoming smaller and smaller and with the shift to lead
free materials, the technical limitations faced by the
packaging industry are becoming more challenging.
eWLB technology provides a window for packaging next
generation devices in a generic, lead-free/halogen free,
green packaging scheme.
Table 1. Advantage of eWLB packaging.
(b)
Figure 1. (a) eWLB wafer after packaging with reconstitution,
RDL and backend processes and (b) schematics of different
eWLB structures.
Figure 2. SEM micrographs of cross-section of eWLB.
(total package body thickness 475um)
Advantage of eWLB Technology
The current BGA package technology is limited by the
organic substrate capability. Moving to eWLB helps
overcome such limitations and also simplifies the supply
chain. Building the substrate on the package itself, allows
for higher integration and routing density in less metal
layers. eWLB is a next generation platform that will
support future integration, particularly for wireless
devices and this packaging technology has a number of
important features. Transition to eWLB packaging
technology enables a significant reduction in recurring
costs by eliminating the need for expensive substrates.
The advantage of eWLB packaging can be summarized in
Table 1. BGA packaging also faces a challenge with
technology nodes beyond 65nm as the device performance
density drives the need for flip chip. But advanced flip
chip nodes drive fine pitch combined with weaker low-k
1.The smallest and thinnest package other than fan-in
WLCSP
2.Excellent electrical and thermal performance
-.Great for high frequency application
-.Excellent for RF and mixed signal due to low parasitics
compared to any laminate-based packages
-.The lowest thermal resistance
-.High density routing is easily implemented in RDL
3.No ELK damage issues for advanced Si nodes devices
4.Proven low cost path using a batch process & simple
supply chain
5.Path to the flexible 3D packages – any array patterns on
the top
6.Scalable technology to a larger panel production – Lower
cost
III. Thin eWLB Packaging
For mobile and handheld applications, portability is a
critical factor for product selection. The thinner package
can provide better board level reliability as well as lighter
and thinner profile in system level. Using advanced
thinning technologies, eWLB was thinned down to less
than 250m thickness as shown in Figure 3. The critical
technical challenges were handling the thin wafer and
grinding and removing of Si/epoxy material together
using the same process steps. There was found significant
increase in TCoB (Temperature Cycle on Board)
reliability performance with thinner eWLB. Drop
reliability also improved significantly.
Figure 3. Thin eWLB after eWLB packaging process.
boundary conditions are imposed on two symmetry planes
of the assembly model and a vertical displacement at the
bottom of the board is further constrained in order to
prevent the rigid body motion during FE analysis. For a
light weight package, it is found that collapsed solder
bump shape after reflow can be reasonably estimated
using truncated sphere theory as reported in [4].
Figure 4. Comparison of package body thickness
between standard and thin eWLB.
Since the eWLB package and board will experience
bending deformations during temperature cycling, a 3D
hexahedral element with reduced integration (C3D8R) is
used to overcome the shear locking phenomenon in fully
integrated element types, e.g. 8-node brick element.
Figure 5. SEM micrographs of cross-section of thin
eWLB. (total package body thickness 250um)
Package Level Reliability Results
Table 2 shows the package level reliability result of
each next generation 3D eWLB packages. They passed
JEDEC (Joint Electron Device Engineering Council)
standard package reliability test such as MSL (Moisture
Sensitivity Level) 1 with Pb-free solder conditions. Test
vehicles have 8x8mm Package with 5x5mm daisychain
die and 0.5mm pitch. Total ball I/O is 192 and lead-free
solder ball is used. All next generation eWLB packages
successfully passed all industry standard package level
reliability with ball shear test and OS(open-short) test.
The distribution of creep strain energy density at the end
of third cycle is shown in Figure 7 for an array of solder
bumps. It was found that the solder with the maximum
volume-averaged creep strain energy density over the
critical solder layer is located at the top interface of corner
solder bump, suggesting the predicted failure site of the
critical solder joint. Table 2 shows the DOE simulation
works of eWLB with package thickness and PCB CTE. It
also shows clearly TCoB performance was improved with
thinner packaging solution.
Figure 6. Quarter symmetry finite element model
of eWLB package assembly.
Table 2. Package Level Reliability Results of thin eWLB
packages.
Condition
MSL1
JEDEC-J-STD-020D
MSL1, 260C
Reflow (3x)
Temperature Cycling
-40C to 125C
(TC) after Precon
JESD22-A104
HAST (w/o bias) after
130C / 85% RH
Precon
JESD22-A118
High Temperature
150C
Storage (HTS)
JESD22-A103
BST after Multiple
260C Reflow
Reflow
* Tested by ball shear test and O/S test
Status
-
Pass
1000x
Pass
96hrs
Pass
1000h
Pass
Figure 7. A creep strain energy density plot of solder
bumps of eWLB packaging.
Table 3. Summary of eWLB parametric studies.
20x
Pass
Finite Element Modeling
Three dimension (3D) finite element models are
constructed for eWLB on board assemblies using
commercial available finite element analysis software,
ABAQUS. Finite element models are initially constructed
to correlate the chosen damage parameters, i.e. equivalent
creep strain and creep strain energy density per stable
cycle, with numbers of cycles-to-failure of solder joints
subjected to temperature cycling on board tests. Due to
the symmetric nature of the package, a quarter-symmetry
model is constructed as shown in Figure 6. Two symmetry
DOE
1
3
5
7
PKG Body Thickness (mm)
0.475
0.25
0.475
0.25
PCB CTE (ppm/k)
16.6
16.6
15.8
15.8
Characteristic Life
Time (cycles)
789
925
911
1058
Board Level Reliability Results
For drop reliability, thin eWLB packages show good
drop reliability as reported in 1st gen eWLB packages. For
thin eWLB packages, they passed industry standard drop
reliability tests. Table 4 shows comparison of standard
and thin eWLB TCoB performance in terms of first failure
and characteristic life time of various package types. Fig.
8 shows Weibull plot of 5x5mm eWLB TCoB reliability
and it shows improvement of TCoB performance,
60~80% compared to standard eWLB. Fig. 9 shows
Weibull plot of drop reliability of standard and thin eWLB
of 5x5mm eWLB. It also shows significant improvement
in drop reliability of more than 60% in characteristic life
time.
Table 4. Comparison of TCoB reliability test results with
standard and thin eWLB of various packages.
control, but warpage at solder reflow temperatures (up to
260C for lead-free solder) should also be considered since
open solder joints occur during solder solidification. As a
result, warpage control at both temperature extremes is
critical for 3D PoP stacking.
Themo-Moire technology used for measure package warpage
with temperature profile. As shown in picture, standard
eWLB showed almost flat during temperature profile and
very stable warpage behaviour of 10um warpage. With
thinned eWLB, it has increased warpage but still in 20um
(absolute) warpage value along with reflow temperature
profile as shown in Fig. 10.
Figure 10. Warpage behavior of thin eWLB compared to
standard eWLB.
Figure 8. Weibull Plot of TCoB reliability of 5x5mm
standard (0.7mm) and thin (0.5mm) eWLB Packages.(40/125C, 1cycle/hr)
Figure 9. Weibull Plot of drop reliability of 5x5mm
standard and thin eWLB Packages.(JEDEC standards)
Warpage Behavior with Temperature Profile
Among the 3D technologies, Package-on-Package (PoP)
is increasingly becoming mainstream due to its flexibility of
combination and sourcing. The top package to be stacked
using solder ball interconnects. For successful package on
package stacking with high assembly yield, warpage of both
the top and the bottom package are critical. If the warpage is
too large, open solder joints may occur between the bottom
package and motherboard, or between the bottom package
and top package. Not only is the warpage at room
temperature a concern for co-planarity measurement as a
IV. Thin 3D eWLB packaging
There is 3D eWLB approach with vertical
interconnection; both sides of the reconstituted wafer will
have isolation and metal layers, connected using
conductive vias. It enables PoP (Package-on-Package), 3D
SiP or 3D micro module as shown in Fig.10. Key to the
miniaturization of 3D SiP is the integration of the
packaging steps as a functional part of the die and system
solution. The PBGA replaced the lead frame by a printed
circuit board (PCB) substrate, to which the die was
electrically connected by wire bonding or flip chip
technology, before covering with molding compound.
eWLB takes the next step, eliminating the PCB, as well as
the need to use wire-bonding or flip-chip bumps to
establish electrical contacts. Without a PCB, the package
is inherently thinner, without thinning the die when lower
profiles are required.
As shown in Fig. 11, PoP and SOW (System-on-Wafer)
takes this integration a step further, placing one package
on top of another for greater integration complexity and
interconnect density. eWLB makes it a very flexible
choice. eWLB technology also offers procurement
flexibility, lower cost of ownership, better total system
and solution costs and faster time to market. Each step
along the path from SiP to PoP (Package on package) to
eWLB represents improvements in these two areas. Each
of these packages fit unique niches. For example, if size is
most important, then stacked die will yield smaller
packages. Moving into PoP increases board space, but
improves cost structure. eWLB, with its potential to
dramatically improve cost effectiveness and reduce entire
systems to the size of a postage stamp, represents the best
of both worlds. SiP, as the name implies, is a technology
that allows the placement of several integrated circuits in
one package, providing a complete set of device
electronics in a small area. This technique saves board
space by integrating devices that were once spread farther
apart on the circuit board.
(a)
eWLB technology is an enhancement to standard
WLPs, allowing the next generation of a WLP
platform due to its fan-out capability. The benefits of
standard
fan-in
WLPs
such
as
low
packaging/assembly cost, minimum dimensions and
height as well as excellent electrical and thermal
performance are true for eWLB as well. The ability to
integrate passives like inductors, resistors and
capacitors
(b)
into
the
various
thin
film
layers,
active/passive devices into the mold compound and
3D vertical interconnection opens additional design
possibilities for new Systems-in-Package (SiP) and
Figure 11. Applications of double-side eWLB packaging;
(a) Package-on-package (PoP) and (b) System-on-Wafer
(SOW).
Thin 3D eWLB has lots of good merits or advantages as
shown in Fig. 12,
i) Lower profile packaging – embedded and thinner,
< 0.5mm package height
ii) Higher assembly/SMT yield - smaller warpage
iii) Improved flipchip solder joint reliability (eWLB
CTE is much less than organic substrate)
Fig.13 shows the package height difference between thin
and standard thickness 3D eWLB packages.
Figure 12. Advantage of double-side 3D eWLB
technology.
Figure 13. Comparison of package height between thin
and standard thickness 3D eWLB.
CONCLUSION
Advanced packaging plays a crucial role in driving
products with increased performance, low power, lower
cost and smaller form factor. There are challenges
associated in the application of cost effective materials
and processes for various reliability requirements. The
industry requires innovation in packaging technology and
manufacturing to meet current demands and the ability to
operate equipment in high volume with large throughput.
3D stacked packaging. Moreover, thin eWLB and
3D eWLB technology provides more value-add in
performance and promises to be a new packaging
platform that can expand its application range to various
types of mobile/portable devices as well as 3D TSV
integration for true 3D SiP systems.
As the world demand for portable and mobile electronics
like as smartphone and tablet PC has accelerated, the need
to make semiconductors smaller, faster, lighter and
cheaper has never been greater. As witnessed by the
dramatic evolution of cellular phones, product
differentiation today is driven by ever-expanding
functionality, feature sets, multi-functionality and faster
communications. At the same time, consumers have made
clear their desires for feature-rich products in compact
form factors to enable maximum portability. Thin and 3D
eWLB technology is successfully enabling semiconductor
manufacturers to provide the smallest possible, highestperforming semiconductors.
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Grid Array (eWLB),” Proceedings of 8th Electronic
Packaging Technology Conference, 10-12 Dec 2009,
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[2] Graham pitcher, “Good things in small packages,”
Newelectronics, 23 June 2009, p18-19 ( 2009)
[3] M. Brunnbauer, et al., “Embedded Wafer Level
Ball Grid Array (eWLB),” Proceedings of 8th Electronic
Packaging Technology Conference, 10-12 Dec 2009,
Singapore (2006)
[3] Seung Wook YOON, Meenakshi PADMANATHAN,
Andreas BAHR, Xavier BARATON and Flynn
CARSON, “3D eWLB (embedded wafer level BGA)
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[4] K.N. Chiang and C.A. Yuan, “An Overview of Solder
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