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A 0.45-V Input On-Chip Gate Boosted (OGB) Buck Converter in 40-nm CMOS with More Than 90% Efficiency in Load Range from 2μW to 50μW Xin Zhang1, Po-Hung Chen1, Yoshikatsu Ryu2, Koichi Ishida1, Yasuyuki Okuma2, Kazunori Watanabe2, Takayasu Sakurai1, and Makoto Takamiya1 1 University of Tokyo, Tokyo, Japan, 2Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan Abstract A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed. Introduction Adaptive power supply voltage (VDD) control is important for near-threshold logic circuits to achieve an energy efficient operation against PVT variations, because low VDD circuits are very sensitive to the variations. In [1], a low dropout regulator (LDO) is used for the adaptive VDD control. The LDO is, however, not suitable for the adaptive VDD control, because the efficiency is limited to less than VOUT/VIN, where VOUT is an output voltage and VIN is an input voltage. To improve the efficiency, a 0.45-V VIN, 0.4-V VOUT buck converter with 2~50-μW output power (POUT) range is developed in this paper. The efficiency of the buck converter with such low VIN and POUT is, however, normally low, because (1) the loss in power transistors increases due to low VIN and (2) the controller power dominates the total power due to low POUT. Fig. 1 shows a calculated dependence of efficiency on quiescent power (= controller power). As the quiescent power increases, the efficiency decreases. For example, to achieve more than 90% efficiency at POUT of 2μW, the quiescent power should be less than 222nW. In order to achieve a high efficiency buck converter, this paper proposes (1) a gate boost by fully integrated switched-capacitor (SC) DC-DC converters to overdrive the power transistors in buck converter, (2) a low power clock gated 0.45-V digital PWM controller to improve the efficiency at low POUT, and (3) a linear delay trimming by a novel logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability. On-chip Gate Boosted (OGB) Buck Converter Fig. 2 shows a block diagram of the proposed on-chip gate boosted (OGB) buck converter. Without OGB, driving voltages of the power transistors are low (=VIN), thus the loss of the power transistors increases and the efficiency decreases. In order to reduce the on-resistance of the power transistors, a fully integrated 2VIN (=double voltage) SC DC-DC converter for the nMOS power transistor (MN) and a minus VIN SC DC-DC converter for the pMOS power transistor (MP) are developed to boost the supply voltages for the gate drivers. The PWM signal (CK_PWM) is boosted to “-VIN to VIN” and “0V to 2VIN”, for MP and MN, respectively. Fig. 3 shows a circuit schematic of a digital PWM controller and a clock gating controller. Instead of a conventional analog feedback control, a delay-line based digital PWM controller is newly developed for 0.45-V operation. A new clock gating technique is applied to shift registers (SR) in the PWM controller for power saving. Specifically, when VOUT is higher than the high reference voltage (VREF(H)) or lower than the low reference voltage (VREF(L)), the clock signal (CK) is given to SR; when VOUT is between VREF(H) and VREF(L), CK divided by 16 is given to SR, thereby reducing the controller power by 26%. Fig. 4 shows a schematic of a fully integrated 2VIN SC DC-DC converter [2] employed in the proposed OGB buck converter. 978-1-4673-0849-6/12/$31.00 ©2012 IEEE Delay Line Trimming by LSV In the digital PWM controller in Fig. 3, a delay-line without feedback control is used to minimize the controller power. Large die-to-die delay variations of the delay line at low VIN, however, might fail the PWM operation. To compensate for the die-to-die process variations, a delay trimming by a charge injection is newly proposed, while the trimming to reduce a minimum operating voltage of an oscillator is previously proposed in [3]. Fig. 5 shows a schematic of the trimmed delay line. During the stress for the charge injection, VDD is set to 1.1V. By applying a high n-well voltage as a stress voltage (Vstress), the absolute value of the threshold voltage of pMOS is raised to increase the delay. Fig. 6 shows a conventional linear stress voltage scheme and the proposed LSV scheme. Fig. 7 shows a measured stress time dependence of the delay of the trimmed delay lines. The conventional linear stress voltage scheme exponentially increases the delay, which means a poor controllability. In contrast, the proposed LSV linearly increases the delay, which means a good controllability. Fig. 8 shows a measured stress time dependence of the delay of the trimmed delay line and the retention characteristics for 8 dies. The target delay is set to five times of the initial delay to show the controllability of proposed LSV scheme. The linear delay trimming by LSV and the compensation of the die-to-die delay variations are successfully demonstrated. No significant retention degradation is observed. Experimental Results A die photo of the buck converter fabricated with a 40-nm CMOS is shown in Fig. 9. Table I shows a performance summary. The 140-nW quiescent power is less than the target 222nW in Fig. 1. Fig. 10 (a) shows measured waveforms of load regulation. Overshoot of 10mV and 8mV, and ripple voltage of 5mV are observed. Fig. 10 (b) shows a startup transition. At the beginning, when VOUT is lower than VREF(L), the SR is clocked by CK of 20kHz. When VOUT is between VREF(L) and VREF(H), the clock gating is activated thus the SR is clocked by (20/16)kHz, thereby reducing the power of the PWM controller. Fig. 11 shows the measured dependence of the efficiency on POUT. By using the proposed OGB, the efficiency is increased from 55% to 96% at POUT of 15μW. On the other hand, at POUT of 270nW, the efficiency is increased from 60% to 67% by the proposed clock gating of SR. At POUT range from 2μW to 50μW, the proposed buck converter achieves more than 90% efficiency (> ideal LDO efficiency=0.4V/ 0.45V=89%) with a peak value of 97% at 7μW. Fig. 12 shows the comparison with the published DC-DC converters [4-8]. The proposed buck converter achieved the highest efficiency to date with the output power less than 40μW. Moreover, the lowest input voltage is also achieved. Acknowledgment This work was carried out as a part of Extremely Low Power (ELP) project supported by METI and NEDO. References [1] K. Hirairi, et al., ISSCC, 2012, to be presented. [2] H. San, et al., Trans. IEEJ, vol. 120-C, pp. 1339-1345, 2000. [3] P. Chen, et al., ISSCC, pp. 216-217, 2011. [4] J. Kwong, et al., ISSCC, pp. 318-319, 2008. [5] Y. Okuma, et al., CICC, pp. 323-326, 2010. [6] Y. Ramadass, et al., ISSCC, pp. 64-65, 2007. [7] S. R. Sridhara, et al., Symp VLSI Circuits, pp. 15-16, 2010. [8] C. Hsieh, et al., Symp VLSI Circuits, pp. 242-243, 2011. 2012 Symposium on VLSI Circuits Digest of Technical Papers 194 W 1m 80 P OU μW =2 T 60 40 20 90% W 0μ 10 μW 10 Efficiency (%) 100 0V On-chip gate boost (OGB) 222nW for 90% efficiency 0 VIN 10nW 100nW 1μW 10μW 100μW 1mW Quiescent power (nW) VIN Linear delay trimming by LSV T Delay0 CK (20kHz) CK_PWM Digital PWM controller Delay1 Delay2 Level shifter -VIN SC DC-DC 2VIN SC DC-DC VIN VIN=0.45V MP VOUT=0.4V -VIN 2VIN Level shifter MN CK (20kHz) Delay31 OUT_VREF Digital PWM controller VIN 1 1 0 Q0 0 Q1 0 Q2 VREF=0.4V OUT_VREF(H) 0 Clock gating controller Q31 VREF(H)=VREF+ΔV OUT_VREF(L) OUT_VREF Bi-directional shift register (SR) VREF(L)=VREF-ΔV CK_SR OUT_VREF(H) OUT_VREF(L) Sel 1 16 IOUT Load Fig. 1. Calculated dependence of efficiency on quiescent power. CK_PWM 2VIN VIN 0V VIN 0V -VIN VIN Fig. 2. Block diagram of proposed buck converter with on-chip gate boost and digital PWM controller. Clock gating controller VIN CK CK 2.5pF 2.5pF CK CK CK Vn-well=Vstress CK VOUT=2VIN =0.9V VIN=0.45V VDD=1.1V 10pF VIN Out 10pF CK (20MHz) CK 66 20 Conventional linear stress voltage scheme 13 Conventional linear stress voltage scheme 15 12 11 10 10 Proposed logarithmic stress voltage (LSV) scheme Vstress=1.67×log10N+9.5 (V) 9 8 0 4 8 12 16 20 Stress time (s) Proposed LSV scheme 5 0 24 0 4 8 12 16 20 Stress time (s) 24 Fig. 7. Measured delay vs. stress time of conventional linear stress voltage scheme and proposed LSV scheme. Fig. 6. Conventional linear stress voltage scheme and proposed logarithmic stress voltage (LSV) scheme. Fig. 5. Circuit schematic of trimmed delay line with charge injection. Delays of 8 dies are trimmed to target value 50ms 55 IOUT 0.45V VIN 5μA 10μA 44 s ur ho rs 72 hou rs 48 ou h 24 s ur ho s 8 ur ho s ur ho 33 22 Linear delay trimming is achieved by LSV. 11 VOUT=0.4V 8mV 8 12 16 20 24 Total stress time (s) 104 105 500μs 106 Time after stress (s) (a) Fig. 8. Measured delay trimming by proposed LSV and retention characteristics for 8 dies. (b) Fig. 10. Measured waveforms. (a) Load regulation. (b) Start up transition. 1050μm 100 450μm With gate boost & clock gating (proposed) PWM controller Power transistors On-chip SC DC-DC 100 VIN=0.45V VOUT=0.4V Fig. 9. Chip micrograph. TABLE I Performance summary Technology 40-nm CMOS Input voltage 0.45V Output voltage 0.34V~0.44V Output power 270nW~165μW Output ripple <5mV Max. efficiency 97% at 7μW Quiescent power 140nW at IOUT=0 Active area 0.043 mm2 978-1-4673-0849-6/12/$31.00 ©2012 IEEE Efficiency (%) (%) Efficiency 90 80 With clock gating & w/o gate boost 60 50 [6] 80 [7] 70 100nW With gate boost & w/o clock gating Clock gating of SR 1μW 1 1μW 10μW 100μW Output power On-chip gate boost Reference Type 40 100nW 0.1 [5] [4] 60 50 70 [8] This work 90 Efficiency (%) 4 0.45V VOUT 00 0 20/16kHz VREF(H) VREF VREF(L) 5mV 10mV 0V 20kHz CK_ SR 5 2 Delay of trimmed delay lines (a. u.) Fig. 4. Circuit schematic of 2VIN (=double voltage) switched-capacitor (SC) DC-DC converter. 14 Delay of trimmed delay lines (a. u.) VIN Stress voltage (Vstress) (V) Fig. 3. Circuit schematic of digital PWM controller and clock gating controller. 10μW 100μW 10 100 Output power power 1mW 1000 Fig. 11. Measured dependence of efficiency on output power with and without gate boost and clock gating of shift register. [4] ISSCC 2008 [5] [6] [7] CICC ISSCC VLSI 2010 2007 2010 SwitchedLDO Buck capacitor Buck [8] This VLSI work 2011 Buck Buck CMOS 65nm 65nm 65nm 130nm 250nm 40nm Input voltage (V) 1.2 0.5 1.2 1.8 1.2 0.45 Output voltage (V) 0.5 0.45 0.5 0.575 1.0 0.4 Fig. 12. Comparison with published low voltage and low output power DC-DC converters. 2012 Symposium on VLSI Circuits Digest of Technical Papers 195