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Body-Bias Scaling for GLOBALFOUNDRIES 22FDx Technology New Dimension to Explore the Design Ramya Srinivasan Tamer Ragheb GLOBALFOUNDRIES March 30-31, 2016 SNUG Silicon Valley SNUG 2016 1 Agenda Introducing 22FDX technology and platform Body-Biasing: A New Dimension in Design Closure Why we need Body-Bias Interpolation PrimeTime solution for Body-Bias Interpolation Results: Accuracy vs Characterized libraries Conclusion SNUG 2016 2 Agenda Introducing 22FDX technology and platform Body-Biasing: A New Dimension in Design Closure Why we need Body-Bias Interpolation PrimeTime solution for Body-Bias Interpolation Results: Accuracy vs Characterized libraries Conclusion SNUG 2016 3 GLOBALFOUNDRIES 22FDX Technology Bulk versus FDSOI • What is 22FDX technology? – It is the new 22nm Fully Depleted Silicon-on-Insulator (FDSOI) technology from GLOBALFOUNDRIES • Delivers FinFET-like performance and powerefficiency at 28nm cost • Integrated RF for reduced system cost and back-gate feature to reduce RF power • Enables applications across mobile, IoT and RF markets SNUG 2016 Planar Bulk Transistor Planar FDSOI Transistor with “green” Insulator layer Effects of Body Biasing in Bulk Transistor and FDSOI Transistor 4 GLOBALFOUNDRIES 22FDx Technology Why 22FDx Technology? • Body-biasing Provides Greatest Design Flexibility -2V to +2V Body-Biasing – Enables Body Bias (BB) with minimal leakage impact – Forward body-bias (FBB) enables low voltage operation – Reverse body-bias (RBB) enables low leakage • • • • Improve within die or die-to-die uniformity Lower Leakage due to insulator layer FDSOI variability is smaller across die due to lower doping effort Dynamic body-biasing enables active tradeoff of performance vs. power – Software-controlled transistor body-biasing for flexible trade-off between performance and power – Post-silicon tuning/trimming SNUG 2016 5 Body-biasing Power/Performance Trade-off Leakage Power Maximum Performance Operating Mode Forward Body-bias (FBB) Reverse Body-bias (RBB) Minimum Leakage In Standby Mode Max Frequency SNUG 2016 6 GLOBALFOUNDRIES 22FDX Technology RBB versus FBB • Bias voltage is applied to P-well and N-well • Reverse Body Bias (RBB) – raising VT of device – nMOS neg. substrate voltage, pMOS pos. substrate voltage • Forward Body Bias (FBB) – lowering VT of device – nMOS pos. substrate voltage, pMOS neg. substrate voltage flipped well SNUG 2016 7 Agenda Introducing 22FDX technology and platform Body-Biasing: A New Dimension in Design Closure Why we need Body-Bias Interpolation PrimeTime solution for Body-Bias Interpolation Results: Accuracy vs Characterized libraries Conclusion SNUG 2016 8 What is Body-biasing? A New Dimension in Design Closure • Substrate biasing is a low power technique – For tuning performance and static power consumption of a CMOS device • Body-biasing applied through voltage variation on PWELL and NWELL terminal • Same implementation can be timed with different Bias voltages resulting in different performance results • Different Body-Biasing domains on one chip are enabling new design architectures and design styles • Due to the variation in Body Bias as a new variable, now the corners are PVTB (Process/Voltage/Temperature/Body Bias) PVT + BIAS PVTB Library Char + Lib char with POCV/LVF BB (Added variability corners) Bulk Flow SNUG 2016 New Step for 22FDX 9 Body-Biasing: A New Dimension in Design Closure • Requirements for static timing analysis on designs with well-biasing – Design using libraries with bias library cells • Cells with exposed bias PG pins – UPF contains specific bias related statements • Bias power domain • Bias supply nets • Forward or reverse biasing as applicable • Recommend asymmetric BB (available in INVECAS libraries): (0,0) Leakage (2,-2) Delay – Reduction of 4X leakage (Nwell is more leaky) – Performance is almost the same (more balanced) (0,-1) (1,-2) (1,-1) (2,-2) FBB SNUG 2016 4X reduction ~10% increase (0,0) (1,-1) (1,-2) (0,-1) FBB 10 Body-Biasing: A New Dimension in Design Closure • 22FDX Liberty Additions for Bias Pins (available in INVECAS libraries) voltage_map (VDD, XX); – Voltage map: Additional entries for bias voltages at N-Well and P-Well voltage_map (VNW_N, 1); voltage_map (VPW_P, -2); voltage_map (VSS, 0); – Power pins: Additional pin definitions for N-Well and P-Well pg_pin (VNW_N) { pg_type : nwell; physical_connection : device_layer; voltage_name : "VNW_N"; } pg_pin (VPW_P) { pg_type : pwell; physical_connection : device_layer; voltage_name : "VPW_P"; } SNUG 2016 11 Body-Biasing: A New Dimension in Design Closure • Static vs Dynamic Body-Biasing techniques: – Static: Need BB value optimization prior to implementation VDD VSS Design Chip VNW=0 VPW= -1 No Change in #of sign-off corners – Dynamic: Can use BB optimization on the spot after implementation VDD VSS Design Chip Sensor SNUG 2016 VNW=? VPW=? BB Gen Increase in #of sign-off corners Corner SS SS FF FF Library Corners VDD BIAS VDD-10% 0V/-1V VDD-10% 0V/-1V VDD+10% 0V/-1V VDD+10% 0V/-1V Library Corners Corner VDD BIAS SS VDD-10% 0V/0V 0V/-1V 1V/-2V SS VDD-10% 0V/0V 0V/-1V 1V/-2V FF VDD+10% 0V/0V 0V/-1V 1V/-2V FF VDD+10% 0V/0V 0V/-1V 1V/-2V Temp. -40C 125C -40C 125C Temp. -40C 125C -40C 125C 12 Body-Bias Flow Usage flow with scaling libraries • Scaling groups are created using the libraries at different bias-voltages. Lib1: 0.72v,-40c (0v,0v) Lib2: 0.72v,-40c (0v,-1v) Lib3: 0.72v,-40c (0v,-2v) Lib4: 0.72v,-40c (1v,0v) Lib5: 0.72v,-40c (1v,-1v) Lib6: 0.72v,-40c (1v,-2v) VPW VNW 0,0 1,0 0,-1 1,-1 0,-2 1,-2 • Libraries characterized at different voltages are grouped together to be used in the design for scaling • set link_path “* Lib1-0.72V-m40c-0-0.db“ • define_scaling_lib_groups “Lib1-0.72V-m40c-0-0.db Lib1-0.72V-m40c-0-M1.db Lib1-0.72V-m40c-0-M2.db Lib1-0.72V-m40c-1-0.db Lib1-0.72V-m40c-1-M1.db Lib1-0.72V-m40c-1-M2.db” SNUG 2016 13 Body-Bias Flow Usage flow with scaling libraries • Define the connectivity to the bias PG pins – set_voltage 0.72 -min 0.72 -object_list VDD – set_voltage 0 -min 0 -object_list VSS – set_voltage 0.5 -min 0.5 -object_list NET_BIAS_VNW – set_voltage -1.0 -min -1.0 -object_list NET_BIAS_VPW • STA Settings – waveform propagation enabled – SI analysis turned off – PBA Mode • Primetime version Read netlist and link design Scaling library groups and enable bias voltage scaling Load UPF (has bias PG info) Read SDC and set_voltage for bias pins Update timing and generate reports – K-2016.06 (Beta version) SNUG 2016 14 Body-Bias Scaling Validation • Bias voltage scaling is validated with spice accuracy correlation for uncoupled path delay VPW • Bias scaling validated for the 9 points (orange points) • Bias interpolation validated with different combinations of scaling libraries (blue points) • Blue points are pre-characterized points • VNW 0,0 1,0 0,-1 1,-1 0,-2 1,-2 For each body-bias value (orange points) STA and spice correlation was carried out with – All 6 libraries (all blue points) – 5 libraries – 4 libraries – 3 libraries SNUG 2016 15 Validation Methodology Primetime Simulation Link • Primetime Simulation Link – perform path-based uncoupled SPICE analysis – The SimLink commands supports the body bias voltage in SPICE deck generation • Synopsys FineSim - 2015.06-SP1-4 sim_setup_library sim_setup_simulator Select paths for correlation (PBA) Specify namemodels of the HSPICE Set up thethe SPICE for Perform path-based uncoupled simulator executable (FineSim), simulation by specifying the SPICE analysis on a specified path simulator options for comparisons library name, subcircuit directory segment and compares the between PrimeTime and the name, and header fileagainst name. the static simulation results Finesim. timing results. sim_validate_path Post process correlation results SNUG 2016 16 Testcase setup • • • • • • • • Testcase: falcon_neon (part of ARM Cortex-A9) Cell-count: 150K (std-cells) Setup Analysis with PBA mode Forward-Bias Mode Placement Utilization: 65% Library: 8T CNRX Metal Stack: 8M layers PNR MCMM Scenarios – TT.0P80V-0P0V-0P0V.25C_FuncCmax – TT.0P80V-0P0V-M1P0V.25C_FuncCmax – TT.0P80V-1P0V-M2P0V.25C_FuncCmax • Cell Types: wcl and wcs SNUG 2016 17 Implementation Details Place & Route with ICC TapCells • Based on Multi-Voltage aware Synopsys reference scripts - UPF and bias-specific scenario settings same as for synthesis - Floorplan includes : Additional physical cells to support Bias-Supply from external : Voltage-Areas for each Bias-Domain - Power Planning Includes Bias-Routes - Fill Insertion has to be :Bias-Domain aware / VT aware - Special NDR Rules on Bias-Nets (HV rules) - CNRX Placement Filler - To reduce the layout dependent effects Cell SNUG 2016 S S Abut D Abut D Abut Spacing 18 Implementation Details Place & Route with ICC: Floor/Power-Planning • Bias Tap-Cells – Supply N-Wells and P-Wells with Bias-Voltages from an external source – Are ideally placed in columns so minimize routing overhead due to additional Bias-Straps – Have to fulfill maximum distance rules between each other • Bias-Routes – Connect NW and PW separately from VDD and VSS mesh – BB mesh connection using UPF flow – Provide Bias-Voltages to Bias-Tap-Cells – Can be connected to a on-die Bias-Voltage generator SNUG 2016 NET_BIAS_2_VNW Metal3-Strap NET_BIAS_2_VPW Metal3-Strap 19 Results Bias Scaling correlation to SPICE with 3 libraries • To get the best accuracy using ONLY the 3 libraries provided by Invecas GLOBALFOUNDRIES recommends body bias scaling along the purple line VPW VNW 0,0 1,0 0,-1 1,-1 0.5V,-1.5V 0,-2 SNUG 2016 1,-2 20 Results Bias Scaling Correlation to SPICE with 4 libraries • For better accuracy, use the 4 corner libraries if available to cover the VNW/VPW scaling space VPW VNW 0,0 1,0 0,-1 1,-1 0.5V,-1.5V 0,-2 SNUG 2016 1,-2 21 Results Bias Scaling Correlation to SPICE with 6 libraries • For best accuracy (Synopsys Recommendation), use the 6 corners libraries if available to cover the VNW/VPW scaling space VPW VNW 0,0 1,0 0,-1 1,-1 0.5V,-1.5V 0,-2 SNUG 2016 1,-2 22 Results Bias Scaling correlation to SPICE with 3 libraries • To get the best accuracy using ONLY the 3 libraries provided by Invecas GLOBALFOUNDRIES recommends body bias scaling along the purple line VNW 0,0 1,0 VPW 0.0V,-0.5V SNUG 2016 0,-1 1,-1 0,-2 1,-2 23 Results Bias Scaling Correlation to SPICE with 4 libraries • For better accuracy, use the 4 corner libraries if available to cover the VNW/VPW scaling space VNW 0,0 1,0 VPW 0.0V,-0.5V SNUG 2016 0,-1 1,-1 0,-2 1,-2 24 Results Bias Scaling Correlation to SPICE with 6 libraries • For best accuracy (Synopsys Recommendation), use the 6 corners libraries if available to cover the VNW/VPW scaling space VNW 0,0 1,0 VPW 0.0V,-0.5V SNUG 2016 0,-1 1,-1 0,-2 1,-2 25 Results Summary VNW 0,0 1,0 VPW 0.0V,-0.5V 0,-1 1,-1 0.5V,-1.5V 0,-2 1,-2 • Bias scaling analysis with 6 libraries (Synopsys Recommendation) correlates very closely to SPICE with maximum percentage error close to 2.5% • Bias scaling with 4 libraries may be a reasonable compromise with acceptable percentage of error – depending on the customer max error target • Using the current Invecas offering (3 libraries), bias scaling is possible ONLY along the purple line if the amount of error is acceptable to customer • Bias scaling accuracy can be different from one library to another – Customer/IP vendor optimization of # of characterized library vs max error SNUG 2016 26 Conclusion • Body Bias Interpolation algorithm works accurately in PrimeTime: – Accurate correlation seen between Scaled STA runs with 6 libraries vs SPICE • Synopsys recommendation is to use 6 libraries for body-bias scaling in STA flows • GLOBALFOUNDRIES will deploy the Body-Bias scaling capability in Primetime in the Digital reference flows • Future work: GLOBALFOUNDRIES is working with Synopsys to include BB Interpolation in upstream tools “ICC/ICCII” SNUG 2016 27 Thank You SNUG 2016 28