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Transcript
MCML Implementation of Gbps
De-Multiplexer with Dynamic
Power Management
Osman Abdulkarim
21 February 2005
•
•
•
•
•
•
•
•
MCML
Advantages
Disadvantages
Topologies
Dynamic Power management
Multiplexers/De-multiplexers
Proposal statement
References
MOS Current Mode Logic
Differential pair acts as a switch that steers current based on input signal
Advantages of MCML
• SPEED
∆V = Vdd – IR, Typically 0.3 ~ 0.4 V
• NOISE IMMUNITY
Common Mode Rejection
• Differential Signal  No need for Inverters
Disadvantages
• Static Power Dissipation
P = Vdd . I
• Hard to design and optimize
Design Considerations include:
-Load Biasing and sizing
-Diff-pairs and current sink
-Minimum Swing for compete steering
Threshold fluctuation tolerant MCML
• Threshold variation is due
to fabrication process
variations. E.g. Gate
length, oxide thickness,
etc.
• Threshold fluctuation
tolerant MCML
Uses feedback to
compensate for threshold
variation.
∆VTHMAX: Maximum allowable threshold voltage variation
Dynamic CML
• Dynamic current source
using a capacitor.
During evaluation, capacitor acts
as a virtual AC ground
• Cross-connected PFETs
speed up the switching
operation.
• Cascading DyCML gates:
-Delayed Clock
-Self timed gates
Dynamic Power Management-AMCML
• Circuit conditions
power consumption
by changing current
based on frequency
of operation.
• Reduce power
dissipation to the
minimum required
for each operation
band.
De-Multiplexers
• De-Multiplexers
convert a serial bit
stream into a parallel
word format.
• Used in serial
communication
systems
• Can be modeled
using shift registers,
switches or D-Latches
2:1 DeMUX
Proposal Statement
• To design a CML Wide Band Gbps 2:1
Multiplexer using Feedback transistors
and an Adaptable current management.
• The results shall be compared to
Conventional CML, with focus on Power
dissipation and speed.
Time Table
• Feb, 16
Project Proposal
• Feb, 16 – Mar, 1
Research: Accumulate information on MCML, threshold voltage fluctuation
theory and its effect on MCL switching speed. Define the problem, the
performance requirements, the testing methodology and performance
indicators measurement.
• Mar, 1 – Mar, 25
Circuit design and simulation
• Mar, 25 – April 1
Project Presentation
• April 1 – April 25
Simulation results recording and analysis. Conclusions and suggestions.
Comprehensive report.
References
[1] 0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode
logic with tolerance to threshold voltage fluctuation
Tanabe, A.; Umetani, M.; Fujiwara, I.; Ogura, T.; Kataoka, K.; Okihara, M.;
Sakuraba,H.;Endoh,T.;Masuoka,F.;Solid-State Circuits, IEEE Journal of ,Volume: 36
, Issue:6, June 001
Pages:988 - 996
[2] Dynamic current mode logic (DyCML): a new low-power high-performance
logic style
Allam, M.W.; Elmasry, M.I.;
Solid-State Circuits, IEEE Journal of ,Volume: 36 , Issue: 3 , March 2001
Pages:550 - 558
[3] Adaptable MOS Current mode logic for use in a multiband RF prescalar
Mark, M.P; Olszweski, D.J; Abdelhalim, K.; MacEachern, L.
Circuits and Systems, 2004. ISCAS’04. Proceedings of the 2004 International
Symposium on, Vol 4, Iss., 23-26 May 2004
Pages: IV-329-32 Vol 4
[4] 10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer
Stout, C.L.; Doernberg, J.;
Solid-State Circuits, IEEE Journal of ,Volume: 28 , Issue: 3 , March 1993
Pages:339 - 343