* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download Cmos Scaling Into The Nanometer Regime
Survey
Document related concepts
Power engineering wikipedia , lookup
History of electric power transmission wikipedia , lookup
Power over Ethernet wikipedia , lookup
Resistive opto-isolator wikipedia , lookup
Switched-mode power supply wikipedia , lookup
Stray voltage wikipedia , lookup
Rectiverter wikipedia , lookup
Power electronics wikipedia , lookup
Voltage optimisation wikipedia , lookup
Surge protector wikipedia , lookup
Alternating current wikipedia , lookup
Mains electricity wikipedia , lookup
Buck converter wikipedia , lookup
Transcript
CMOS Scaling into the Nanometer Regime YUAN TAUR, SENIOR MEMBER, IEEE, DOUGLAS A. BUCHANAN, MEMBER, IEEE, WEI CHEN, MEMBER, IEEE, DAVID J. FRANK, MEMBER, IEEE, KHALID E. ISMAIL, SHIH-HSIEN LO, GEORGE A. SAI-HALASZ, FELLOW, IEEE, RAMAN G. VISWANATHAN, HSING-JEN C. WANN, SHALOM J. WIND, MEMBER, IEEE, AND HON-SUM WONG Invited Paper Starting with a brief review on 0.1-m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations, and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET’s, low-temperature CMOS, and double-gate MOSFET’s, which may take us to the outermost limits of silicon scaling. Keywords— CMOS integrated circuits, integrated circuits, MOSFET logic devices, MOSFET’s, transistors, very-large-scale integration. I. INTRODUCTION After more than two decades of relentless scaling to ever smaller dimensions for higher packing density, faster circuit speed, and lower power dissipation, CMOS technology has become the prevailing technology for very large scale integration (VLSI) applications today. These advances led to computers and networks with far superior performance and dramatically reduced cost per function. Currently, 0.35m CMOS technology with 0.25- m channel length is being used in the manufacturing of 64-Mb DRAM’s and 200-MHz microprocessors with the number of transistors per chip in the – range. Meanwhile, CMOS devices of 0.1- m (100 nm) channel length have recently been fabricated in research laboratories. Fig. 1 shows the trends of power supply voltage , threshold voltage , and gate oxide thickness versus channel length for CMOS logic technologies. A key question at this point is: are we approaching the limit of silicon scaling? This paper addresses the challenges in further scaling of MOSFET’s Manuscript received September 5, 1996; revised February 10, 1997. The authors are with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598 USA. Publisher Item Identifier S 0018-9219(97)03191-5. into the sub-100-nm regime in light of fundamental physical effects and practical considerations. Section II reviews the current status of 0.1- m (100 nm) CMOS devices in terms of their performance. Section III examines key issues in scaling bulk CMOS below 100 nm. These include: lithography, power supply and threshold voltage, short-channel effect, gate oxide, highfield effects, dopant number fluctuations, and interconnect delays. Section IV discusses several alternative or unconventional device structures that may take us to the outermost limit of silicon scaling. They are: silicon-on-insulator (SOI), SiGe MOSFET, low-temperature CMOS, and double-gate MOSFET. Section V concludes the paper. II. 0.1- m CMOS RESULTS Fig. 2 shows a transmission-electron micrograph (TEM) cross section of a 0.1- m gate MOSFET with 30-Å-thick gate oxide. This device operates at a power supply voltage of 1.5 V for high-performance logic application [1]. The measured saturation transconductances versus the effective channel length are shown in Fig. 3, where the highest values are 640 mS/mm for nMOSFET and 360 mS/mm for pMOSFET, respectively. The effective channel lengths are extracted from a series of low-drain-bias – curves using the “Shift and Ratio” method [2]. The ac performance of the 0.1- m CMOS devices is shown in Fig. 4, where the measured unity-current-gain frequencies are plotted versus channel length. The highest ’s obtained are 118 GHz for nMOSFET and 67 GHz for pMOSFET [1]. These are comparable to the highest numbers reported for bipolar devices. The gate delay of a 101-stage unloaded CMOS-inverter ring oscillator is shown in Fig. 5 as a function of the supply voltage. At 1.5 V, the delay is 22 ps/stage, which is more than a factor of two faster than the 2.5-V, 0.25- m channel CMOS devices currently being manufactured. The measured delays agree well with model simulations also plotted in Fig. 5 [1]. 0018–9219/97$10.00 1997 IEEE 486 PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 Fig. 3. Measured n- and p-MOSFET saturation transconductance at room temperature versus effective channel length. Fig. 1. Power supply voltage (Vdd ), threshold voltage (Vt ), and gate-oxide thickness (tox ) trends versus channel length for CMOS logic technologies. Fig. 4. Unity-current-gain frequencies p-MOSFET’s versus channel length. (fT) of n- and Fig. 2. Cross-sectional TEM image of a 0.1-m gate MOSFET with 30-Å gate oxide. III. CHALLENGES OF SCALING BULK CMOS BELOW 100 nm This section examines the key challenges in further scaling of bulk CMOS technology into the nanometer (sub0.1 m) regime in light of fundamental physical effects and practical considerations. The issues are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations, and interconnect delays. A. Lithography It has been the ability of lithographic patterning to continually reduce device features in the lateral dimensions that has directly led us into the ultra-large scale integration (ULSI) era. Extensions beyond today’s lithography technologies are required in order to bring CMOS into the nanoscale regime. TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME Fig. 5. Measured (points, solid lines) and simulated (dashed line) CMOS inverter delay versus power supply voltage. Optical photolithography has exceeded previously predicted resolution limits many times over by a combination of improved lenses with higher numerical aperture and the use of shorter wavelength illumination. Today’s most advanced production lithography equipment uses excimer laser sources at a wavelength of 248 nm (KrF), offering a resolution near 0.25 m. Further improvements in resolution may be attained at the 193-nm wavelength (ArF). A prototype 193-nm stepper has already shown lithographic resolution to 0.18 m [3]. Resolution enhancement tech487 Fig. 6. 80-nm-wide lines patterned in APEX-E resist by X-ray lithography. The mask-wafer gap was 25 m. niques, such as phase shifting, are capable of imaging features in the 0.10–0.12- m range, with a 248-nm source [4]. This technique relies on material or topographic changes on the optical mask to vary the phase of the illuminating radiation. The resulting interference effectively sharpens the image at the wafer plane. Because this effect is geometry dependent, the phase-shifting technique has thus far not been demonstrated to be generally applicable to arbitrary device geometries which may be encountered in a chip design. With the exception of near-field techniques, which may be impractical for device fabrication applications, there are no current expectations that optical lithographic techniques will extend into the sub-100-nm regime. For the fabrication of such ultrasmall devices, optical lithography may be used for noncritical levels, in a mix-and-match scheme, where the critical features are defined by electron beam lithography or X-ray lithography. X-ray lithography is a prime candidate for high-resolution patterning of critical features for sub-100-nm CMOS applications. Fig. 6 shows line/space features with a resolution 80 nm patterned by synchrotron X-ray lithography with a mask-wafer gap of 25 m. Chen et al. have demonstrated 50-nm features patterned by proximity X-ray lithography with a 5- m gap [5]. In a near-contact printing mode, 30nm features have been resolved by X-ray lithography [6], which is sufficient to pattern gates for MOSFET devices near the currently perceived limits of operation (see later discussions). The challenges in implementing an X-ray lithography technology lie primarily in mask fabrication. Xray masks consist of thin ( 2–5 m) membranes of Si or a Si compound such as Si N or SiC, patterned with an X-ray absorbing material. Electroplated gold has been used as the absorber material. Precise control of mechanical stress in the absorber-covered membrane must be maintained, as it has a direct effect on the image placement accuracy in X-ray lithography. In addition, since X-ray proximity printing is a replication, more stringent control of defects is required as compared to systems using image reducing optics. Another form of X-ray lithography under investigation for sub-100 nm applications has come to be known as extreme ultraviolet (EUV) lithography [7]. This technique 488 uses reflective optics at the 13-nm wavelength with a 4 reduction scheme. Key challenges to this technology lie in the radiation source, in the multilayer thin-film mirror optics, and in mask fabrication [7]. Electron beam lithography has been the lithography workhorse in nanostructure patterning within the research environment for years. Since Gaussian probes can be focused to a spot of only a few nanometers, the resolution limits of e-beam lithography are primarily determined by beam-resist-substrate interactions and are thought to be 10 nm for conventional lithography and resist systems [8]. Thus, for Gaussian beam systems, resolution limitations are generally not a consideration in CMOS device applications. Pattern distortion due to electron scattering, known as proximity effects, can be effectively compensated for by a variety of correction schemes [9]. High-accuracy pattern placement can also be achieved with good stage interferometry and control over noise in the electron beam deflection system. An example of high-fidelity patterning can be seen in Fig. 7, which shows 25-nm overlay between critical levels of a 100-nm compact field-effect transistor (FET) [10]. The key challenge for e-beam lithography lies in throughput. Even with mix-and-match lithography schemes, Gaussian beam systems are incapable of patterning the 10 or more pixels required for product level chips in a reasonable time. Shaped beam systems and character projection systems offer several orders of magnitude improvement in speed by patterning many pixels in parallel, however the increase in beam current needed to achieve high throughput will limit the achievable resolution because of Coulomb interactions and off-axis aberrations [11]. An alternative technique which has received recent interest is electron beam projection lithography. Proposed projection systems use reduction optics with a mask patterned alternately with an electron absorbing material on an electron transparent [11] or electron scattering [12] substrate. Electron optical models predict that such systems can image up to 10 pixels per exposure field with a resolution near 50 nm [11], [13], limited by Coulomb interactions and geometric aberrations. Recently, there has been significant activity in patterning of thin films with proximal probes. Minne et al. [14] have demonstrated the application of surface modification to the fabrication of MOS devices. Typically, the scanning speeds of such systems are quite low ( 1 mm/s), so that significant throughput improvements will have to be realized before scanning probes can serve as the basis for lithography for CMOS applications. B. Power Supply and Threshold Voltage It is shown in Fig. 1 that as the MOSFET channel length is scaled down, power supply voltage is reduced as well to keep active power and electric field (reliability) within reasonable limits [15]. In general, the active power of a CMOS chip is given by (excluding crossover currents) (1) PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 Fig. 8. Measured power per stage versus gate delay of 0.1-m CMOS ring oscillator with Vdd as a parameter. The device widths 3 m and Wp = 4 m. are Wn = in power dissipation per device. This is needed to pack more transistors on a chip in future CMOS technologies. As the supply voltage is reduced, gate delay is traded off as a result. Nevertheless, the minimum power-delay product, corresponding to a switching energy of 2 fJ, is obtained at the lowest shown [16]. In contrast to the power supply voltage, the threshold voltage has not been scaled nearly as much, as shown in Fig. 1. This is because of the standby power requirement. The worst case standby power of a CMOS chip is given by (2) Fig. 7. Example of ultrahigh precision pattern placement for three of four critical levels of a 100-nm compact FET (four devices are shown): trench isolation, gate, and contact. A 25-nm overlay is achieved for all three levels. where is the total node capacitance being switched (either up or down) in a clock cycle and is the clock frequency. As CMOS technology advances, clock frequency goes up. The total switching capacitance is likely to increase as well, as one tries to integrate more circuits into the same or even larger chip area. The active power of today’s microprocessors is already in the 10–20-W range. Besides power management systems with architectural innovation, the most effective way to curb the growth of active power is to reduce the power supply voltage. Fig. 8 plots the power per device of a 0.1- m CMOS ring oscillator versus the gate delay by varying the power supply voltage [16]. Also shown are two points representing similar circuits fabricated with the current 3.3-V CMOS technology and with the upcoming 2.5-V technology. It is clear that by reducing the power supply voltage, one achieves a dramatic reduction TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME where is the total turnedoff device width with across it, is the worst case off-current per device width at 100 C, is the extrapolated current per width at threshold voltage (of the order of 1–10 A/ m for 0.1- m devices), is a dimensionless factor normally (see Section III-C), and is the worst case threshold voltage at 100 C. Typically, is lower than the nominal roomtemperature threshold voltage, , shown in Fig. 1 by about 200 mV because of both the temperature difference (25–100 C) and the threshold uncertainties due to channel-length tolerances. The latter stems from the short-channel effect to be discussed in the next section. The primary reason that cannot be scaled is because the inverse subthreshold slope, (ln10)( ), a measure of the transistor turn-off rate versus gate voltage, is largely driven by thermally activated diffusion and is independent of power supply voltage and channel length. In fact, even if is kept constant, the leakage current of turnedoff devices would increase in 1 proportion to and . The off-state leakage current would further increase by about 10 for every 0.1V reduction of . Fortunately, the leakage current and therefore the standby power is quite low in today’s 3.3-V chips. There is also a limited reduction of short-channel tolerances with lower power supply voltages. These allow some room for a slightly downward trend of , as shown in Fig. 1. For room-temperature CMOS devices, 1 The current at threshold condition I is proportional to the inversion 0 charge density at threshold, Qi (1–2)(kT=q )Cox , where Cox = "ox =tox is the gate oxide capacitance per unit area. 489 Fig. 9. Simulated delay/stage of a 1.5-V, 0.1-m CMOS inverter versus Vt =Vdd ratio. The delays are normalized to the value (13 0. ps) at Vt =Vdd = however, a minimum threshold voltage of 0.3–0.4 V is required, below which the standby power due to off-state leakage current becomes prohibitively high. The increasing ratio in Fig. 1 signifies a loss of gate overdrive, which degrades CMOS circuit performance gained from scaling, as can be seen in a plot of the normalized inverter delay versus in Fig. 9 [16]. Since cannot be reduced below 0.3 V and since CMOS delay increases rapidly when , there is very little performance to gain by scaling the power supply voltage to significantly below 1 V. Another problem that goes with lower operating voltages is increased sensitivity to soft errors due to ionizing radiation. The amount of charge required to upset a circuit scales down more rapidly than the charge collected from an alpha-particle hit. There are other proposals for dealing with the thresholdvoltage requirement. For example, one can fabricate multiple-threshold-voltage devices on a chip [17]. Lowdevices are used in critical logic paths for speed while high- devices are used everywhere else (including in the memory arrays) for low standby power. One can also sense the circuit activity and cut off the power supply to logic blocks that are not switching (sleep mode). Other schemes include dynamic-threshold devices with the threshold voltage controlled by a backgate bias voltage in either bulk or SOI (silicon-on-insulator) device structures to be covered in Section IV-A. However, dealing with noise margin and inductive effects might make these kinds of approaches more difficult to implement in the highest-performance systems. C. Short-Channel Effect Short-channel effect is the decrease of threshold voltage in short-channel devices due to two-dimensional (2-D) electrostatic charge sharing between the gate and the sourcedrain regions. It was mentioned in the last section that short-channel effect plays a key role in -tolerances which determine the minimum acceptable . To scale down MOSFET channel length without excessive short-channel effect, both the oxide thickness and the gate-controlled depletion width in silicon must be reduced in 490 Fig. 10. Band diagrams at threshold condition of a uniformly doped and an extreme retrograde-doped channel (profiles shown below). proportion to . The latter requires increased channeldoping concentration which, for a uniformly doped channel, leads to higher depletion charge and electric field at the silicon surface. These in turn cause the potential across the oxide and therefore the threshold voltage to go up. To reduce the gate-controlled depletion width while fulfilling the -reduction trend depicted in Fig. 1, a retrograde, i.e., low–high, channel doping is needed below 0.2- m channel length [1]. Fig. 10 shows a schematic band-bending diagram at the threshold condition of an extreme retrograde profile with an undoped surface layer of thickness . For the same gate depletion width , the surface electric field and the total depletion charge of an extreme retrograde channel is one-half of that of a uniformly doped channel. This reduces threshold voltage and improves mobility. Retrograde channel doping represents a vertically nonuniform profile that allows the threshold voltage to be decoupled from the gate-controlled depletion width. However, the body-effect coefficient,2 , and the inverse subthreshold slope, (ln10)( ), are still coupled to the gate depletion width . For a given , reduction in improves short-channel effect but compromises substrate sensitivity and subthreshold slope. Halo doping or nonuniform channel profile in the lateral direction provides yet another degree of freedom which can be tailored to further minimize -tolerances due to short-channel effect [1]. Fig. 11 shows schematically an idealized, 2-D nonuniform channel-doping profile. Pockets of high-doping regions are placed at two lower corners of the gatecontrolled depletion region where the potential difference (band bending) between the source/drain and the substrate is the highest. These regions are partly depleted by the 2 The sensitivity of threshold voltage to substrate bias, measured by m01, is usually referred to as the body effect. Body effect tends to degrade MOSFET currents when the source-to-substrate junction is reverse-biased. PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 Fig. 11. Schematic diagram of optimum 2-D nonuniform doping profiles for minimizing short-channel effect. Fig. 13. Measured and simulated Ig –Vg characteristics under inversion conditions for different oxide thicknesses. The dotted line indicates the 1-A/cm2 limit for leakage current discussed in the text. Fig. 12. High-resolution cross-sectional TEM image of polysilicon gate over a thermally grown 33-Å oxide. The cross section is in h110i plane of silicon. The silicon crystal lattice spacing (3.13 Å) provides a calibration for oxide thickness. source/drain fields and shield the rest of the channel region from further penetration. In the middle of the channel and under the gate, the doping concentration is low to keep the gate depletion charge to a minimum. Such a 2-D doping profile can be formed with self-aligned halo implants made together with the source-drain implant. Halo doping has been shown to significantly improve short-channel effect in 0.1- m channel devices and below [18], [19]. Fundamental limitations on the maximum halo doping come from band-to-band tunneling considerations discussed in Section III-E. D. Gate Oxide In order to keep short-channel effect under control and to maintain a good subthreshold turn-off slope, gate oxide thickness is reduced nearly in proportion to channel length as shown in Fig. 1. For 0.1- m CMOS devices operating at 1.5 V, an oxide thickness of about 30 Å is needed. This thickness corresponds to roughly ten layers of silicon atoms as shown in a high-resolution TEM in Fig. 12. With such a thin oxide, quantum mechanical (QM) tunneling takes place, leading to a gate leakage current that increases exponentially as the oxide thickness is scaled down. To find the scaling limitation of gate oxide, tunneling current characteristics of ultra-thin oxides have been studied for both measured and simulated current-voltage ( – ) characteristics. Due to the confinement of their motion in the direction normal to the surface, electrons in the inversion layer must be treated quantum mechanTAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME ically as a two-dimensional electron gas (2-DEG) rather than classically as a three-dimensional (3-D) gas [20]. Under these circumstances, the transmission probability is no longer a meaningful concept and the well-known Wentzel–Kramers–Brillouin (WKB) approximation or the use of Airy functions and numerical integration are not valid. Direct tunneling current from the quantized inversion layer to the polysilicon gate is calculated using a QM model [21] coupled with a transverse-resonance method [22]. In Fig. 13, an excellent agreement is shown between characteristics of the calculated and the measured – four nMOSFET devices from different processing runs – – characteristics for ( Å). Simulated oxides down to 15 Å are also shown. At a gate bias of 1.5 V, the current density increases by ten orders of magnitude as the oxide thickness decreases from 36 to 15 Å. The current gate dielectric agrees density calculated for a 15-Å reasonably with recently reported experimental data [23]. While the gate leakage current may be at a negligible level compared with the on-state current of a device, it will first have an effect on the chip standby power. If one assumes that the total active gate area per chip is of the order of 0.1 cm for future generation technologies, the maximum tolerable gate leakage current would be of the V. From Fig. 13, gate order of 1 A/cm for oxide can be scaled to 20 Å before running into such a limit. Although it may seem like a daunting task to produce 20-Å gate oxides consistently with defect densities as low as 0.1 cm , recent results on 30-Å grown films suggest that a standard deviation 0.5 Å (long-range average) can be achieved across a 200-mm wafer [21]. Below 20 Å, however, oxide tunneling current quickly becomes unmanageable. Unless a new gate dielectric material is developed, this sets a channel length scaling limit of 25–50 nm for bulk CMOS. The above considerations apply to high-performance CMOS logic chips which can tolerate a standby power in the 100-mW range. Dynamic memory 491 devices have a more stringent leakage requirement and therefore a thicker oxide limit. Since the gate leakage current increases exponentially with decreasing oxide thickness, one may be concerned with reliability issues due to greatly increased electron fluence passing through gate oxide over the lifetime of the device. However, as the power supply voltage is reduced to about 1 V, the electrons traversing the gate dielectric may no longer be considered “hot” and the rate at which these “cooler” electrons cause damage in these devices is greatly reduced [24]. There have been many publications that have demonstrated, both from a theoretical perspective as well as from measured results, that as the dielectric is thinned for a given applied bias, the charge required for dielectric breakdown increases rapidly [25]. Therefore, it is reasonable to assume that the reliability of devices incorporating 20-Å oxides will not be a limiting factor. Another issue with the thin gate oxide is the loss of inversion charge, and therefore transconductance, due to inversion layer quantization and polysilicon-gate depletion effects. In the QM model, the density of inversion electrons peaks at approximately 10 Å below the silicon surface, which effectively reduces the gate capacitance and therefore the inversion charge to those of an equivalent oxide 3–4 Å thicker than the physical oxide. Similarly, polysilicon gate depletion effect also reduces the gate capacitance and inversion charge density for a given gate drive. Both of these effects have been studied using the aforementioned one-dimensional (1-D) QM model, with the results shown in Fig. 14. The percentage of gate capacitance attenuation becomes more significant as the oxide thickness is scaled down. For a polysilicon doping of 10 cm , a 20-Å oxide loses about 20% of the inversion charge at a 1.5-V gate voltage due to polysilicon gate depletion and inversion layer quantization effects. Fig. 14. Calculated MOS capacitance under inversion normalized to the oxide capacitance as a function of gate oxide thickness. The dashed curves are calculated from a classical model with Fermi-Dirac statistics; the solid curves are calculated from the quantum mechanical model. The differences between the metal-gate and the polysilicon-gate (doped to 1020 cm03 concentration) cases are due to polysilicon depletion effects. band bending or a larger surface potential is required to populate the inversion layer. This has the effect of shifting the threshold voltage to a higher value, particularly at high fields. Under subthreshold conditions when the inversion charge density is low, the band bending is solely determined by the depletion charge governed by Poisson’s equation. Since inversion layer electrons are located in a narrow region close to the surface where electric field is nearly constant , it is a good approximation to consider the potential well as composed of an infinite oxide barrier for and a triangular potential from the depletion charge for . The solutions to the Schrödinger equation in this case are Airy functions with eigenvalues given by [20] (3) E. High Field Effects Because the power supply voltage has not been scaled in proportion to the channel length, the electric field strength has been increasing as CMOS devices are scaled down. For 0.1- m channel length devices, the oxide field has reached a maximum of 5 MV/cm, while the field in silicon has exceeded 1 MV/cm. They are expected to go even higher when the channel length is scaled into the nanometer regime. At such high fields, several undesirable effects occur, which either increase the leakage current or detract from the device performance. High field effects in gate oxides are addressed in the last section, whereas the next section discusses the high field effects in silicon: quantum effect on threshold voltage, band-to-band tunneling, and mobility degradation. 1) Quantum Effect on Threshold Voltage: In the 2-DEG QM treatment mentioned in Section III-D, electrons in the inversion layer not only are distributed away from the surface, but also occupy discrete energy levels called “sub-bands.” Since the lowest sub-band is some finite energy above the bottom of the conduction band, more 492 is the effective mass where is Planck’s constant and of electrons perpendicular to the surface. For silicon in direction, the lowest sub-band has a two-fold the degeneracy with , where is the freeelectron mass. At room temperature, several sub-bands are occupied near threshold, with a majority of the electrons in the lowest sub-band of energy above the bottom of the conduction band. If one plots the QM inversion charge , versus the surface potential on a semi-log density, scale, it exhibits the same inverse slope as the classical - curve, but with a parallel shift to the right. This means that additional band bending is required to achieve the same inversion charge per unit area as the classical value. The classical threshold condition, , should therefore be modified to , where (4) PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 Fig. 15. Additional band bending beyond 2 B needed to reach threshold condition due to QM shift of electron ground state. Fig. 15 shows the calculated as a function of . Knowing , one can easily calculate the threshold voltage shift due to quantum effect (5) where is the body-effect coefficient, usually between 1.2 and 1.5. It is clear that the quantum effect on threshold voltage becomes nonnegligible when V/cm. Beyond V/cm, the threshold voltage can increase by as much as 0.2 V or more due to quantum effect, making it very difficult to design a channel profile that controls the short-channel effect while still having a low enough compatible with the 1-V power supply. The retrograde doping profile discussed in Section III-C is indispensable in limiting the surface electric field and therefore minimizing such effects. 2) Band-to-Band Tunneling in Silicon: It was discussed in Section III-C that in order to control short-channel effect, high doping pockets in the form of halos are needed to limit the penetration of source/drain fields into the MOSFET depletion region. This creates a high field region near the drain, where a band bending of 1–2 V occurs within a distance as little as 100 Å. Under these conditions, quantum mechanical band-to-band tunneling takes place, which could result in significant junction leakage currents. The exact form of the electron tunneling barrier is not generally known. Two types of barriers are commonly assumed: the triangular and the parabolic barriers. Both models assume a constant field across the tunneling region, yet the parabolic barrier is the simplest algebraic function with the correct behavior at the boundaries. Using the WKB approximation, one can express the tunneling current density for a triangular barrier of height (silicon bandgap) as [26] (6) is the electron effective mass and is the where reverse bias voltage across the p-n junction. The tunneling TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME Fig. 16. Calculated band-to-band tunneling current density as a function of electric field. The solid line is for a triangular potential barrier and the dashed line is for a parabolic barrier. The dotted line indicates the 10-A/cm2 limit for leakage current discussed in the text. current density for a parabolic barrier is almost identical to that for a triangular barrier, except that the numerical factor , is replaced by . Fig. 16 in the exponent, versus electric field for both barrier profiles plots V and , where is the free assuming electron mass. Because of the exponential dependence, increases very rapidly with the electric field . The current density for the parabolic potential barrier is greater than that for the triangular barrier at the same field. To estimate how high a field can be tolerated from a tunneling leakage point of view, we assume that the high field region near the drain in Fig. 11 is approximately 100-Å wide in the direction perpendicular to the surface. A tunneling current density of 10 A/cm would then correspond to a drain leakage current per device width of 1 nA/ m. Such a leakage current is tolerable in highperformance logic technologies since it is comparable to or less than the worse case source-drain leakage specification at the highest chip temperature (tunneling current is insensitive to temperature). The same conclusion can be drawn from a chip standby power consideration as that given in the gate oxide section. According to Fig. 16, this sets a limit of about 2 MV/cm for the maximum field in the drain depletion region, which should allow a reasonable design point for 50-nm channel length MOSFET’s. 3) Mobility Degradation: Another consequence of operating nanometer CMOS devices at high fields is mobility degradation. It is well known that both electron and hole mobilities exhibit a “universal” behavior when plotted versus the effective field experienced by an average carrier [27]. Fig. 17 shows the measured effective electron and hole mobilities from 70- and 30-Å gate oxide devices versus . The effective field is defined by the effective field , where and represent the depletion and inversion charge per unit area that can be obtained from a split C–V measurement [28]. The effective and the longmobility is calculated from the measured 493 Fig. 17. Measured electron and hole mobilities versus effective field for two oxide thicknesses. Dotted lines indicate asymptotic trends of phonon scattering and surface roughness scattering. channel MOSFET current in the linear region with a very small applied source-drain voltage, – mV. When V/cm, the mobility essentially follows a dependence as the carrier transport is dominated by phonon scattering. At higher fields, the carriers are increasingly pressed toward the Si/SiO interface and surface scattering [29] becomes dominant. Surface scattering is sensitive to the conditions of the Si/SiO interface and usually results in a to dependence for the mobility, as indicated in Fig. 17. Because of this stronger dependence, both electron and hole mobilities decrease rapidly when V/cm, which degrades the performance gained from scaling. F. Effects of Random Dopant Distribution Random fluctuation of the number of dopant atoms in the channel of MOSFET’s had been predicted to be a fundamental physical limitation of MOSFET miniaturization since the 1970’s [30]. As MOSFET scaling approaches the sub-100-nm regime, the number of dopants is of the order of hundreds in the depletion region for minimum geometry devices. As a result, the detailed microscopic dopant distribution in the MOSFET channel will have non-negligible effects on device threshold voltages. In particular, threshold matching, which is important for certain types of circuits such as SRAM and sense amplifiers, may be limited by such fluctuations. The dependence of the terminal currents and the threshold voltage on: 1) the random fluctuation of the number of dopants in the MOSFET channel and 2) the discrete microscopic random distribution (arrangement) of dopant atoms in the MOSFET channel [31] was studied using a 3-D driftdiffusion device simulator FIELDAY [32]. Fig. 18 shows an example set of I–V curves of 24 MOSFET’s with different random “atom” distributions for nm, nm, Å, and an average uniform substrate doping of 8.6 10 cm . Comparing with the I–V of the same MOSFET simulated using the conventional continuum dop494 Fig. 18. Drain current versus gate voltage for a conventionally doped MOSFET (solid circles) and 24 devices with different discrete dopant distributions in the channel (grey lines). The average current of all 24 devices were shown in solid triangles. The threshold voltage shift in the subthreshold region was defined as the gate voltage shift at a constant current level (Ioff ). ing model, the discrete doping simulation displayed: 1) a spread of the I–V curves along the gate voltage axis of about 20–30 mV (one standard deviation); 2) an average shift of the I–V toward the negative gate voltage direction of about 30 mV in the subthreshold and of about 15 mV in the linear region; and 3) a slight degradation ( 3 mV/dec) and fluctuation of the subthreshold slope. shift in the subthreshold was obtained by current averaging and was larger than in the linear region because of the logarithmic dependence. The additional shift of the average in the subthreshold region means that conventional estimations of the off-current (hence standby power) from the linear region threshold voltage could be about a factor of two too low. Decreasing the channel doping resulted in smaller deviations from the continuum model. Furthermore, the high-drain I–V of narrow width devices were asymmetric upon interchanging the source and the drain terminals. The asymmetry of threshold is about 20–40 mV (one standard deviation). This asymmetry can be attributed to the discrete and random nature of the dopant atoms, which results in an inhomogeneous channel potential. The effects of discrete random dopants become more important as the channel length and width are scaled down. The uncertainty due to discrete random dopants for a retrograde (low–high) channel doping can be shown analytically to be (7) where is the maximum gate depletion width and is the width of the low-impurity (assumed undoped) region. In an extreme retrograde-doped channel, and the depletion charge contribution to the threshold voltage ,3 insensitive to the doping concentration is beyond the undoped layer. This essentially eliminates the effect of dopant number fluctuations on threshold voltage. 32 B is the band bending defined in Fig. 10. PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 G. Interconnect Delays If the performance of processors is to keep pace with the speed improvement of devices, special attention has to be paid to interconnections. This is because the delay stemming from wire resistance, commonly referred to as delay, to first order is (8) and has to be included with other delay components. Here, and are the resistance and capacitance of unit wire length, is the wire length, and is the load at the end of the wire. The part in the delay due to the wire alone does not decrease in spite of scaling to smaller dimensions. The factor that improves the term through shorter is negated by the increase in due to wire cross-sectional shrinkage. Wire capacitance in the meantime remains constant, around 0.2 pF/mm for minimum width wires with oxide dielectric [33]. Traditionally the wire delays were barely noticeable even on long wires, but for high-performance CMOS CPU’s, the resistance in the wiring can be critical. If one looks carefully at roles various interconnects play, a performance-oriented approach immediately suggests itself [34], [35]. High-performance processors need two kinds of wires. First, there are the “short” wires that serve the vast majority of interconnects. For CMOS processors they are typically up to 1–2 mm in length. They are mainly responsible for making the chip “wirable” by providing sufficient number of interconnections. Here the delay plays no appreciable role; capacitance is the only consideration. Such “short” wires should follow the minimum lithography features of the available technology. Second, there is a need for “long” wires, where density is secondary to delay considerations. They run between distant parts of the chip, and their characteristic length is that of a chip-edge. A good scaling gauge for such “long” wires is that the time of signal propagation on them should be only a small fraction of the cycle-time. From such considerations, it immediately follows that the cross section of these wires and insulators cannot have minimum lithography features. This type of interconnects will be referred to as “fat” wires [34], [35]. Typically, the bottom two levels are at the finest pitch for which the device technology can take advantage. Here, lines and spaces should be almost at minimum design rules. The next two levels’ dimensions should already pay attention to the problem, and finally the top two can serve to run signals to full chip-edge length, or longer, distances. With this type of wiring, where conductor and dielectric crosssectional dimensions are scaled together, capacitance per unit length stays constant for each level, while resistance decreases proportionally with wire cross-sectional increase. The number of wiring planes and pitch ratios amongst them must be optimized for any given design. For reaching the highest performances, ratios where the second - planepair resistance per unit length is one-fourth and the third is one-thirty-sixth that of the bottom plane are quite realistic. TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME Fig. 19. RC delay versus wire length for three different wire sizes (assuming square wire cross sections). Wires become electromagnetic-wave-propagation limited when the RC delay equals the time of flight over the line length. One consequence of having low wires is that one will observe transmission line characteristics not only on the package, but also on the chips themselves [36]. With an oxide insulator the minimum delay that a signal can achieve due to the finite velocity of electromagnetic wave propagation is 7 ps/mm. When the input of a low resistance wire is driven with a faster signal than the travel time down that line, delays are necessarily dominated by transmission line characteristics, and finite signal propagation speed and inductive coupling effects must be taken into account [36]. Fig. 19 shows the interconnect delay versus wire length for three different wire cross sections. Long, thin wires are limited by effects, in which the delay increases quadratically with wire length [see (8)]. To reach the limit of electromagnetic wave propagation where the signal delay increases only linearly with wire length, a larger cross section is required for longer wires. With the projected chip size in the 1–3-cm range, the wiring hierarchy scheme described above should allow the building of future microprocessors with clock frequencies well in the gigahertz regime. It might seem that the “fat” wiring scheme wastes too many wiring channels in comparison with having all levels at minimum dimensions. The difference between the number of wiring-channels offered by the two cases is not as large as it might first appear. The reason is that wiring levels block one another. Thus, a “fat” wire on the top provides less wiring capability than one at fine pitch, but if the fine pitch wire were fully utilized, it would impact more severely the number of available wiring channels in all of the lower levels. If all the pitches are identical, it is estimated that a level blocks 12%–15% of the wiring capacity of every layer underneath it. Even with efficient wiring protocols, six or seven wiring levels is about the maximum useful number. One also has to ask whether the performance of processors will be limited by wires, since wire capacitance per unit length tends to stay essentially constant (0.2 pF/mm) and does not scale with technology. As a processor is scaled, both wire length and device width decreases with , the design rule scaling factor. Thus, wiring load 495 decreases linearly with . If the useful device capacitance (the inversion layer capacitance) scales similarly, the ratio of device to wire capacitance does not change. This happens if oxide capacitance per unit area stays on a scaling path. Even if the inversion layer capacitance per unit area does not scale up exactly as (Section III-D), one can maintain performance scaling by increasing device widths. This does not have to result in total processor area enlargement because the size of the system, as determined by wiring constraints, can easily accommodate increased device widths [35]. The net result is higher power consumption than pure scaling would dictate, but without relative performance loss. The same line of reasoning also shows that lowering the inter-level dielectric constant saves power but leads to higher performance only in as much as it allows higher propagation speed on long wires. The speed of well-designed CMOS processors will depend on device properties for as far as one can see along the path of device scaling. One further remark regarding interconnects: any future technology, not only CMOS, has to deal with the nonscaling nature of wire capacitance. Fast devices are useless unless they can drive capacitances that are comparable to wire capacitances. The concept of device width for FET’s can be extended to any device no matter how exotic it might be. One has to parallel them up to add to their driving capability. In this light, many exotic/nano schemes face more significant problems in building real processors than just simply making devices ever smaller. IV. NOVEL DEVICES This section discusses several alternative or unconventional device structures that may offer further improvement in performance or power over bulk CMOS and take us to the outermost limit of silicon scaling. They are: silicon-oninsulator (SOI), SiGe MOSFET, low-temperature CMOS, and double-gate MOSFET. A. SOI CMOS Silicon-on-insulator technology, once mainly used in radiation-hard applications, has emerged as a promising candidate for mainstream ULSI applications in the deepsubmicron era. The SOI MOSFET (Fig. 20) may be able to provide solutions to some increasingly difficult device and process challenges, such as shallow junction, soft-error, and isolation, encountered in bulk CMOS technologies. SOI substrates fabricated by ion implantation (SIMOX) and wafer bonding are of particular interest for competitive ULSI CMOS applications due to progress in material quality and compatibility with established processing technology. SOI MOSFET’s are often distinguished as partiallydepleted (PD) SOI MOSFET when the silicon film thickness ( in Fig. 20) is larger than the depletion width and the devices exhibit floating-body effect (Fig. 21), and fully depleted (FD) SOI MOSFET when the silicon film thickness is smaller than the depletion width. FD 496 Fig. 20. Cross-sectional view of SOI MOSFET. The silicon film thickness (tsi ) for device application is around 100 nm, but can be as thin as 20 nm. The buried insulating layer thickness is around 400 nm for SIMOX. 80-nm BOX is also available. For SOS wafers, the entire substrate is an insulator (sapphire). Fig. 21. Subthreshold characteristics of floating-body and linked-body SOI devices. Floating-body effect increases the high-drain off-current of a partially depleted SOI nMOSFET. Linked-body SOI characteristics are the same as bulk devices. SOI MOSFET’s exhibit superior subthreshold characteristics, thereby attracting attention for low-voltage operation. However, the nearly ideal subthreshold slope of a FD SOI MOSFET results from very different factors when compared to a double-gate MOSFET, which also has nearly ideal subthreshold slope [37]. The channel potential of any MOSFET is controlled by both the front gate and the back gate. For double-gate MOSFET’s, the ideal subthreshold slope is because the channel is being controlled by both gates, which are switched simultaneously. However, in FD SOI MOSFET’s, the nearly ideal subthreshold slope occurs because the back gate does not have much control over the channel. The lack of back gate control leaves a wide depletion or dielectric region vulnerable to source-drain field penetration, which results in poor short-channel effect [38]. This point is further addressed in Section IV-D. It should be noted that there is no abrupt boundary between PD and FD; the floating-body or kink effect occurs PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 when the majority carriers generated by impact ionization or junction leakage—and thereafter stored in the floating body—can affect the device threshold voltage. When the silicon film thickness is reduced, the barrier height of the body-to-source junction is lowered and there is less change in both the body potential and the threshold voltage. The floating-body effect becomes rather complex in ac conditions. In practical circuit switching, the chargingup of the floating body capacitance by junction leakage and impact ionization usually takes a longer time than the input transition. For example, the kink effect is not observed in pulse measurements [39]. In fast gate ramp, the body potential is directly coupled to the gate potential, and increases the transient current. This which reduces phenomenon is referred to as the drain current overshoot. The importance of this component increases at larger bodyto-gate capacitance, smaller body-to-source/drain capacitance, smaller output loading, and at larger due to wider swing. One can take advantage of the direct gate-to-body coupling in designing circuits using PD SOI MOSFET’s. Since the performance advantage of SOI over bulk depends strongly on circuit design, it is not unusual that the improvement factors reported in the literature vary widely. With a major part of the SOI advantage coming from its inherently low junction capacitance (Fig. 20), the speed improves the most in unloaded circuits. For a three fan-out ring oscillator with 300 fF load per 15- m device width, the improvement in delay/stage over bulk is 20%–25% at the same level of power dissipation [40]. One undesirable consequence of the floating-body effect in a PD SOI is the higher off-current due to a forwardbiased body-to-source junction when the drain voltage is high, as shown in Fig. 21. Using body contacts can restore the device characteristics of SOI MOSFET’s back to bulk-MOSFET-like characteristics. There were many body contact schemes proposed. For example, the body contact can be placed at the edge of the device, however at the expense of larger area and higher parasitic capacitance. Alternatively, one can use incomplete isolation (linkedbody) [41] to leave a thin silicon film in the surrounding area of the transistor, whereby the body can be electrically connected through the edge then tied down to the source or the ground. Fig. 21 shows that this restores the highdrain off-current of a PD SOI nFET to the low bulk-like value. In the above examples, the body is contacted at the edge of the device, hence the time constant of the contact increases as increases. Another approach is to contact the body from the source side or to use a “leaky source.” Such source side contacts can be accomplished by, for example, alloy-spikes, quasi-SOI [42], and low-barrier source junctions [43]. The source-side body contacts can be effective at high switching speeds, but require asymmetric source/drain structures and a critical mask overlay. Another type of SOI device, the dynamic-threshold MOSFET (DTMOS), is obtained by tying the body to the gate so that they both switch in a transition [44]. Such devices can have high when is low to suppress off current and low when is high to increase on current. DTMOS TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME Fig. 22. Device characteristics of DTMOS [44]. DTMOS has an ideal subthreshold swing. However, the operating voltage must be limited to avoid large body current. Fig. 23. Electron mobility and density versus gate voltage in strained Si/SiGe in an oxide-gated structure. For comparison, the electron mobility in bulk Si MOS is shown (dotted). is essentially a double-gate MOSFET whose subthreshold slope is close to the ideal value of 60 mV/dec (Fig. 22). However, DTMOS must be operated below the p-n junction turn-on voltage to avoid significant forward-bias currents at the body to source/drain junctions, hence it is more suitable for very low voltage operation. B. SiGe MOSFET The transition from Si to a different material system with better transport properties seems to be an attractive solution, provided a material system can be found that is compatible with state-of-the-art technology of fabrication. The epitaxial growth of strained SiGe compounds on Si substrates allows the strain in the Si and SiGe layers to be tuned. In Si under tensile strain and in SiGe under compressive strain, the electron and hole mobilities, respectively, are enhanced. Furthermore, due to the confinement of the charge carriers in a quantum well, cladded by a heteroepitaxial layer, there is no measurable roughness scattering at room temperature associated with this material system, as in the case of Si/SiO . In an oxide-gated sample (70-Å oxide thickness) with a buried strained Si channel, high electron mobility in excess of 2200 cm /V-s (Fig. 23) can be maintained at an electron density of 3 10 cm [45]. Similarly, a high 497 Fig. 24. Layer cross section of a Si/SiGe CMOS structure. The strained Si channel is populated with electrons under positive gate bias (see conduction band on the right), and the strained SiGe channel is populated with holes under negative gate bias (see the valence band on the left). hole mobility in excess of 800 cm /V-s can be achieved in a modulation-doped Si/SiGe heterostructure at a hole density of 3 10 cm [46]. Saturation velocities of electrons and holes in strained Si and SiGe are comparable to bulk Si, but are reached at much lower lateral fields. This translates into a lower bias requirement and, consequently, lower power consumption and higher reliability. A possible design of a Si/SiGe CMOS [47] is shown in Fig. 24. Hydrodynamic simulations of 0.1- m devices with a threshold voltage in the range of 0.3–0.35 V indicate a significant velocity overshoot in the n-FET and a small overshoot in the p-FET, even at a bias of 0.8 V. At this bias, the Si/SiGe CMOS offers a four-fold reduction in power-delay compared to bulk Si operated at 1.5 V, while expecting a similar delay. Thus, the higher mobility material can be viewed as an addition/alternative to scaling, which promises to improve the power and performance of CMOS technology at the same channel length. This is at the expense of having to optimize the growth conditions of this strained material, and to develop low-temperature processing techniques ( C) to avoid strain relaxation and Ge segregation problems. That includes growing or depositing gate oxide layers at C, and annealing ohmic contact and C while achieving high dopant other implants at activation and low junction leakage currents. Furthermore, the scaling of the layer thickness of the Si and SiGe channels is limited to about 30 Å (due to quantum mechanical effects), hence the gate-to-channel separation will always be larger than in surface-channel Si CMOS. C. Low-Temperature CMOS The advantages of low-temperature MOSFET operation for high-performance systems have been recognized and 498 advocated for a long time [48]. It appears, however, that as long as performance improvements can be made at room temperature, low-temperature operation will not be taken seriously. Since now we are perceiving limits in roomtemperature CMOS performance, we must re-examine lowtemperature CMOS in the nanometer regime. Because of higher carrier mobility and lower interconnect resistance, low-temperature CMOS can provide a factor of 1.5–2.0 performance gain over room-temperature CMOS [49]. More importantly, at low temperature the subthreshold slope steepens by a factor proportional to , making it much easier to turn off a MOSFET than at room temperature. This allows for additional low-threshold, low-voltage design space from which room-temperature operation is excluded because of the high off-currents (Section III-B). However, steeper subthreshold slope by itself is not sufficient for operating at a low threshold voltage. Very tight threshold tolerance is required as well, which means that an optimum halo-doping profile discussed in Section III-C is even more important for low-temperature CMOS. Measured low-temperature saturation transconductance with a 30-Å gate oxide reached 1040 mS/mm for nMOSFET [18] and 510 mS/mm for pMOSFET [50], respectively. Fig. 25 shows the waveform of a 43-stage inverter-type MOS ring oscillator at 85 K. A minimum delay of 7.8 ps per stage was obtained from the 0.08- m channel ring oscillator operating at 2.5 V [18]. This is the fastest switching speed reported to date for any silicon device at any temperature. D. Double-Gate MOSFET In an effort to understand the outermost limits of scaling, recent simulation studies have focused on double-gated FET’s [51], [52]. The structure of these FET’s is sketched PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 (a) Fig. 25. Measured waveform of a 43-stage, 0.08-m channel n-MOS ring oscillator at 85 K. The gate delay is 7.8 ps per stage. (b) Fig. 26. Simulated threshold voltage versus channel length, comparing short-channel effect of double-gate FET’s (solid lines) with SOI MOSFET’s (dashed lines), where the threshold of the long-channel FET’s has been taken as zero. These values are extracted from drift diffusion simulations of the subthreshold regime of these FET’s. Inset: cross-sectional structure of a double-gated FET. in the inset to Fig. 26. There is a very thin Si layer for a channel, with two gates, one on each side of the channel. The two gates are electrically connected so that they both serve to modulate the channel. Short channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field lines, preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold with drain voltage and with gate length of a double-gated FET is much smaller than that of a conventional single-gated structure of the same channel length. This can be seen in Fig. 26, where the threshold versus gate length behavior of the double-gated MOSFET is compared with that of singlegated SOI MOSFET’s (fully depleted as that discussed in Section IV-A). Note that for the same channel thickness, the double-gated FET’s can be scaled to two–three times shorter channel lengths. To estimate a limit on the scaling of such double-gated FET’s, it is necessary to consider various device physics TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME Fig. 27. Monte Carlo simulation of drain current versus drain voltage for (a) n-channel and (b) p-channel double-gated MOSFET. Both channel lengths are 30 nm; channel thickness is 50 Å. Note the high transconductance (2300 mS/mm for nFET, 1300 mS/mm for pFET) and the low output conductance. principles and tolerance issues. Since voltages must be low, the threshold voltage uncertainty should be kept to 100 mV or less. Channel thickness uncertainty causes uncertainty in the energy of the first quantized energy level of the channel, which translates into threshold voltage variation. This uncertainty grows very rapidly as the channel is thinned, which results in a minimum viable channel thickness of 40–50 Å, assuming a thickness tolerance of 20%. Given a 50-Å-thick channel and 30-Å-thick gate oxide, Fig. 26 indicates a minimum channel length of 30 nm using the criterion of 100-mV threshold variation for a 30% gate length variation. Similarly, for an oxide thickness of 20 Å and a channel thickness of 40 Å, a minimum channel length of 20–25 nm should be possible. To avoid threshold fluctuations due to the discreteness of the dopants, it would be necessary to adjust the threshold of this FET by the work function of the gate, leaving the channel undoped. To evaluate the potential on-state performance of these FET’s, detailed Monte Carlo simulations were performed [51], [52] using the simulator DAMOCLES [53]. Both nand p-channel MOSFET’s have been simulated, yielding 499 Fig. 28. Monte Carlo simulation of electron energy versus position down the channel of an n-channel double-gate MOSFET. The points represent electrons and the line indicates the conduction band edge. The height of the points above the band edge indicates their kinetic energy. low output conductance, high-performance I–V characteristics for both device types, as is illustrated in Fig. 27. The transconductance exceeds 2300 mS/mm for this nFET, and it reaches 1300 mS/mm for the pFET. Transient Monte Carlo simulations were also done for the nFET switching a capacitive load equivalent to another nFET. This resulted in a minimum estimated switching time of 1.1 ps for this nFET, clearly indicating the potential for performance in these tiny FET’s. The Monte Carlo simulations also allow an analysis of the internal carrier behavior of the double-gate MOSFET. As illustrated in Fig. 28, the carriers behave quite ballistically in these short devices. Very little kinetic energy is lost until 500 the carriers reach the drain end of the device. In keeping with this observation, the electrons reach peak velocities as 10 cm/s just before entering the drain. The high as 3 10 cm/s, even though holes, however, only reach 1.3 they lose relatively little energy. It appears that a high momentum scattering rate is responsible for reducing the hole velocities and currents to only about half those of the electrons in the nFET, even at the limits of scaling. While it is not trivial to accurately model the doublegate MOSFET at its scaling limits, it is even more difficult to fabricate the ideal double-gate MOSFET (see inset to Fig. 26). Considering the 3-D nature of the doublegate MOSFET, Fig. 29 shows all the possible configuraPROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 that self-alignment of the gates to the source and drain is key to high circuit speed. This is because of increased gateto-drain overlap capacitance and/or loss of current drive in nonself-aligned structures. None of the planar devices [Fig. 29(a)] reported in the literature so far [54], [55] has a self-aligned bottom gate. The challenges, therefore, lie in the fabrication of double-gate MOSFET’s with both gates self-aligned to the source and drain. V. CONCLUSION (a) (b) (c) Fig. 29. Three possible orientations of a double-gate MOSFET on a silicon wafer. Examples of devices fabricated are: (a) Colinge et al. [54], Tanaka et al. [55], (b) Takato et al. [56], and (c) Hisamoto et al. [57]. tions defined in terms of the 2-D current carrying plane [54]–[57]. To control short channel effects, the silicon channel thickness should be approximately one-fourth of the gate length [58]. Thus, the surrounding gate or pillar transistor [56] and DELTA devices [57] with the currentcarrying plane normal to the wafer surface [Fig. 29(b), (c)] would require a lithographic and pattern transfer capability four times more stringent than the minimum gate length. Furthermore, device and circuit simulations [58] showed TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME In conclusion, CMOS devices will scale into the nanometer regime with improved device performance and lower power before running into fundamental barriers of physics. A 50-nm channel length bulk MOSFET would have a 20-Å-thick gate oxide and a power supply voltage near 1 V for high-performance applications. The maximum electric field would reach 5 MV/cm in the oxide and 2 MV/cm in silicon ( 1 MV/cm at threshold condition). Nonuniform channel doping in both the vertical (retrograde) and the lateral (halo) directions will be used to minimize short-channel effects. For low-power applications, multiple and/or dynamic threshold voltages may be implemented with a power supply voltage 1 V for active/standby power management. A hierarchical wiring scheme with six–eight metal levels will be necessary to deal with the interconnect delays. With the top-level global wires limited only by the speed of electromagnetic wave propagation, it should be possible to build processors with clock frequencies well into the gigahertz regime. In practice, however, many difficult challenges lie ahead in tightening process tolerances to satisfy more stringent defect density and reliability requirements in future generation CMOS technologies. Some of the solutions call for a paradigm shift and costly buildup of new infrastructures, e.g., in the case of X-ray lithography. Others require near atomic-level thickness control and nanometer-scale lateral-dimension inspection and control. Much lower defect densities and higher device yields than today’s standard will undoubtedly be required when multi-billion transistors are fabricated on a single chip. Finally, several novel/alternative CMOS device structures have been discussed. SOI and SiGe devices offer performance and power advantage over bulk CMOS without channel length scaling, while low-temperature CMOS and double-gate MOSFET’s can potentially take us to the outermost limit of silicon scaling. The challenges, however, lie in the fabrication of self-aligned double-gate MOSFET’s and low-cost cooling of VLSI chips/packages to low temperatures. ACKNOWLEDGMENT The authors would like to thank R. H. Dennard, T. H. Ning, L. Su, F. Assaderaghi, K. A. Jenkins, S. Rishton, J. O. Chu, J. Y.-C. Sun, E. Crabbe, E. Nowak, and F. Stern for many stimulating discussions. They would also like to thank the Yorktown, NY, Silicon Facility and the Advanced Silicon Technology Center in East Fishkill, NY, for device fabrication. 501 REFERENCES [1] Y. Taur, S. Wind, Y. Mii, Y. Lii, D. Moy, K. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfield, M. Thomson, and M. Polcari, “High performance 0.1 m CMOS devices with 1.5 V power supply,” in 1993 IEDM Tech. Dig., pp. 127–130. [2] Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, “A new shift and ratio method for MOSFET channel length extraction,” IEEE Electron Device Lett., vol. 13, p. 267, 1992. [3] S. C. Palmateer, R. R. Kunz, M. W. Horn, A. R. Forte, and M. Rothschild, “Optimization of a 193-nm silylation process for sub-0.25 m lithography,” in Proc. SPIE, 1995, vol. 2438, p. 455. [4] P. Agnello, T. Newman, E. Crabbe, S. Subbanna, E. Ganin, L. Liebmann, J. Comfort, and D. Sunderland, “Phase edge lithography for sub-0.1 m electrical channel length in a 200 mm full CMOS process,” IEEE 1995 Symp. on VLSI Technology, Dig. Tech. Papers, 1995, p. 79. [5] Y. Chen, R. K. Kupke, F. Rousseaux, F. Carcenac, D. Decanini, M. F. Ravet, and H. Launois, “50 nm X-ray lithography using synchrotron radiation,” J. Vac. Sci. Technol., vol. B12, p. 3959, 1994. [6] H. I. Smith and M. L. Schattenburg, “X-ray lithography, from 500 to 30 nm: X-ray nanolithography,” IBM J. Res. Devel., vol. 37, p. 319, 1993. [7] R. H. Stulen, “13-nm extreme ultraviolet lithography,” IEEE J. Select. Topics. Quantum Electron., vol. 1, p. 970, 1995. [8] W. Langheinrich, A. Vescan, B. Spangenberg, and H. Beneking, “The resolution of the inorganic electron beam resist, LiF(Al3 ),” Microelectronics Eng., vol. 23, p. 287, 1994. [9] M. Parikh, “Corrections to proximity effects in electron beam lithography,” J. Appl. Phys., vol. 50, p. 4371, 1979. [10] S. J. Wind, C. M. Reeves, J. J. Bucchignano, Y. T. Lii, T. H. Newman, D. P. Klaus, J. Keller, R. P. Volant, B. Tebin, and F. J. Hohn, “Fabrication of compact 100 nm-scale silicon metal-oxide-semiconductor field effect transistrs,” J. Vac. Sci. Technol., vol. B10, p. 2912, 1992. [11] H. C. Pfeiffer and W. Stickel, “PREVAIL—An e-beam stepper with variable axis immersion lenses,” Microelectronic Eng., vol. 27, p. 143, 1995. [12] S. D. Berger, J. M. Gibson, R. M. Camarda, R. C. Farrow, H. A. Huggins, J. S. Kraus, and J. A. Liddle, “Projection electron beam lithography: A new approach,” J. Vac. Sci. Technol., vol. B9, p. 2996, 1991. [13] L. R. Harriott, S. D. Berger, J. A. Liddle, G. P. Watson, and M. M. Mkrtchyan, “Space charge effects in projection charged particle lithography systems,” J. Vac. Sci. Technol., vol. B13, p. 2404, 1995. [14] S. C. Minne, H. T. Soh, P. Flueckiger, and C. F. Quate, “Fabrication of 0.1 m metal oxide semiconductor field effect transistors with the atomic force microscope,” Appl. Phys. Lett., vol. 66, p. 703, 1995. [15] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, p. 256, 1974. [16] Y. Mii, S. Wind, Y. Taur, Y. Lii, D. Klaus, and J. Bucchignano, “An ultra-low power 0.1 m CMOS,” in 1994 VLSI Technology Symp. Tech. Dig., pp. 9–10. [17] Y. Taur, Y. Mii, D. Frank, H.-S. Wong, D. Buchanan, S. Wind, S. Rishton, G. Sai-Halasz, and E. Nowak, “CMOS scaling into the 21st century: 0.1 m and beyond,” IBM J. Res. Devel., vol. 39, p. 245, 1995. [18] Y. Mii, S. Rishton, Y. Taur, D. Kern, T. Lii, K. Lee, K. Jenkins, D. Quinlan, T. Brown Jr., D. Danner, F. Sewell, and M. Polcari, “Experimental high performance sub-0.1 m channel nMOSFET’s,” IEEE Electron Device Lett., vol. 15, p. 28, 1994. [19] L. Su et al., “A High performance 0.08 m CMOS,” in 1996 VLSI Technology Symp. Tech. Dig., p. 12. [20] F. Stern, “Self-consistent results for -type Si inversion layers,” Phys. Rev. B, vol. 5, no. 12, pp. 4891–4899, 1972. [21] D. A. Buchanan and S.-H. Lo, “Growth, characterization and the limits of ultra-thin SiO2 -based dielectrics for future CMOS applications,” in The Physics and Chemistry of SiO2 and the Si-SiO2 Interface-3, H. Z. Massoud, E. H. Poindexter, and C. 502 [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] R. Helms, Eds. Pennington, NJ: The Electrochemical Society, 1996, pp. 3–14. R. E. Collin, Field Theory of Guided Waves, 2nd ed. Piscataway, NJ: IEEE Press. H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, “Tunneling gate oxide approach to ultrahigh current drive in small-geometry MOSFET’s,” in IEDM Tech. Dig., 1994, pp. 593–596. D. J. DiMaria and J. W. Stasiak, “Trap creation in silicon dioxide produced by hot electrons,” J. Appl. Phys., vol. 65, p. 2342, 1989. K. F. Schuegraf and C. Hu, “Hole injection SiO2 breakdown model for very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices, vol. 41, p. 761, 1994. R. B. Fair and H. W. Wivell, “Zener and avalanche breakdown in as-implanted low-voltage silicon - junctions,” IEEE Trans. Electron Devices, vol. ED-23, p. 512, 1976. A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted Si surface,” in 1979 IEDM Tech. Dig., pp. 18–21. C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors,” Solid-State Electron., vol. 25, p. 833, 1982. Y. C. Cheng and E. A. Sullivan, “On the role of scattering by surface roughness in silicon inversion layers,” Surface Sci., vol. 34, p. 717, 1973. B. Hoeneisen and C. A. Mead, “Fundamental limitations in microelectronics—I. MOS technology,” Solid-State Electron., vol. 15, p. 819, 1972. H. S. Wong and Y. Taur, “Three-dimensional atomistic simulation of discrete random dopant distribution effects in sub-0.1 m MOSFET’s,” in 1993 IEDM Tech. Dig., p. 705. E. Buturla, J. Johnson, S. Furkay, and P. Cottrell, “A new 3-D device simulation formulation,” in NASCODE VI: Sixth Int. Conf. on Numerical Analysis of Semiconductor Devices and Integrated Circuits, Dublin, Boole Press, 1989, p. 291. D. C. Edelstein, G. A. Sai-Halasz, and Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Devel., vol. 39, p. 383, 1995. G. A. Sai-Halasz, “Directions in future high-end processors,” in Proc. IEEE ICCD, 1992, p. 230. , “Performance trends in high-end processors,” Proc. IEEE, 1995, vol. 83, pp. 20–36. A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, R. P. Dunne Jr., T. A. Gallo, and R. H. Dennard, “Modeling and characterization of long on-chip interconnections for high-performance micro-processors,” IBM J. Res. Devel., vol. 39, p. 547, 1995. C. H. Wann, R. Tu, B. Yu, C. Hu, K. Noda, T. Tanaka, M. Yoshida, and K. Hui, “A comparative study of advanced MOSFET structures,” in 1996 VLSI Technology Symp. Tech. Dig., p. 32. L. T. Su, J. B. Jacobs, J. Chung, and D. A. Antoniadis, “Deepsubmicronmeter channel design in silicon-on-insulator (SOI) MOSFET’s,” IEEE Electron Device Lett., vol. 15, no. 5, pp. 183–185, May 1994. J. Gautier and J. Y.-C. Sun, “On the transient operation of partially depleted SOI NMOSFET’s,” IEEE Electron Device Lett., vol. 16, no. 11, pp. 497–499, Nov. 1995. G. G. Shahidi et al., “CMOS scaling in the 0.1 m, Volt regime for high-performance applications,” IBM J. Res. Devel., vol. 39, p. 229, 1995. W. Chen, Y. Taur, D. Sadana, K. Jenkins et al., “Suppression of the SOI floating-body effects by linked-body structure,” in 1996 VLSI Symp. on Technology, Dig. Tech. Papers, p. 92. C. T. Nguyen, S. Kuehne, P. Renteln, and S. Wong, “Quasi-SOI using selective epitaxy and polishing,” in Int. Electron Devices Meet. Tech. Dig., 1992, pp. 341–344. M. Chan et al., “Comparative study of fully-depleted and body-grounded non fully-depleted SOI MOSFET’s for high performance analog and mixed signal circuits,” IEEE Trans. Electron Devices, vol. 42, no. 11, pp. 1975–1981, Nov. 1995. F. Assaderaghi, S. Parke, D. Sinitsky, J. Bokor et al., “A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation,” IEEE Electron Device Lett., vol. 15, pp. 510–512, Dec. 1994. PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997 [45] K. Ismail, J. O. Chu, K. L. Saenger, and B. S. Meyerson, “Modulation-doped -type Si/SiGe with inverted interface,” Appl. Phys. Lett., vol. 65, p. 1248, 1994. [46] K. Ismail, J. O. Chu, and B. S. Meyerson, “High hole mobility in SiGe alloys for device applications,” Appl. Phys. Lett., vol. 64, pp. 3124–3126, 1994. [47] K. Ismail, “Si/SiGe high-speed field-effect transistors,” in IEDM Tech. Dig., 1995, p. 509. [48] F. H. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, “Very small MOSFET’s for low temperature operation,” IEEE Trans. Electron Devices, vol. ED-24, p. 218, 1977. [49] J. Y.-C. Sun, Y. Taur, R. H. Dennard, and S. P. Klepner, “Submicrometer-channel CMOS for low-temperature operation,” IEEE Trans. Electron Devices, vol. ED-34, p. 19, 1987. [50] Y. Taur, S. Cohen, S. Wind, T. Lii, C. Hsu, D. Quinlan, C. Chang, D. Buchanan, P. Agnello, Y. Mii, C. Reeves, A. Acovic, and V. Kesan, “Experimental 0.1- m p-channel MOSFET with + polysilicon gate on 35-Å gate oxide,” IEEE Electron Device Lett., vol. 14, p. 304, 1993. [51] D. Frank, S. Laux, and M. Fischetti, “Monte Carlo simulation of a 30 nm dual-gate MOSFET: How far can Si go?,” in 1992 IEDM Tech. Dig., p. 553. [52] , “Monte Carlo simulations of - and -channel dualgate MOSFET’s at the limits of scaling,” IEEE Trans. Electron Devices, vol. 40, p. 2103, 1993. [53] S. Laux, M. Fischetti, and D. Frank, “Monte Carlo analysis of semiconductor devices: The DAMOCLES program,” IBM J. Res. Devel., vol. 34, p. 466, 1990. [54] J. Colinge, M. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around device,” in 1990 IEDM Tech. Dig., p. 595. [55] T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, “Ultrafast lowpower operation of + - + double-gate SOI MOSFET’s,” in 1994 VLSI Technology Symp. Tech. Dig., p. 11. [56] H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, “High performance CMOS surrounding gate transistor (SGT) for ultra high density LSI’s,” in 1988 IEDM Tech. Dig., p. 222. [57] D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, “A fully depleted lean-channel transistor (DELTA)—A novel vertical ultra thin SOI MOSFET,” in 1989 IEDM Tech. Dig., p. 833. [58] H.-S. Wong, D. Frank, Y. Taur, and J. Stork, “Design and performance considerations for sub-0.1 m double-gate SOI MOSFET’s,” in 1994 IEDM Tech. Dig., p. 747. Yuan Taur (Senior Member, IEEE) was born in Jiangxi, China. He received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, in 1967 and the Ph.D. degree in physics from the University of California, Berkeley, in 1974. From 1975 to 1979, he worked at NASA, Goddard Institute for Space Studies, NY, on low-noise Josephson junction mixers for millimeter-wave detection. From 1979 to 1981, he worked at Rockwell International Science Center, Thousand Oaks, CA, on II–VI semiconductor devices for infrared sensor applications. Since 1981, he has been with the Silicon Technology Department of the IBM Thomas J. Watson Research Center, Yorktown Heights, NY. He is presently Manager of Exploratory Devices and Processes. His recent work/publications include: latchup-free 1-m CMOS and BiCMOS, shallow trench isolation, 0.25-m CMOS with n+ =p+ poly gates, SOI, low-temperature CMOS, and 0.1-m CMOS. He has authored or co-authored over 90 technical papers and holds four U.S. patents. Dr. Taur received four outstanding Technical Achievement Awards and three Invention Achievement Awards during his IBM career. He has served on the technical program committees and as panelist for the Device Research Conference, International Electron Device Meeting, and as Rump Session Chairman and Secretary at the Symposium on VLSI Technology. TAUR et al.: CMOS SCALING INTO THE NANOMETER REGIME Douglas A. Buchanan (Member, IEEE) received the B.Sc. and M.Sc. degrees in electrical engineering from the University of Manitoba, Winnipeg, Canada, in 1981 and 1982, respectively. In 1986, he received the Ph.D. degree from Durham University, Durham, U.K. Following a two-year Post-Doctoral Fellowship at IBM’s Thomas J. Watson Reaearch Center, Yorktown Heights, NY, he spent three years in the CVD thin-film technology group in the IBM Microelectronics Division. He currently works on issues pertaining to grown and characterization of ultra-thin dielectrics at the Thomas J. Watson Research Center. Wei Chen (Member, IEEE) received the B.S. degree from the University of Science and Technology of China in 1986 and the M.S. and Ph.D. degrees in physics from Brown University, Providence, RI, in 1988 and 1992, respectively. From 1986 to 1992, he was a Graduate Research Associate working on optoelectronics in GaAs-based HEMT’s at Brown University. He then became a Post-Doctoral Fellow at the University of Rochester, Rochester, NY, working on nanocrystals spectroscopy. During 1993, he worked on terahertz laser ultrasonics in semicondutor nanostructures at Brown University. He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, in 1994. Since then, he has been working on single-electron devices, 10th-m CMOS, SOI CMOS, and CMOS microprocessor design. David J. Frank (Member, IEEE) received the B.S. degree from the California Institute of Technology, Pasadena, in 1977 and the Ph.D. degree in physics from Harvard University, Cambridge, MA, in 1983. Since graduation, he has been at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, where he is a Research Staff Member. His research has included nonequilibrium superconductivity, modeling and measuring III–V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low-power circuit design. His interests include superconductor and semiconductor device physics, modeling and measurement, circuit design, and percolation in two-dimensional systems. Khalid E. Ismail received the B.Sc. and M.Sc. degrees from Cairo University, Egypt, in 1982 and 1985, respectively. He received the Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, in 1989. From 1989 to 1990 he was a Post-Doctoral Fellow at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, and from 1990 to 1995 he held an Assistant Professor, then an Associate Professor, position at Cairo University. Since 1991, he has been conducting research at IBM in the field of Si/SiGe and is currently leading the effort in high-speed Si/SiGe devices at the IBM Thomas J. Watson Research Center. He has conducted research in various areas, such as numerical modeling of semiconductor devices, microwave amplifiers and oscillators, nanofabrication and quantum-effect devices, and Si/SiGe n-type and p-type modulation-doped structures and devices. He has published and presented over 120 papers since 1982 in the above areas, holds four patents, and is the recipient of the IBM Outstanding Achievement Award and the Eta Kappa Nu Outstanding Young Electrical Engineer. 503 Shih-Hsien Lo was born in Taiwan, R.O.C., in 1964. He received the B.S. degree in electrical engineering from National Cheng-Kung University in 1986 and the M.S. and Ph.D. degrees in electronics from National Chiao-Tung University in 1988 and 1991, respectively. After serving two years in the military, he joined National Nano Device Laboratory, Taiwan, as an Associate Researcher in 1993. He has been doing his post-doctoral research at the Exploratory Devices and Circuits Group of the Silicon Technology Department at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, since 1995. His research interests are in the areas of ultra-thin-oxide reliability characterization and numerical modeling and electrical characterization of Si-based small geometry devices. George A. Sai-Halasz (Fellow, IEEE) graduated in physics from the Eotvos Lorand University, Budapest, Hungary, in 1966. He received the Ph.D. degree in physics from Case Western Reserve University, Cleveland, OH, in 1972. Over the next two years, he held a PostDoctoral Fellowship at the Physics Department of the University of Pennsylvania, Philadelphia. He joined the IBM Thomas J. Watson Research Center in 1974. He has made seminal experimental/theoretical contributions in field ranging from basic science to technology. He contributed to quantum solids, nonequilibrium superconductivity, and the physics and device aspects of semiconductor lattices. He was one of the originators and primary theoretical exponent of the Type II superlattice system. He invented and developed a statistical modeling scheme for predicting radiation-induced soft-error rates in VLSI circuits. He was the manager and technical leader of the first successful effort to demonstrate 1-m and below FET technology feasibility. His current interests are in the areas of systems and high-end CMOS processor design. Dr. Sai-Halasz was co-recipient of the 1997 IEEE Cledo Brunetti Award. Raman G. Viswanathan, photograph and biography not available at the time of publication. 504 Hsing-Jen C. Wann, photograph and biography not available at the time of publication. Shalom J. Wind (Member, IEEE) received the B.A. degree in physics from Yeshiva University, NY, and the M.Phil. and Ph.D. degrees in physics from Yale University, New Haven, CT, where he studied electron quantum transport in metallic nanostructures. He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, following his doctoral studies in 1987. There, he has worked on high-resolution electron beam patterning and the study of nanostructures and nanodevices. His current work focuses on nanolithography and the exploration of the limits of silicon device fabrication. Hon-Sum Wong received the B.Sc. degree (Hon.) degree in electrical engineering from the University of Hong Kong, Hong Kong, in 1982, the M.S. degree in electrical engineering from the State University of New York, Stony Brook, NY, in 1983, and the Ph.D. degree in electrical engineering from Lehigh University, Bethlehem, PA, in 1988. He joined the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, in 1988. From 1988 to 1992, he worked on the design, fabrication, and characterization of a high-resolution, high colorfidelity CCD image scanner for art work archiving and multimedia applications. These scanners are now in use at museums around the world, including the Vatican Library and the National Gallery of Art (Washington, D.C.). Since 1993, he has been working on exploratory devices and processes for sub-100-nm CMOS and CMOS image sensors. His recent work included simulations of discrete random dopant effects in small MOSFET’s, hot-electron-induced photon emission, silicon CMOS projection displays, and CMOS image sensors. His research interests have been in electron device physics, device simulation and modeling, microelectronics fabrication technology, and solid-state imagers. PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997