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Download LTC5586 - 6GHz High Linearity I/Q
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LTC5586 6GHz High Linearity I/Q Demodulator with Wideband IF Amplifier DESCRIPTION FEATURES 300MHz to 6GHz Operating Frequency nn Wide IF Bandwidth: DC to 1GHz (–1dB Bandwidth) nn High Mixer IIP3: 30dBm at 1.9GHz nn High Total OIP3: 40dBm at 1.9GHz nn High Total OIP2: 74dBm at 1.9GHz nn User Adjustable OIP2 to 80dBm nn User Adjustable Image Rejection to 60dB nn User Adjustable DC Offset Null nn Serial Interface nn Power Conversion Gain: 7.7dB at 1.9GHz nn 31dB RF Attenuator with 1dB Step Size nn RF Switch with 40dB Isolation at 1.9GHz nn Single-Ended RF Inputs with On-Chip Transformer nn IF Amplifier Gain Adjustable in 8 Steps nn Operating Temperature Range (T ): –40°C to 105°C C nn 32-Lead 5mm × 5mm QFN Package The LTC®5586 is a direct conversion quadrature demodulator optimized for high linearity zero-IF and low-IF receiver applications in the 300MHz to 6GHz frequency range. The very wide IF bandwidth of more than 1GHz makes the LTC5586 particularly suited for demodulation of very wide-band signals, especially in Digital Pre-Distortion (DPD) applications. The outstanding dynamic range of the LTC5586 makes the device suitable for demanding infrastructure direct conversion applications. Proprietary technology inside the LTC5586 provides the capability to optimize OIP2 to 80dBm, and achieve image rejection better than 60dB. The DC offset control function allows nulling of the DC offset at the A/D converter input, thereby optimizing the dynamic range of true zero-IF receivers that use DC coupled IF signal paths. The wide-band RF and LO input ports make it possible to cover all the major wireless infrastructure frequency bands using a single device. The IF outputs of the LTC5586 are designed to interface directly with most common A/D converter input interfaces. The high OIP3 and high conversion gain of the device eliminate the need for additional amplifiers in the IF signal path. nn APPLICATIONS 4G and 5G Base Station Receivers Wideband DPD Receivers nn Point-To-Point Broadband Radios nn High Linearity Direct Conversion I/Q Receivers nn Image Rejection Receivers nn nn L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Gain, OIP3 and OIP2 vs Temperature (TC) (Unoptimized) Dual Band Transmitter with DPD Receiver 90 IFIP LTC5586 ADC RFA IFIM 8 STEPS RFB 0º fLO 90º RFSW ATTEN 0dB – 31dB 8 STEPS IFQP SPI 70 60 50 OIP3 40 30 20 GAIN 10 0 ADC IFQM RF2 OIP2 80 PA1 GAIN, OIP3, OIP2 (dB,dBm,dBm) RF1 PA2 5586 TA01 -10 0 1 2 3 4 RF FREQUENCY (GHz) I, 105°C I, 85°C I, 25°C I, –40°C 5 Q, 105°C Q, 85°C Q, 25°C Q, –40°C 6 5586 G01 5586f For more information www.linear.com/LTC5586 1 LTC5586 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) IFIP IFIM DNC AIP AIM DNC MIM MIP TOP VIEW 32 31 30 29 28 27 26 25 GND 1 24 OVDD RFA 2 23 SCK TEMP 3 22 SDI RFSW 4 21 SDO 33 GND VCCN 5 20 LOM VCM 6 19 LOP RFB 7 18 VCC GND 8 17 CSB IFQP IFQM DNC AQP AQM DNC MQM 9 10 11 12 13 14 15 16 MQP VCC, VCCN Supply Voltage (Note 21)........ –0.3V to 5.5V OVDD, SDO Voltage (Note 18).................... –0.3V to 3.8V RFA, RFB DC Voltage....................................1.5V to 2.0V LOP, LOM DC Voltage................................... 2.1V to 2.8V IFIM, IFIP, IFQP, IFQM DC Voltage.............. –0.3V to 3.5V AIM, AIP, AQM, AQP DC Voltage............................ VCC – 1.7V to VCC – 1.2V MIM, MIP, MQM, MQP DC Voltage............................ VCC – 1.7V to VCC – 1.2V Voltage on Any Other Pin........................... –0.3V to 5.5V LOP, LOM, RFA, RFB Input Power (Note 17).......+20dBm Output Short Circuit Duration (Notes 14, 17).... Indefinite Maximum Junction Temperature (TJMAX).............. 150°C Case Operating Temperature Range (TC).– 40°C to 105°C Storage Temperature Range................... –65°C to 150°C UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 150°C, θJC = 7.7°C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION http://www.linear.com/product/LTC5586#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC5586IUH#PBF LTC5586IUH#TRPBF 5586 32-Lead (5mm x 5mm) Plastic QFN –40°C to 105°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 2 5586f For more information www.linear.com/LTC5586 LTC5586 ELECTRICAL CHARACTERISTICS TC = 25°C, VCC = VCCN = 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V, VCM = 0.9V, PIF = 1.5dBm (–1.5dBm/tone for 2-tone tests), PLO = 6dBm, all registers at default values unless otherwise noted. (Notes 2, 3, 6, 9, 19, 22) SYMBOL PARAMETER CONDITIONS fRF(RANGE) RF Input Frequency Range (Note 12) 0.3 to 6.0 GHz fLO(RANGE) LO Input Frequency Range (Note 12) 0.3 to 6.0 GHz RLRF RF Input Return Loss fRF = 300MHz to 500MHz (Note 5) fRF = 500MHz to 6.0GHz >10 >10 dB dB RLLO LO Input Return Loss fLO = 300MHz to 6.0GHz PLO(RANGE) LO Input Power Range (Note 12) GP(MAX) Maximum Power Conversion Gain ATT = 0x00, AMPG = 0x06, RLOAD = 100Ω Differential (Note 8) fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 7.4 9.2 7.7 7.1 4.3 0.7 dB dB dB dB dB dB GP(MIN) Power Conversion Gain at Maximum Attenuation. ATT = 0x1F, AMPG = 0x06, RLOAD = 100Ω, Differential (Note 8) fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz –23.3 –21.3 –21.8 –23.5 –24.0 –23.9 dB dB dB dB dB dB 1.0 dB Attenuation Step Size MIN TYP >10 – 6 to 12 MAX UNITS dB dBm Attenuation Step Accuracy 0.2 dB RFA, RFB Gain Error 0.05 dB RFA, RFB Switching Time 100 ns ABISO RFA, RFB Isolation fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 49 48 40 42 38 25 dB dB dB dB dB dB NF Noise Figure, Double Side Band (Note 4) fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 19.0 17.8 19.5 21.1 23.2 31.0 dB dB dB dB dB dB NFBLOCKING Noise Figure Under Blocking Conditions Double Side Band, PIF, BLOCKER = 1.5dBm (Note 7) fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 19.7 18.9 20.8 22.5 24.8 30.2 dB dB dB dB dB dB OIP3 Output 3rd Order Intercept Unadjusted/Adjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 41/44 42/43 40/42 38/40 35/36 32/33 dBm dBm dBm dBm dBm dBm OIP2 Output 2nd Order Intercept Unadjusted/Adjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 75/80 75/80 74/80 65/80 60/70 49/56 dBm dBm dBm dBm dBm dBm 5586f For more information www.linear.com/LTC5586 3 LTC5586 ELECTRICAL CHARACTERISTICS TC = 25°C, VCC = VCCN = 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V, VCM = 0.9V, PIF = 1.5dBm (–1.5dBm/tone for 2-tone tests), PLO = 6dBm, all registers at default values unless otherwise noted. (Notes 2, 3, 6, 9, 19, 22) SYMBOL PARAMETER CONDITIONS IIP3DEMOD Input 3rd Order Intercept Without Amplifier Unadjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 31 29 30 30 30 32 dBm dBm dBm dBm dBm dBm OIP3AMP Output 3rd Order Intercept, Amplifier Only (Note 15) fIF = 10MHz fIF = 100MHz fIF = 200MHz fIF = 300MHz fIF = 500MHz fIF = 1000MHz 42 41 38 37 35 30 dBm dBm dBm dBm dBm dBm HD2 2nd Order Harmonic Distortion Unadjusted/Adjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz –63/–85 –62/–90 –63/–90 –61/–90 –64/–85 –52/–74 dBc dBc dBc dBc dBc dBc HD3 3rd Order Harmonic Distortion Unadjusted/Adjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz –83/–84 –80/–81 –80/–81 –80/–80 –79/–78 –69/–73 dBc dBc dBc dBc dBc dBc P1dB Output 1dB Compression Point fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 10.5 13 13 13 13 12.5 dBm dBm dBm dBm dBm dBm DCOFFSET DC Offset, Unadjusted (Note 13) fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 20 21 22 25 35 45 mV mV mV mV mV mV –75 to 75 mV DCOFF(RANGE) DC Offset Adjustment Range DCOI, DCOQ = 0x00 to 0xFF DCOFF(STEP) DC Offset Step Size ∆G I/Q Gain Mismatch, Unadjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz ∆G(RANGE) I/Q Gain Mismatch Adjustment Range GERR = 0x00 to 0x3F ∆G(STEP) I/Q Gain Mismatch Adjustment Step Size ∆φ I/Q Phase Mismatch, Unadjusted fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz ∆φ(RANGE) I/Q Phase Mismatch Adjustment Range PHA = 0x000 to 0x1FF 4 MIN TYP MAX UNITS 640 µV 0.04 0.05 0.06 0.06 0.07 0.10 dB dB dB dB dB dB –0.5 to 0.5 dB 0.016 dB 0.4 1.1 1.1 2.3 3.2 0.3 Deg Deg Deg Deg Deg Deg –2.5 to 2.5 Deg 5586f For more information www.linear.com/LTC5586 LTC5586 ELECTRICAL CHARACTERISTICS TC = 25°C, VCC = VCCN = 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V, VCM = 0.9V, PIF = 1.5dBm (–1.5dBm/tone for 2-tone tests), PLO = 6dBm, all registers at default values unless otherwise noted. (Notes 2, 3, 6, 9, 19, 22) SYMBOL PARAMETER ∆φ(STEP) I/Q Phase Mismatch Adjustment Step Size CONDITIONS IRR Image Rejection Ratio Unadjusted/Adjusted (Note 10) LRLEAK MIN TYP MAX UNITS 0.05 Deg fRF = 400MHz fRF = 700MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 51/68 44/70 45/68 39/69 33/70 39/70 dB dB dB dB dB dB LO to RF Leakage fLO = 400MHz fLO = 900MHz fLO = 1900MHz fLO = 2600MHz fLO = 3500MHz fLO = 5800MHz –67 –63 –56 –55 –45 –47 dBm dBm dBm dBm dBm dBm RLISO RF to LO Isolation fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 59 65 66 62 57 52 dB dB dB dB dB dB RIISO RF to IF Isolation (Note 16) fRF = 400MHz fRF = 900MHz fRF = 1900MHz fRF = 2600MHz fRF = 3500MHz fRF = 5800MHz 70 65 50 53 48 47 dB dB dB dB dB dB LILEAK LO to IF Leakage (Note 16) fLO = 400MHz fLO = 900MHz fLO = 1900MHz fLO = 2600MHz fLO = 3500MHz fLO = 5800MHz –37 –36 –34 –33 –42 –36 dBm dBm dBm dBm dBm dBm Power Supply and Other Parameters VCC, VCCN Supply Voltage 4.75 5.0 5.25 V 430 440 470 mA ICC Supply Current IVCCN Supply Current to VCCN Pin OVDD Digital I/O Supply Voltage 700 µA 1.2 to 3.3 V VDH RFSW Input High Voltage (On) VDL RFSW Input Low Voltage (Off) 0.7 • OVDD V IRFSW RFSW Pin Input Current RFSW = 3.3V 1 μA VTEMP TEMP Diode Bias Voltage ITEMP = 100μA into TEMP pin 0.774 V TEMP Diode Temperature Slope ITEMP = 100μA into TEMP pin –1.52 mV/°C 100||0.6 Ω||pF 0.3 • OVDD V ZMIX(OUT) Mixer Output Impedance Differential VMIX(OUT) Mixer Output DC Voltage Common-Mode ZAMP(IN) Amplifier Input Impedance Differential 200||0.2 Ω||pF VAMP(IN) Amplifier DC Input Voltage Common-Mode 3.0 to 4.0 V ZAMP(OUT) Amplifier Output Impedance Differential IAMP(SC) Amplifier DC Output Short Circuit Current IFIP = IFIM = IFQP = IFQM = 0V VCM(RANGE) VCM Pin Voltage Range (Notes 11, 12) 3.7 4||0.5 100 0.5 to 2.0 V kΩ||pF mA V 5586f For more information www.linear.com/LTC5586 5 LTC5586 ELECTRICAL CHARACTERISTICS TC = 25°C, VCC = VCCN = 5V, OVDD = CSB = RFSW = 3.3V, SDI = SCK = 0V, VCM = 0.9V, PIF = 1.5dBm (–1.5dBm/tone for 2-tone tests), PLO = 6dBm, all registers at default values unless otherwise noted. (Notes 2, 3, 6, 9, 19, 22) SYMBOL PARAMETER CONDITIONS BWIF IF Output Bandwidth –1dB Corner Frequency (Note 20) MIN TYP MAX 1.0 UNITS GHz Serial Interface Pins VIH High Level Input Voltage CSB, SDI, SCK VIL Low Level Input Voltage CSB, SDI, SCK VIHYS Input Hysteresis Voltage CSB, SDI, SCK IIN(SER) Input Current CSB, SDI, SCK (Note 17) VOH High Level Output Voltage SDO, 10mA Current Sink VOL Low Level Output Voltage SDO, 10mA Current Source 0.7 • OVDD V 0.3 • OVDD 250 V mV 30 0.7 • OVDD μA V 0.3 • OVDD V Serial Interface Timing tCKH SCK High Time 25 ns tCKL SCK Low Time 25 ns tCSS CSB Setup Time 10 ns tCSH CSB High Time 10 ns tDS SDI to SCK Setup Time 6 ns tDH SDI to SCK Hold Time tDO SCK to SDO Time 6 To VIH/VIL/Hi-Z with 30pF Load Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. The voltage on all pins should not exceed VCC + 0.3V or be less than –0.3V, otherwise damage to the ESD diodes may occur. Note 2: Tests are performed with the test circuit of Figure 1. Note 3: The LTC5586 is guaranteed to be functional over the –40°C to 105°C case temperature operating range. Note 4: DSB noise figure is measured at the baseband frequency of 15MHz with a small-signal noise source without any filtering on the RF input and no other RF signal applied. Note 5: A 4.7pF shunt capacitor is used on the RF inputs for 300MHz to 500MHz. 0.3pF is used for 500MHz to 6GHz. Note 6: The differential amplifier outputs (IFIP, IFIM and IFQP, IFQM) are combined using a 180° combiner. Note 7: Noise figure under blocking conditions (NFBLOCKING) is measured at an output frequency of 60MHz with RF input signal at fLO + 1MHz. Both RF and LO input signals are appropriately filtered, as well as the baseband output. Note 8: Power conversion gain is measured with a 100Ω differential load impedance on the I and Q outputs. Any losses due to IF combiner and spectrum analyzer termination have been de-embedded. Note 9: Input PRF adjusted so that PIF = –1.5dBm/tone at the amplifier output. RF tone spacing set at 4MHz with high-side LO, fLO = fRF + 30MHz. 6 ns 16 ns Note 10: Image rejection is measured at fIF = 12MHz and calculated from the measured gain error and phase error. Note 11: If the VCM pin is left floating, it will self bias to a nominal 0.9V. Note 12: This is the recommended operating range, operation outside the listed range is possible with degraded performance to some parameters. Note 13: DC offset measured differentially between IFIP and IFIM and between IFQP and IFQM. The reported value is the mean of the absolute values of the characterization data distribution. Note 14: IF outputs shorted to ground. Note 15: IF tone spacing set at 1MHz. Note 16: Worst case leakage or isolation measured to each IF single-ended port. Note 17: Guaranteed by design characterization, not tested in production. Note 18: The voltage on the OVDD pin must never exceed VCC + 0.3V, otherwise damage to the ESD diodes may occur. Note 19: Refer to Appendix for register definition and default values. Note 20: Mixer outputs directly connected to amplifier inputs. Bandwidth measured on single amplifier output, I or Q. Note 21: VCC should be ramped up slower than 5V/ms to prevent damage. Note 22: PIF measured at amplifier differential outputs. 5586f For more information www.linear.com/LTC5586 LTC5586 V TYPICAL PERFORMANCE CHARACTERISTICS CC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. TEMP Diode Voltage Noise Figure and Conversion Supply Current vs Supply Voltage vs Temperature (TC) Gain vs Temperature (TC) 470 40 460 450 440 430 420 0.9 30 25 0.8 0.7 0.6 5.00 SUPPLY VOLTAGE (V) 0.5 -40 5.25 -20 0 20 40 60 80 TEMPERATURE (°C) -10 100 120 GAIN 35 30 5 NF GAIN (dB) 20 15 10 GAIN 5 5 –5 –10 –15 1 2 3 4 RF FREQUENCY (GHz) 5 –30 6 15 LSLO -25 ATT = 31 0 1 2 3 4 RF FREQUENCY (GHz) 5 -30 6 Gain vs AMPG Register Value 60 fRF = 1900MHz 10 5 -20 -25 0 0 5586 G08 –15 40 35 30 0 1 2 3 –10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IF FREQUENCY (GHz) ATT = 31 45 –5 Q, 400MHz Q, 900MHz Q, 1900MHz Q, 2600MHz Q, 3500MHz Noise Figure vs ATT Setting 50 NF (dB) GAIN (dB) I, 400MHz I, 900MHz I, 1900MHz I, 2600MHz I, 3500MHz -15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IF FREQUENCY (GHz) 55 5 -10 0 Q, 400MHz Q, 900MHz Q, 1900MHz Q, 2600MHz Q, 3500MHz Q, 5800MHz 5586 G07 10 -5 I, 400MHz I, 900MHz I, 1900MHz I, 2600MHz I, 3500MHz I, 5800MHz 5586 G06 Gain vs RF Frequency for LSLO 0 -10 -20 5586 G05 15 0 -5 -15 –25 –5 6 10 –20 0 0 5 15 ATT = 0 0 25 2 3 4 RF FREQUENCY (GHz) 20 GAIN (dB) –6dBm 0dBm 6dBm 12dBm 1 Gain vs RF Frequency 10 40 0 5586 G04 Conversion Gain vs ATT Setting 45 GAIN, NF (dB) 10 5586 G03 Noise Figure and Conversion Gain vs LO Power GAIN (dB) 15 0 5586 G02 -30 20 -5 400 4.75 20 NF 5 410 –10 105°C 85°C 25°C –40°C 35 TEMP DIODE VOLTAGE (V) 480 SUPPLY CURRENT (mA) 1.0 TC = 105°C TC = 85°C TC = 25°C TC = –40°C 490 GAIN, NF (dB) 500 0 4 5 6 7 25 ATT = 0 20 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IF FREQUENCY (GHz) 5586 G09 15 0 1 2 3 4 RF FREQUENCY (GHz) 5 6 5586 G10 5586f For more information www.linear.com/LTC5586 7 LTC5586 TYPICAL PERFORMANCE CHARACTERISTICS VCC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. RFA to RFB Isolation vs RFSW RFSW = 1 RFSW = 0 -10 -20 16 -30 15 -40 14 -50 -60 11 10 -90 9 1 2 3 4 5 6 RF FREQUENCY (GHz) 7 8 8 45 40 12 -80 0 RFA RFB 13 -70 -100 OIP3 vs IF Frequency 50 17 P1dB (dBm) -ISOLATION (dB) Output Referred P1dB 18 OIP3 (dBm) 0 20 0 1 2 3 4 RF FREQUENCY (GHz) 5 LSLO OIP3 vs Temperature (TC) 50 40 40 40 I, 30MHz I, 100MHz I, 200MHz I, 300MHz I, 500MHz 20 15 0 1 Q, 30MHz Q, 100MHz Q, 200MHz Q, 300MHz Q, 500MHz 2 3 4 RF FREQUENCY (GHz) OIP3 (dBm) 45 30 35 30 25 I, 105°C I, 85°C I, 25°C I, –40°C 20 5 15 6 0 1 2 3 4 RF FREQUENCY (GHz) 5 15 6 40 40 40 1 2 3 4 RF FREQUENCY (GHz) 5 OIP3 (dBm) 45 OIP3 (dBm) 45 0 35 30 25 5586 G17 1 2 3 4 RF FREQUENCY (GHz) 5 I, –4.5dBm I, –1.5dBm I, 1.5dBm 15 0 1 6 35 30 OPTIMIZED AT 25°C 25 20 6 0 Q, 4.75V Q, 5V Q, 5.25V Optimized OIP3 vs Temperature (TC) 45 15 I, 4.75V I, 5V I, 5.25V 5586 G16 50 20 OIP3 vs Supply Voltage (VCC) 20 OIP3 vs IF Tone Power Q, –6dBm Q, 0dBm Q, 6dBm Q, 12dBm 6 30 50 I, –6dBm I, 0dBm I, 6dBm I, 12dBm 5 35 50 25 2 3 4 RF FREQUENCY (GHz) 5586 G15 OIP3 vs LO Power 30 1 25 Q, 105°C Q, 85°C Q, 25°C Q, –40°C 5586 G14 35 0 Q, 30MHz Q, 100MHz Q, 200MHz Q, 300MHz Q, 500MHz 5586 G13 45 25 OIP3 (dBm) 15 6 45 OIP3 (dBm) OIP3 (dBm) 50 35 I, 30MHz I, 100MHz I, 200MHz I, 300MHz I, 500MHz 5586 G12 OIP3 vs IF Frequency for LSLO 8 30 25 5586 G11 50 35 Q, –4.5dBm Q, –1.5dBm Q, 1.5dBm 2 3 4 RF FREQUENCY (GHz) 5 I, 105°C I, 85°C I, 25°C I, –40°C 20 6 5586 G18 15 0 1 2 3 4 RF FREQUENCY (GHz) Q, 105°C Q, 85°C Q, 25°C Q, –40°C 5 6 5586 G19 5586f For more information www.linear.com/LTC5586 LTC5586 TYPICAL PERFORMANCE CHARACTERISTICS VCC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. OIP3 vs Temperature (TC) and Register Value, I-Channel 50 OIP3 vs Temperature (TC) and Register Value, Q-Channel 50 I-CHANNEL fRF = 1900MHz 45 30 25 IM3IY, 105°C IM3IY, 85°C IM3IY, 25°C IM3IY, –40°C 20 0 32 40 OIP3 (dBm) OIP3 (dBm) OIP3 (dBm) 45 40 35 15 Q-CHANNEL fRF = 1900MHz 45 40 35 30 25 IM3IX, 105°C IM3IX, 85°C IM3IX, 25°C IM3IX, –40°C IM3QY, 105°C IM3QY, 85°C IM3QY, 25°C IM3QY, –40°C 20 15 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) 0 32 45 40 40 25 20 0 1 Q, 0 Q, 1 Q, 2 Q, 3 Q, 4 Q, 5 Q, 6 Q, 7 I, 0 I, 1 I, 2 I, 3 I, 4 I, 5 I, 6 I, 7 30 0 1 Q, 0 Q, 1 Q, 2 Q, 3 Q, 4 Q, 5 Q, 6 Q, 7 2 3 4 RF FREQUENCY (GHz) 50 40 30 10 5 0 6 90 80 80 80 70 70 70 60 60 60 0 0 1 2 3 4 RF FREQUENCY (GHz) OIP2 (dBm) 40 I, 105°C I, 85°C I, 25°C I, –40°C 10 6 5586 G26 2 3 4 RF FREQUENCY (GHz) 5 0 0 1 2 3 4 RF FREQUENCY (GHz) 6 I-CHANNEL fRF = 1900MHz 90 50 20 5 100 OPTIMIZED AT 25°C 30 10 1 OIP2 vs Temperature (TC) and Register Value, I-Channel 90 Q, –6dBm Q, 0dBm Q, 6dBm Q, 12dBm 0 Q, 105°C Q, 85°C Q, 25°C Q, –40°C 5586 G25 100 I, –6dBm I, 0dBm I, 6dBm I, 12dBm I, 105°C I, 85°C I, 25°C I, –40°C 20 Optimized OIP2 vs Temperature (TC) OIP2 (dBm) OIP2 (dBm) 60 100 20 6 OIP2 vs Temperature (TC) 5586 G24 OIP2 vs LO Power 30 5 70 5586 G23 40 2 3 4 RF FREQUENCY (GHz) 80 35 15 6 50 1 90 20 5 0 Q, 0 Q, 1 Q, 2 Q, 3 5586 G22 100 25 2 3 4 RF FREQUENCY (GHz) 15 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) OIP2 (dBm) 45 35 I, 0 I, 1 I, 2 I, 3 20 OIP3 vs LVCM Register Value 50 OIP3 (dBm) OIP3 (dBm) OIP3 vs IP3IC Register Value I, 0 I, 1 I, 2 I, 3 I, 4 I, 5 I, 6 I, 7 30 5586 G21 50 30 35 25 IM3QX, 105°C IM3QX, 85°C IM3QX, 25°C IM3QX, –40°C 5586 G20 15 OIP3 vs IP3CC Register Value 50 40 30 Q, 105°C Q, 85°C Q, 25°C Q, –40°C 5 50 IM2IX, 105°C IM2IX, 85°C IM2IX, 25°C IM2IX, –40°C 20 10 6 5586 G27 0 0 32 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) 5586 G28 5586f For more information www.linear.com/LTC5586 9 LTC5586 TYPICAL PERFORMANCE CHARACTERISTICS VCC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. OIP2 vs Temperature (TC) and Register Value, Q-Channel Q-CHANNEL fRF = 1900MHz 90 80 –20 70 –30 60 –40 50 40 30 IM2QX, 105°C IM2QX, 85°C IM2QX, 25°C IM2QX, –40°C 20 10 0 0 32 HD2 vs Temperature (TC) I, 105°C I, 85°C I, 25°C I, –40°C –10 HD2 (dBc) OIP2 (dBm) 0 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) HD2 vs LO Power 0 Q, 105°C Q, 85°C Q, 25°C Q, –40°C –20 –30 –50 –60 –80 –90 –90 –100 –100 2 3 4 RF FREQUENCY (GHz) 5 –20 –30 HD2 vs Temperature (TC) and Register Value, I-Channel 0 Q, 105°C Q, 85°C Q, 25°C Q, –40°C –20 HD2 (dBc) HD2 (dBc) –50 –60 –30 –40 –50 –60 –80 –80 –90 –90 –100 –100 2 3 4 RF FREQUENCY (GHz) 5 6 HD2IY, 105°C HD2IY, 85°C HD2IY, 25°C HD2IY, –40°C 0 32 –20 0 Q, 105°C Q, 85°C Q, 25°C Q, –40°C 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) I, –6dBm I, 0dBm I, 6dBm I, 12dBm –10 –20 –30 –40 –50 –60 0 Q, –6dBm Q, 0dBm Q, 6dBm Q, 12dBm –30 –40 –50 –60 –50 –60 –70 –80 –90 –90 –90 5 6 5586 G35 10 –100 0 1 2 3 4 RF FREQUENCY (GHz) 5 6 5586 G36 Q, 105°C Q, 85°C Q, 25°C Q, –40°C –40 –80 2 3 4 RF FREQUENCY (GHz) 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) OPTIMIZED AT 25°C I, 105°C I, 85°C I, 25°C I, –40°C –20 –70 1 32 Optimized HD3 vs Temperature (TC) –10 –80 0 0 HD2QX, 105°C HD2QX, 85°C HD2QX, 25°C HD2QX, –40°C 5586 G34 –70 –100 HD2QY, 105°C HD2QY, 85°C HD2QY, 25°C HD2QY, –40°C –90 –100 HD3 vs LO Power HD3 (dBc) HD3 (dBc) –30 –60 –80 HD3 (dBc) I, 105°C I, 85°C I, 25°C I, –40°C 6 –50 5586 G33 HD3 vs Temperature (TC) 0 5 Q-CHANNEL fRF = 1900MHz –70 HD2IX, 105°C HD2IX, 85°C HD2IX, 25°C HD2IX, –40°C 5586 G32 –10 2 3 4 RF FREQUENCY (GHz) –20 –40 –70 1 0 –10 –30 –70 0 1 HD2 vs Temperature (TC) and Register Value, Q-Channel I-CHANNEL fRF = 1900MHz –10 –40 0 5586 G31 HD2 (dBc) OPTIMIZED AT 25°C I, 105°C I, 85°C I, 25°C I, –40°C 6 5586 G30 Optimized HD2 vs Temperature (TC) 0 –60 –70 5586 G29 –10 –50 –80 1 Q, –6dBm Q, 0dBm Q, 6dBm Q, 12dBm –40 –70 0 I, –6dBm I, 0dBm I, 6dBm I, 12dBm –10 HD2 (dBc) 100 –100 0 1 2 3 4 RF FREQUENCY (GHz) 5 6 5586 G37 5586f For more information www.linear.com/LTC5586 LTC5586 TYPICAL PERFORMANCE CHARACTERISTICS VCC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. HD3 vs Temperature (TC) and Register Value, I-Channel –20 –20 –30 –40 –50 –60 –60 –70 –80 –100 0 32 –100 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) 0 32 0 105°C 85°C 25°C –40°C 1.0 OPTIMIZED AT 25°C –50 –60 –70 0 –0.2 –0.4 –90 –0.8 5 –1.0 6 105°C 85°C 25°C –40°C 0 8 16 24 32 40 48 56 REGISTER VALUE (INTEGER) DC Offset vs Temperature (TC) –2 –3 20 64 128 192 256 320 384 448 512 REGISTER VALUE (INTEGER) DC OFFSET (mV) 5 0 –5 –10 –30 Optimized DC Offset vs Temperature (TC) OPTIMIZED AT 25°C 10 10 0 1 2 3 4 LO FREQUENCY (GHz) 5 0 –5 –10 –6dBm 0dBm 6dBm 12dBm –25 5586 G44 0 15 15 6 105°C 85°C 25°C –40°C 5586 G43 20 5 –1 –5 64 25 –20 2 3 4 LO FREQUENCY (GHz) 6 0 –4 30 –15 1 5 1 DC Offset vs LO Power 105°C 85°C 25°C –40°C 0 2 3 4 LO FREQUENCY (GHz) 5586 G42 DC OFFSET (mV) DC OFFSET (mV) 5586 G41 50 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 –20 1 fRF = 1900MHz 2 0.2 –0.6 2 3 4 RF FREQUENCY (GHz) 3 0.4 –80 1 0 Phase Error vs Temperature (TC) and PHA Register Value 0.6 –40 0 –50 5586 G40 fRF = 1900MHz 0.8 –30 –100 –40 Gain Error vs Temperature (TC) and GERR Register Value GAIN ERROR (dB) –IMAGE REJECTION (dB) –20 –30 5586 G39 Optimized Image Rejection vs Temperature (TC) –10 –20 –70 64 96 128 160 192 224 256 REGISTER VALUE (INTEGER) 5586 G38 105°C 85°C 25°C –40°C –60 Q-CHANNEL fRF = 1900MHz –90 Image Rejection vs Temperature (TC) –10 –50 –80 I-CHANNEL fRF = 1900MHz HD3QX, 105°C HD3QX, 85°C HD3QX, 25°C HD3QX, –40°C –40 –70 –90 0 HD3QY, 105°C HD3QY, 85°C HD3QY, 25°C HD3QY, –40°C –10 HD3 (dBc) HD3 (dBc) –30 0 HD3IX, 105°C HD3IX, 85°C HD3IX, 25°C HD3IX, –40°C –IMAGE REJECTION (dB) HD3IY, 105°C HD3IY, 85°C HD3IY, 25°C HD3IY, –40°C PHASE ERROR (DEGREES) 0 –10 HD3 vs Temperature (TC) and Register Value, Q-Channel 105°C 85°C 25°C –40°C –15 5 6 5586 G45 –20 0 1 2 3 4 LO FREQUENCY (GHz) 5 6 5586 G46 5586f For more information www.linear.com/LTC5586 11 LTC5586 TYPICAL PERFORMANCE CHARACTERISTICS VCC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. DC Offset vs Temperature (TC) and Register Value 100 Blocking Noise Figure vs LO Power 40 fLO = 1900MHz 80 –6dBm 0dBm 6dBm 12dBm RFSW IFIP IFIM 20 1.5 15 1.0 10 0.5 5 NF (dB) 0 –20 IFIP, IFIM (V) 30 20 25 20 –40 105°C 85°C 25°C –40°C –60 –80 0 32 15 10 –30 64 96 128 160 192 224 256 DC OFFSET DAC (INTEGER) –25 –20 –15 –10 –5 RF INPUT POWER (dBm) 5586 G47 –ISOLATION (dB) 60 IIP3 40 30 20 10 –40 –40 –45 –45 –50 –55 –60 –65 –75 0 1 2 3 4 RF FREQUENCY (GHz) 5 5586 G50 TC = 25°C RFSW = 1 RFA INPUT –10 –30 –80 0 1 2 3 4 LO FREQUENCY (GHz) 5 6 5586 G52 LO to IF Isolation 0 IFQP IFQM IFIM IFIP –40 –50 –60 –70 –80 IFQP IFQM IFIM IFIP TC = 25°C BAND = 1 CF = 0 LF1 = 0 CF2 = 0 –10 –ISOLATION (dB) –ISOLATION (dB) –20 6 5586 G51 RF to IF Isolation 0 0 10 –65 –80 6 9 –60 –20 5 8 –55 –70 2 3 4 RF FREQUENCY (GHz) 7 –50 –75 GAIN 1 4 5 6 TIME (µs) RFA RFB –35 –10 0 3 LO to RF Leakage –70 0 2 –30 RFA RFB –35 50 1 5586 G49 LEAKAGE (dBm) 70 0 RF to LO Isolation –30 I Q IIP2 80 0 0 5586 G48 Gain, IIP3 and IIP2 for Mixer Only 90 GAIN, IIP3, IIP2 (dB,dBm,dBm) fRF = 2.1GHz fLO = 2.102GHz RFSW (V) DC OFFSET (mV) 40 –100 fLO = 1900MHz fRF, BLOCK = 1960MHz fIF, NOISE = 30MHz 35 60 RFSW Transient Response 2.0 –20 –30 –40 –50 –90 –100 0 1 2 3 4 5 6 RF FREQUENCY (GHz) 7 8 –60 0 1 5586 G53 12 2 3 4 5 6 LO FREQUENCY (GHz) 7 8 5586 G54 5586f For more information www.linear.com/LTC5586 LTC5586 TYPICAL PERFORMANCE CHARACTERISTICS VCC = VCCN = 5V, TC = 25°C, PLO = 6dBm, HSLO, RF tone spacing = 4MHz, fIF = 30MHz, PIF = –1.5dBm per tone, and register defaults. DC Blocks, 50Ω terminations, and MACOM H9 180° combiner at amplifier outputs de-embedded from measurement unless otherwise noted. Test circuit shown in Figure 1 with 500MHz interstage filter. OIP2 Distribution vs Temperature (TC) 100 fRF = 2GHz 60 I, 105°C I, 85°C I, 25°C I, –40°C Q, 105°C Q, 85°C Q, 25°C Q, –40°C 40 20 0 100 fRF = 2GHz 80 PERCENTAGE (%) 30 32 34 60 I, 105°C I, 85°C I, 25°C I, –40°C Q, 105°C Q, 85°C Q, 25°C Q, –40°C 40 20 36 38 OIP3 (dBm) 40 0 42 30 40 50 5586 G55 100 fRF = 2GHz PERCENTAGE (%) I, 105°C I, 85°C I, 25°C I, –40°C Q, 105°C Q, 85°C Q, 25°C Q, –40°C 20 0 60 70 OIP2 (dBm) 80 90 10 12 14 20 22 24 100 fRF = 2GHz 60 40 105°C 85°C 25°C –40°C 6.5 7.0 7.5 GAIN (dB) 8.0 0 –0.20 –0.15 –0.10 –0.05 GAIN ERROR (dB) 60 40 105°C 85°C 25°C –40°C 0 0 0 0.5 1.0 1.5 PHASE ERROR (dB) 2.0 5586 G60 Optimized Image Rejection vs IF Frequency fRF = 2GHz 80 60 40 105°C 85°C 25°C –40°C –45 –40 –35 –IMAGE REJECTION (dB) 9.0 fRF = 2GHz 5586 G59 20 8.5 Phase Error Distribution vs Temperature (TC) 20 Image Rejection Distribution vs Temperature (TC) 0 –50 6.0 80 5586 G58 100 5.5 5586 G57 Gain Error Distribution vs Temperature (TC) 20 16 18 NF (dB) 105°C 85°C 25°C –40°C 0 5.0 100 80 PERCENTAGE (%) PERCENTAGE (%) 80 40 40 5586 G56 Noise Figure Distribution vs Temperature (TC) 60 60 20 PERCENTAGE (%) 100 fRF = 2GHz 80 –30 –IMAGE REJECTION (dB) PERCENTAGE (%) 80 Conversion Gain Distribution vs Temperature (TC) PERCENTAGE (%) 100 OIP3 Distribution vs Temperature (TC) 0 OPTIMIZED AT fRF = 1750MHz –10 FIXED fLO = 1900MHz WITHOUT INTERSTAGE FILTER –20 TC = 55°C –30 –40 –50 –60 –70 HSLO, DEFAULT LSLO, DEFAULT HSLO, OPTIMIZED LSLO, OPTIMIZED –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IF FREQUENCY (GHz) 5586 G61 5586 G62 5586f For more information www.linear.com/LTC5586 13 LTC5586 PIN FUNCTIONS RFA (Pin 2): 50Ω switched RF input. The pin should be DCblocked with coupling capacitor; 1000pF is recommended. is set by a resistance of 25Ω to 200Ω from each pin to ground and the VCM control voltage. TEMP (Pin 3): Temperature monitoring diode. The diode to ground at this pin can be used to measure the die temperature. A forward bias current of 100µA can be used into this pin and the forward voltage drop can be measured as a function of die temperature. CSB (Pin 17): Chip Select Bar. When CSB is low, the serial interface is enabled. It can be driven with 1.2V to 3.3V logic levels. RFSW (Pin 4): RF channel select. The state of the RF switch is the logical AND of the RFSW pin and the RFSW register value. (See Appendix). This pin should not be left floating. Either tie high or low. VCC (Pin 18): Positive supply pin. This pin should be bypassed with a 1000pF and 4.7µF capacitor to ground. VCCN (Pin 5): Positive Supply Pin. This pin must be tied to the VCC pin. LOP, LOM (Pins 19, 20): LO inputs. External matching is not needed. Can be driven 50Ω single-ended or 100Ω differentially. The LO pins should be DC-blocked with coupling capacitor; 1000pF is recommended. When driven single-ended, the unused pin should be terminated with 50Ω in series with the DC-blocking capacitor. VCM (Pin 6): IF amplifier common-mode output voltage adjust. Source resistance should be 1kΩ or lower. If this pin is left unconnected, it will internally self-bias to 0.9V. SDO (Pin 21): Serial Data Output. This output can accommodate logic levels from 1.2V to 3.3V. During read-mode, data is read out MSB first. RFB (Pin 7): 50Ω switched RF input. The pin should be DCblocked with coupling capacitor; 1000pF is recommended. SDI (Pins 22): Serial Data Input. Data is clocked MSB first into the mode-control registers on the rising edge of SCK. SDI can be driven with 1.2V to 3.3V logic levels. MQP, MQM, MIM, MIP (Pins 9, 10, 31, 32): Mixer differential output pins. When connected to the amplifier input pins, the DC bias point is VCC – 1.3V for each pin. A low-pass filter is typically used between the MQM(P) or MIM(P) pins and the AQM(P) or AIM(P) pins to suppress the high frequency mixing products. See the Applications section for more information. DNC (Pins 11, 14, 27, 30): DO NOT CONNECT. No connection should be made to these pins. AQM, AQP, AIP, AIM (Pins 12, 13, 28, 29): Amplifier differential input pins. When connected to the mixer output pins, the DC bias point is VCC – 1.3V for each pin. A low-pass filter is typically used between the AQM(P) or AIM(P) pins and the MQM(P) or MIM(P) pins to suppress the high frequency mixing products. See the Applications section for more information. SCK (Pin 23): Serial Clock Input. SDI can be driven with 1.2V to 3.3V logic levels. OVDD (Pin 24): Positive digital interface supply pin. This pin sets the logic levels for the digital interface. 1.2V to 3.3V can be used. This pin should be bypassed with a 1µF capacitor to ground. The VCC supply must be applied before the OVDD supply to prevent damage to the ESD diodes. GND (Pins 1, 8, Exposed Pad Pin 33): Ground. These pins must be soldered to the circuit board RF ground plane. The backside exposed pad ground connection should have a low-inductance connection and good thermal contact to the printed circuit board ground plane using many through-hole vias. See layout information. IFQM, IFQP, IFIP, IFIM (Pins 15, 16, 25, 26): IF amplifier output pins. The current used by the output amplifiers 14 5586f For more information www.linear.com/LTC5586 LTC5586 BLOCK DIAGRAM 18 32 VCC 5 3 2 7 4 VCCN 31 MIP MIM 22 21 17 AIM 28 AIP FINE GAIN/DC OFFSET/ DISTORTION ADJUST BIAS VCM TEMP IFIP + – RFB 0º 90º RFSW SDI SPI CSB ADJUST REGISTERS 26 LOP IFQM IFQP 20 19 15 16 8 STEPS GND FINE GAIN/DC OFFSET/ DISTORTION ADJUST OVDD 24 LOM LO MATCH ADJUST – + SCK SDO IFIM 6 25 8 STEPS RFA ATTEN 0dB TO 31dB 23 29 MQP 9 MQM 10 GND AQM AQP 12 13 1 8 EXPOSED PAD 33 5586 BD01 5586f For more information www.linear.com/LTC5586 15 LTC5586 TIMING DIAGRAMS SPI Port Timing (Readback Mode) tCSS tDO tCKH AUTO-INCREMENT tCKL AUTO-INCREMENT CSB tCSH SCK tDS SDI R/W A6 tDH A5 A4 A3 A2 A1 A0 XX HIGH-Z SDO (SDO_MODE=1) HIGH-Z SDO (SDO_MODE=0) D7 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 HIGH-Z HIGH-Z 5586 TD01 SPI Port Timing (Write Mode) tCSS tDO tCKH AUTO-INCREMENT tCKL AUTO-INCREMENT CSB tCSH SCK tDS SDI HIGH-Z SDO (SDO_MODE=1) R/W A6 tDH A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 HIGH-Z SDO (SDO_MODE=0) 16 HIGH-Z HIGH-Z 5586 TD02 5586f For more information www.linear.com/LTC5586 LTC5586 TEST CIRCUIT RF GND 0.015" 0.062" C10 DC GND NELCO N4000-13 C12 IFIM OUTPUT R3 0.015" C9 L1 R5 L2 C11 R4 C1 RFA INPUT C2 C3 RFB INPUT C4 VCC 26 31 29 27 25 32 30 28 MIP MIM DNC AIM AIP DNC IFIM IFIP 1 GND OVDD SCK 2 RFA SDI TEMP 3 TEMP SDO RFSW 4 RFSW LOM VCC 5 VCCN U1 VCM 6 LTC5586IUH VCM 7 RFB LOP 8 GND 33 GND VCC CSB MQP MQM DNC AQM AQP DNC IFQM IFQP 9 C13 R20 10 11 12 13 14 15 IFIP OUTPUT OVDD 24 23 SCK 22 SDI 21 SDO 20 C40 C6 LO INPUT C5 R1 19 18 17 CSB C7 C8 C42 C43 16 VCC 4.75V TO 5.25V IFQP OUTPUT C15 R11 R13 TEMP C14 L3 L4 C16 R12 IFQM OUTPUT 5586 F01 REF DES VALUE SIZE VENDOR REF DES VALUE SIZE VENDOR C1, C3, C6, C8, C42 1000pF 0402 Murata L1-L4 22nH 0805 Coilcraft C2, C4, C5, C7 0.3pF 0402 Murata R1, R3, R4, R11, R12 49.9Ω 0402 C9-C16 3.0pF 0201 Murata R5, R13 0Ω 0402 C40 1μF 0603 Murata R20 40.2kΩ 0402 C43 4.7μF 0805 Murata Figure 1. Test Circuit Schematic 5586f For more information www.linear.com/LTC5586 17 LTC5586 TEST CIRCUIT Figure 2. Component Side of Evaluation Board Figure 3. Bottom Side of Evaluation Board 18 5586f For more information www.linear.com/LTC5586 LTC5586 APPLICATIONS INFORMATION The LTC5586 is an IQ demodulator designed for high dynamic range receiver applications. It consists of RF switches, a step attenuator, I/Q mixers, quadrature LO amplifiers, IF amplifiers, and correction circuitry for DC offset, image rejection, and non-linearity. Operation As shown in the Block Diagram for the LTC5586, the RF inputs, RFA and RFB, are selected by an internal switch. The RF signal is then converted to a differential signal by the on-chip balun transformer covering the 300MHz to 6GHz band. A differential 0 to 31dB step attenuator then scales the RF input level to the I and Q channel mixers. The LO inputs are impedance matched using a programmable network, and then accurately shifted in phase by 90° by an internal precision phase shifter. This phase shifter maintains the accurate quadrature relation over the full LO input range from 300MHz to 6GHz. In addition, the phase shifter allows fine tuning of the phase difference between the I- and Q-channel LO with a resolution of around 0.05 degrees to compensate for any phase mismatch between the mixers and phase mismatch introduced into the IF path by any filter component mismatch. The differential mixer IF output signals are filtered off-chip to remove the fRF + fLO signal and other high frequency mixing products before being applied to the on-chip IF amplifiers. The IF amplifiers have adjustable gain and common-mode output voltage to allow for direct interfacing with A/D converters. The gain balance between both IF output channels of the LTC5586 can be fine tuned with a resolution of about 0.016dB in order to compensate for gain mismatches in the IF signal path, either caused internally by the device or by external amplifiers and filters. The DC offset in both IF channels can be adjusted in order to minimize the accumulated DC offset at the A/D converter input. The RF switch state, attenuation, IF gain, gain error and phase error adjust, DC offset adjust, and non-linearity adjust registers are digitally controlled through a 4-wire SPI interface. The register map is detailed in the Appendix. RF Input Ports Figure 4 shows a simplified schematic of the demodulator’s RF inputs (the RFA input is identical to RFB input) which consist of an RF switch, balun transformer, and step-attenuator. External DC voltage should not be applied to the RF input pins. DC current flowing into the pins may cause damage to the chip. Series DC blocking capacitors should be used to couple the RF input pins to the RF signal sources. The RF switch can be selected by the RFSW pin, and by the RFSW register 0x17 bit[0]. The RFA input is selected when the logical AND of the value of RFSW in register 0x17 and the logic level of the RFSW pin is 1 (see digital input pins section and register map). The switch state is detailed in Table 1. Table 1. RF Switch State vs Logic Levels RFSW RFSW Pin Register 0 1 0 RFB RFB 1 RFB RFA VCC LTC5586 RFA INPUT (MATCHED) C1 1000pF RFA C2 0.3pF RFB GND RFSW 5586 F04 Figure 4. Simplified Schematic of the RF Input with External Matching Components 5586f For more information www.linear.com/LTC5586 19 LTC5586 APPLICATIONS INFORMATION As shown in Figure 5, the RF input ports are well matched with return loss greater than 10dB over the frequency range of 500MHz to 6GHz with a 0.3pF capacitor on C2. The RF pins can be externally matched over the 300MHz to 500MHz frequency range by changing C2 to 4.7pF. Figure 6 shows the RF input return loss with C2 set to 4.7pF. Table 2 shows the impedance and input reflection coefficient for the RF input with C2 = 0.3pF. The input transmission line length is de-embedded from the measurement. 5 –RETURN LOSS (dB) –5 –10 –15 –20 –25 –35 S11 MAG 0.468 0.403 0.330 0.215 0.211 0.297 0.310 0.303 0.228 0.185 0.120 0.202 0.259 0.188 0.138 ANGLE (°) 112.0 83.5 56.2 –3.2 –96.7 –173.2 134.4 96.0 79.9 72.3 33.8 30.8 14.6 –18.0 –96.1 LO Input Port The demodulator’s LO input interface is shown in Figure 7. The input consists of a programmable input match and a high precision quadrature phase shifter which generates 0° and 90° phase shifted LO signals for the LO buffer amplifiers to drive the I/Q mixers. DC blocking capacitors are required on the LOP and LOM inputs. When using a single-ended LO input, it is necessary to terminate the unused LO input (LOP in Figure 7) into 50Ω. 0 1 2 3 4 5 6 RF FREQUENCY (GHz) 7 8 5586 F05 Figure 5. RF Input Return Loss 5 C2 = 4.7pF TC = 25°C 0 –RETURN LOSS (dB) INPUT IMPEDANCE (Ω) 24.9 + j27.6 39.1 + j37.3 60.1 + j36.9 77.4 – j1.9 43.7 – j19.2 27.2 – j2.1 29.6 + j14.5 39.3 + j26.0 48.9 + j23.1 52.4 + j19.2 60.5 + j8.2 69.2 + j15.0 82.4 + j11.5 71.2 – j8.6 46.8 – j13.1 RFA, RFA SELECTED RFB, RFB SELECTED RFA, RFB SELECTED RFB, RFA SELECTED –30 Table 2. RF Input Impedance FREQUENCY (MHz) 300 400 500 700 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 C2 = 0.3pF TC = 25°C 0 RFA, RFA SELECTED –5 –10 –15 –20 –25 –30 0 1 2 3 4 5 6 RF FREQUENCY (GHz) 7 8 5586 F06 Figure 6. RF Input Return Loss with C2 = 4.7pF VCC LO INPUT (MATCHED) C6 1000pF R1 49.9Ω C8 1000pF LTC5586 LOM C5 0.3pF LO MATCH ADJUST LOP 0º 90º C7 0.3pF GND 5586 F07 Figure 7. Simplified Schematic of the LO Inputs with Single-Ended Drive 20 5586f For more information www.linear.com/LTC5586 LTC5586 APPLICATIONS INFORMATION The programmable input match adjust is controlled by the BAND, CF1, LF1, and CF2 registers as detailed in the register map shown in Table 3. The return loss for the register setting in Table 3 is shown in Figure 8. 5 VCC TC = 25°C 0 –RETURN LOSS (dB) The LO inputs can also be driven differentially. Figure 10 compares the uncalibrated OIP2 performance of single ended versus differential LO drive using the ANAREN B4859A53 balun as shown in the schematic of Figure 9. –5 LO INPUT (MATCHED) –10 –15 ANAREN B4859A53 C6 1000pF C8 1000pF –20 LTC5586 LOM C5 0.3pF LO MATCH ADJUST LOP 0º 90º C7 0.3pF –25 –30 –35 0 1 2 3 4 5 6 LO FREQUENCY (GHz) 0, 31, 3, 31 0, 17, 2, 31 0, 14, 1, 27 1, 21, 3, 28 7 1, 15, 1, 31 1, 2, 1, 10 1, 1, 0, 19 1, 0, 0, 0 5586 F09 GND 8 Figure 9. Simplified Schematic of the LO Inputs Using a Balun for Differential Drive 100 5586 F08 Figure 8. Single-Ended LO Input Return Loss vs BAND, CF1, LF1, and CF2 TC = 25°C 90 80 Table 3. Register Settings for Single-Ended LO Matching LO FREQUENCY (MHz) 300 - 339 339 - 398 398 - 419 419 - 556 556 - 625 625 - 801 801 - 831 831 - 1046 1046 - 1242 1242 - 1411 1411 - 1696 1696 - 2070 2070 - 2470 2470 - 2980 2980 - 3500 3500 - 6000 BAND 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CF1 31 21 14 17 10 15 14 8 31 21 17 15 8 2 1 0 LF1 3 3 3 2 2 1 1 1 3 3 2 1 1 1 0 0 CF2 31 24 23 31 23 31 27 21 31 28 26 31 21 10 19 0 OIP2 (dBm) 70 60 50 40 30 I, SINGLE-ENDED Q, SINGLE-ENDED I, DIFFERENTIAL Q, DIFFERENTIAL 20 10 0 0 1 2 3 4 RF FREQUENCY (GHz) 5 6 5586 F10 Figure 10. OIP2 vs Single-Ended and Differential LO Input 5586f For more information www.linear.com/LTC5586 21 LTC5586 APPLICATIONS INFORMATION Interstage Filter An interstage IF filter should be used between the MIP (MIM) and AIP (AIM) pins and the MQP (MQM) and AQP (AQM) pins to suppress the large fRF + fLO and other mixing products from the mixer outputs. Without the filter, the linearity of the amplifier can be degraded for the desired signal. Figure 11 shows a recommended lowpass filter. Table 4 shows typical values used for a lowpass response of various bandwidths. lengths on the amplifier inputs can lead to instability. As shown in Figure 12, a 50Ω common-mode termination resistor can be used to better ensure stability with long line lengths and/or higher order filtering. The placement of C9 and C11 should be as close as possible to the mixer outputs for effective filtering of the 2xLO, fRF + fLO, and other mixing products. MIP MIM C11 C9 Table 4. Component Values for Interstage Lowpass Filter 1dB BW (MHz) 20 50 100 300 500 1000 L1, L2 (nH) 330 150 68 33 22 8 C9, C11 (pF) 39 15 10 4.7 3.0 0.5 C10, C12 (pF) 120 47 22 6.8 3.0 1.0 L2 C12 L1 C10 AIM AIP 5586 F12 50Ω Figure 12. Interstage IF Filter with Common-Mode Termination It is important that the placement of C10 and C12 be as close as possible to the amplifier inputs. Long line By adjusting the values of the capacitors in the filter, it is possible to add or remove frequency slope of the IF VCC LTC5586 1pF 50Ω 50Ω PACKAGE PARASITICS 1pF 1.5nH 2k MIP 0.2pF 1.5nH MIM 0.2pF 36mA C11 C9 36mA AC CURRENT SOURCE L2 VCC 100Ω PACKAGE PARASITICS 1.5nH 100Ω 1.5nH 0.6pF 50Ω AIM L1 C12 C10 0.2pF AIP 0.2pF 0.6pF 50Ω 5586 F11 GND Figure 11. Simplified Schematic of the Mixer Output and IF Amplifier Input with Interstage Filter 22 5586f For more information www.linear.com/LTC5586 LTC5586 APPLICATIONS INFORMATION response. The RF input has a frequency slope above 2GHz of approximately –2dB/GHz. If a high-side LO (HSLO) is used the resulting IF slope will be 2dB/GHz. If a low-side LO (LSLO) is used the resulting IF slope will be –2dB/GHz. The IF filter component values can be adjusted so that approximately 1dB of peaking or roll-off can be achieved over the filter bandwidth to give an overall flat IF response for the HSLO or LSLO case. 45 IF TONESPACING = 1MHz PIF = –1.5dB/TONE TC = 55°C 40 OIP3 (dBm) 35 30 0.5V 0.7V 0.9V 1.2V 1.5V 1.8V 2.0V 25 20 I-Channel and Q-Channel Outputs 15 The phase relationship between the I-channel output signal and the Q-channel output signal is fixed. When the LO input frequency is higher (or lower) than the RF input frequency, the Q-channel outputs (IFQP, IFQM) lead (or lag) the I-channel outputs (IFIP, IFIM) by 90°. Figure 14 shows a simplified schematic of the IF amplifier outputs. The current-mode outputs require a terminating resistance to establish a common-mode voltage level. The optimum operating current is 18mA per output. A 50Ω termination to ground is recommended on each output for a 0.9V common-mode voltage. Operation at higher or lower common-mode voltages is possible with the addition of a common-mode termination. For example, to operate at 1.8V, an additional common-mode resistance of 25Ω (R5 = 66.5Ω and R6 = 0Ω, or R5 = R6 = 43.2Ω) would be used to maintain an output current of 18mA. To operate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 IF Frequency (GHz) 5586 F13 Figure 13. OIP3 of Amplifier Only vs Output Common-Mode Voltage (VCM) at lower common-mode voltages, a lower termination resistance can be used on each output at the expense of conversion gain, or a negative supply can be used at the connection of the termination resistors. Figure 13 shows the OIP3 of the amplifier alone with various commonmode voltages. The amplifier gain can be adjusted in 8 steps of roughly 1dB from 7dB to 15dB using the AMPG register. Setting AMPG = 0x7 sets the gain at about 15dB and setting AMPG = 0x0 sets the gain to about 7dB. VCC LTC5586 + – 5TH ORDER ANTI-ALIAS FILTER 2k VCM AC CURRENT SOURCE L5 0.9V PACKAGE PARASITICS 1.5nH 2k C17 IFIP 0.2pF 1.5nH 0.2pF C20 R3 68.1Ω R5 0Ω R2 24.9Ω IFIM L7 C18 R4 68.1Ω L6 0.9V R7 200Ω C23 R6 0Ω L8 R9 24.9Ω R8 200Ω C21 C24 ZOUT = 100Ω 5586 F14 GND Figure 14. Simplified Schematic of the IF Amplifier Output with Anti-Alias Filter 5586f For more information www.linear.com/LTC5586 23 LTC5586 APPLICATIONS INFORMATION A typical anti-alias filter is shown in Figure 14 for interface with an ADC. The parallel combinations R3||R7 and R4||R8 set the differential impedance for the ADC. The input and output of the filter contain a common-mode termination for high frequencies. These are formed by C17, C18 and 24.9Ω at the input and C23, C24 and 24.9Ω at the output. The common-mode termination at the amplifier output ensures stability and the common-mode termination at the ADC input provides a termination for the high-frequency kickback from the sampling capacitors in the ADC. Table 5 shows some typical values vs 1dB cutoff frequency for the anti-alias filter. To optimize the flatness and ripple of the IF band, both the IF interstage filter and the anti-alias filter can be designed together in a simulator including package parasitics. The additional slope due to RF slope and HSLO or LSLO can be compensated by using this method. The layout of the anti-alias filter should be done so that the amplifier outputs and ADC inputs are as close as possible. This is to prevent long line lengths from introducing additional parasitics. Table 6. IF Amplifier S-Parameters (Differential-Mode) Table 5. Component Values for Anti-Alias Lowpass Filter Table 7. IF Amplifier S-Parameters (Common-Mode) 1dB BW (MHz) 20 50 100 300 500 1000 L5 – L8 (nH) 560 240 120 33 22 8 C17, C18 (pF) 56 22 12 3.9 1.8 1.0 C20, C21 (pF) 180 68 39 8.2 6.8 3.3 C23, C24 (pF) 82 33 22 6.8 3.3 1.8 Tables 6 and 7 show the differential and common-mode S-parameters for the amplifier by itself with 50Ω terminations on all ports. In addition, common-mode terminations were used on the input and output ports having a value of 2pF in series with 50Ω. 24 IF (MHz) 0.001 100 200 300 400 500 600 700 800 900 1000 1500 2000 2500 3000 3500 4000 S11 S12 S22 ANG MAG ANG MAG ANG MAG ANG 0.204 0.203 0.205 0.207 0.210 0.215 0.221 0.227 0.235 0.242 0.251 0.303 0.365 0.385 0.365 0.319 0.307 –179.9 176.0 172.2 168.5 164.8 160.9 157.0 153.0 149.0 144.6 140.6 117.6 90.2 56.1 16.6 –28.2 –83.4 2.129 2.154 2.170 2.197 2.239 2.292 2.363 2.445 2.535 2.642 2.770 3.420 3.318 2.232 2.620 1.021 0.742 180.0 171.9 163.7 155.6 147.3 138.8 130.1 121.2 112.0 102.0 92.3 32.3 –45.5 –105.2 –160.2 157.4 113.3 1.8e-4 5.4e-4 1.0e-4 1.7e-4 2.8e-4 3.2e-4 4.0e-4 5.0e-4 5.5e-4 6.9e-4 7.9e-4 0.003 0.005 0.005 0.005 0.005 0.005 164.8 118.0 102.8 92.8 93.7 95.4 92.0 92.1 86.2 93.2 92.7 92.6 33.2 –3.1 –34.2 –61.9 –79.5 0.014 0.026 0.050 0.079 0.111 0.147 0.186 0.230 0.279 0.334 0.396 0.738 0.828 0.666 0.488 0.418 0.409 178.5 –120.9 –112.0 –113.5 –118.3 –125.0 –132.1 –140.0 –148.1 –157.0 –166.2 134.4 70.0 13.1 –38.4 –94.7 –150.6 IF (MHz) 0.001 100 200 300 400 500 600 700 800 900 1000 1500 2000 2500 3000 3500 4000 S21 MAG MAG S11 ANG 0.184 0.186 0.188 0.191 0.196 0.202 0.210 0.219 0.230 0.243 0.252 0.325 0.438 0.549 0.601 0.618 0.595 –138.7 172.5 166.6 160.2 154.4 148.4 142.8 137.2 132.0 126.5 120.9 96.7 72.1 40.1 6.9 –27.5 –60.3 S21 S12 S22 MAG ANG MAG ANG MAG ANG 9.2e-4 0.085 0.173 0.237 0.291 0.340 0.387 0.436 0.488 0.550 0.612 0.981 0.776 0.496 0.397 0.281 0.254 –112.8 –118.9 –134.7 –150.0 –163.8 –176.8 170.9 159.1 147.1 134.9 122.2 43.4 –46.1 –97.1 –143.2 –175.7 147.3 0.037 0.013 0.007 0.004 0.002 0.002 0.002 0.003 0.003 0.004 0.006 0.020 0.036 0.041 0.042 0.044 0.046 –65.3 –68.6 –91.8 –113.1 –145.4 170.2 137.0 118.1 107.8 106.6 104.8 80.4 18.6 –21.9 –52.2 –80.3 –101.2 0.985 0.152 0.125 0.097 0.067 0.037 0.023 0.051 0.094 0.148 0.211 0.749 1.000 0.873 0.764 0.668 0.620 179.8 126.7 116.7 97.3 75.2 43.6 –38.0 –97.8 –121.5 –137.0 –151.3 136.1 55.9 2.9 –37.3 –72.7 –107.0 5586f For more information www.linear.com/LTC5586 LTC5586 APPLICATIONS INFORMATION The common-mode feedback amplifier holds the commonmode output voltage within about 20mV of the VCM pin voltage. The VCM pin interface is shown in Figure 15. The VCM pin should be driven by a voltage source with an output impedance lower than 1kΩ. When the VCM pin is unbiased, the output common-mode voltage will be held at a nominal 0.9V given by the internal voltage divider formed by the 40kΩ and 8kΩ resistors. Connecting the VCM pin to an ADC common-mode reference pin allows the output common-mode voltage of the IF amplifier to track the ADC common-mode. Temperature Diode A schematic of the TEMP pin is shown in Figure 16. The temperature diode can be used to directly measure the die temperature. A 40kΩ resistor is recommended to VCC to generate a 100µA current source for the diode readout. The temperature slope is about –1.52mV/°C. VCC LTC5586 VCC 40k 20k VCM VCC LTC5586 R20 40.2k 250Ω VTEMP TEMP 100Ω 8k 6.5pF 5586 F16 5586 F15 GND GND Figure 15. Simplified Schematic of the VCM Input Pin Figure 16. Schematic of the TEMP Pin 5586f For more information www.linear.com/LTC5586 25 LTC5586 APPLICATIONS INFORMATION Digital Input Pins VCC Figure 17 show the simplified schematics for the digital input pins, SCK, CSB, SDI, and RFSW. These pins should not be left floating, since there is no internal pull-down or pull-up. LTC5586 SDO OVDD VCC LTC5586 DIGITAL INPUT DIGITAL INPUTS 5586 F18 2k GND Figure 18. Simplified Schematic of the OVDD Pin Interface SERIAL PORT GND 5586 F17 Figure 17. Simplified Schematic of the Digital Input Pins (SCK, CSB, SDI, RFSW) OVDD Interface Figure 18 shows the simplified schematic of the OVDD interface. The OVDD pin supplies the voltage for the digital inputs and SDO pin. By setting the pin at 1.2V to 3.3V, the serial port can function with 1.2V to 3.3V logic levels. It is important that when sequencing the supply voltages for the chip that the VCC supply be brought up first before the OVDD supply. This is to prevent the ESD diode connected between OVDD and VCC from getting damaged. 26 The SPI-compatible serial port provides control and monitoring functionality. Communication Sequence The serial bus is comprised of CSB, SCK, SDI and SDO. Data transfers to the part are accomplished by the serial bus master device first taking CSB low to enable the LTC5586’s port. Input data applied on SDI is clocked on the rising edge of SCK, with all transfers MSB first. The communication burst is terminated by the serial bus master returning CSB high. See the timing diagrams for details. Data is read from the part during a communication burst using SDO. Readback may be multidrop (more than one LTC5586 or other serial device connected in parallel on the serial bus), as SDO is high impedance (Hi-Z) when CSB = 1. 5586f For more information www.linear.com/LTC5586 LTC5586 APPLICATIONS INFORMATION Single Byte Transfers SDO_MODE Control Bit The serial port is arranged as a simple memory map, with status and control available in 23 registers as shown in the appendix. All data bursts are comprised of at least two 8-bit bytes. The most significant bit of the first byte is the read/write bit. Setting this bit to 1 puts the serial port into read mode. The next 7 bits of the first byte are address bits and can be set from 0x00 to 0x17. The subsequent byte, or bytes, is data from/to the specified register address. See the timing diagrams for details. Note that the written data is transferred to the internal register at the falling edge of the 16th clock cycle (parallel load). The SDO output has two modes of operation as shown in the timing diagram. When register 0x16 control bit SDO_MODE = 0, the SDO pin functions as a normal output which is High-Z during a write command. If SDO_MODE = 1, the SDO output is put into a serial repeater mode where SDO echos the command written to SDI before readback of register contents either in read or write mode. This can be used in high bus noise environments where it is necessary to perform error-checking on commands sent to the serial port. Multiple Byte Transfers More efficient data transfer of multiple bytes is accomplished by using the LTC5586’s register address autoincrement feature as shown in the timing diagram. The serial port master sends the destination register address in the first byte and reads or writes data in the second byte as before, but on the third byte the address pointer is auto-incremented by 1 and the serial port master can read or write to subsequent registers. If the register address pointer attempts to increment past 23 (0x17), it is automatically reset to 0. OVDD A simplified schematic of the SDO output is shown in Figure 19. The OVDD supply sets the logic level of the output, and a 25Ω series resistor limits the output current. Register Defaults The register map and defaults are given in Tables 8 and 9 in the appendix. When the device is powered up, the registers may not be reset to their default values. By writing a 1 to the SRST bit (bit[3]) of register 0x16, the device will go into soft reset and the registers will be reset to their default values. VCC LTC5586 25Ω SDO 5586 F19 GND Figure 19. Simplified Schematic of the SDO Pin Interface 5586f For more information www.linear.com/LTC5586 27 LTC5586 APPLICATIONS INFORMATION Impairment Minimization The LTC5586 contains circuitry for minimizing receiver impairments such as DC offset, Phase and Gain Error, and non-linearity. An example block diagram of a DPD transmitter application is shown in Figure 20. A DSP is used to implement a 2-tone source and minimization algorithms for calibration of impairments. To setup the DSP for impairment calibration, the DATA ENCODER would be configured to produce symbols for two tones in the band of interest. The tones would be modulated up to the carrier frequency of fLO before being applied to the LTC5586 RFA input. The tones are then down-converted to baseband for the DSP. In the DSP, a complex-FFT can be used to extract gain error and phase error for image rejection optimization, while the FFT of each channel can be used to optimize DC offset and nonlinearities independently. One possible general optimization method would be to sequentially apply a 1-D minimization algorithm to each impairment. A simple bisection method or more complicated (but faster converging) Brent’s method[1] could be used for the 1-D minimization. Figure 21 shows the non-optimized spectrum and Figure 22 shows the optimized spectrum for a 2-tone test signal at 2GHz. The Upper Sideband spectrum is the desired signal while the Lower Sideband is the image signal. [1] Saul Teukolsky, William T. Vetterling, William H. Press, and Brian P. Flannery, “Numerical Recipes in C: The Art of Scientific Computing,” p. 352, 1988. LTC5588-1 DSP LTC2000-14 DAC I 0º PA 90º COMPLEX GAIN PREDISTORTER LTC2000-14 DATA INPUT Q DAC DATA ENCODER LTC6946 fLO ADAPTIVE LUT LTC2158-14 LTC5586 ADC RFA 0º RFB 90º FEEDBACK SIGNAL PROCESSING I LINEARITY DC OFFSET IMAGE ADJUST RFSW FFT ADC Q EXTRACT FFT BIN SPI SPI IMPAIRMENT MINIMIZATION 5586 F20 Figure 20. Example Block Diagram of a DPD Transmitter with DSP for Impairment Minimization 28 5586f For more information www.linear.com/LTC5586 LTC5586 APPLICATIONS INFORMATION Figure 21. Non-Optimized 2-Tone Spectrum at 2GHz with 100MHz Anti-Alias Filter 5586f For more information www.linear.com/LTC5586 29 LTC5586 APPLICATIONS INFORMATION Figure 22. Optimized 2-Tone Spectrum at 2GHz with 100MHz Anti-Alias Filter 30 5586f For more information www.linear.com/LTC5586 LTC5586 APPENDIX Table 8. Serial Port Register Contents ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT 0x00 IM3QY[7] IM3QY[6] IM3QY[5] IM3QY[4] IM3QY[3] IM3QY[2] IM3QY[1] IM3QY[0] R/W 0x80 0x01 IM3QX[7] IM3QX[6] IM3QX[5] IM3QX[4] IM3QX[3] IM3QX[2] IM3QX[1] IM3QX[0] R/W 0x80 0x02 IM3IY[7] IM3IY[6] IM3IY[5] IM3IY[4] IM3IY[3] IM3IY[2] IM3IY[1] IM3IY[0] R/W 0x80 0x03 IM3IX[7] IM3IX[6] IM3IX[5] IM3IX[4] IM3IX[3] IM3IX[2] IM3IX[1] IM3IX[0] R/W 0x80 0x04 IM2QX[7] IM2QX[6] IM2QX[5] IM2QX[4] IM2QX[3] IM2QX[2] IM2QX[1] IM2QX[0] R/W 0x80 0x05 IM2IX[7] IM2IX[6] IM2IX[5] IM2IX[4] IM2IX[3] IM2IX[2] IM2IX[1] IM2IX[0] R/W 0x80 0x06 HD3QY[7] HD3QY[6] HD3QY[5] HD3QY[4] HD3QY[3] HD3QY[2] HD3QY[1] HD3QY[0] R/W 0x80 0x07 HD3QX[7] HD3QX[6] HD3QX[5] HD3QX[4] HD3QX[3] HD3QX[2] HD3QX[1] HD3QX[0] R/W 0x80 0x08 HD3IY[7] HD3IY[6] HD3IY[5] HD3IY[4] HD3IY[3] HD3IY[2] HD3IY[1] HD3IY[0] R/W 0x80 0x09 HD3IX[7] HD3IX[6] HD3IX[5] HD3IX[4] HD3IX[3] HD3IX[2] HD3IX[1] HD3IX[0] R/W 0x80 0x0A HD2QY[7] HD2QY[6] HD2QY[5] HD2QY[4] HD2QY[3] HD2QY[2] HD2QY[1] HD2QY[0] R/W 0x80 0x0B HD2QX[7] HD2QX[6] HD2QX[5] HD2QX[4] HD2QX[3] HD2QX[2] HD2QX[1] HD2QX[0] R/W 0x80 0x0C HD2IY[7] HD2IY[6] HD2IY[5] HD2IY[4] HD2IY[3] HD2IY[2] HD2IY[1] HD2IY[0] R/W 0x80 0x0D HD2IX[7] HD2IX[6] HD2IX[5] HD2IX[4] HD2IX[3] HD2IX[2] HD2IX[1] HD2IX[0] R/W 0x80 0x0E DCOI[7] DCOI[6] DCOI[5] DCOI[4] DCOI[3] DCOI[2] DCOI[1] DCOI[0] R/W 0x80 0x0F DCOQ[7] DCOQ[6] DCOQ[5] DCOQ[4] DCOQ[3] DCOQ[2] DCOQ[1] DCOQ[0] R/W 0x80 0x10 ATT[4] ATT[3] ATT[2] ATT[1] ATT[0] IP3IC[2] IP3IC[1] IP3IC[0] R/W 0x04 0x11 GERR[5] GERR[4] GERR[3] GERR[2] GERR[1] GERR[0] IP3CC[1] IP3CC[0] R/W 0x82 0x12 LVCM[2] LVCM[1] LVCM[0] CF1[4] CF1[3] CF1[2] CF1[1] CF1[0] R/W 0x48 0x13 BAND LF1[1] LF1[0] CF2[4] CF2[3] CF2[2] CF2[1] CF2[0] R/W 0xE3 0x14 PHA[8] PHA[7] PHA[6] PHA[5] PHA[4] PHA[3] PHA[2] PHA[1] R/W 0x80 0x15 PHA[0] AMPG[2] AMPG[1] AMPG[0] AMPCC[1] AMPCC[0] AMPIC[1] AMPIC[0] R/W 0x6A 0x16 1* 1* 1* 1* SRST SDO_MODE 0* 0* R/W 0xF0 0x17 CHIPID[1] CHIPID[0] 0* 0* 0* 0* 0* RFSW R/W 0x01 *Unused, do not change default value. 5586f For more information www.linear.com/LTC5586 31 LTC5586 APPENDIX Table 9. Serial Port Register Bit Field Summary BITS FUNCTION DESCRIPTION VALID VALUES DEFAULT AMPCC[1:0] IF Amplifier IM3 CC Adjust Used to optimize the IF amplifier IM3. 0x00 to 0x03 0x02 AMPIC[1:0] IF Amplifier IM3 IC Adjust Used to optimize the IF amplifier IM3. 0x00 to 0x03 0x02 AMPG[2:0] IF Amplifier Gain Adjust Adjusts the amplifier gain from 6dB to 15dB. 0x00 to 0x07 0x06 ATT[4:0] Step Attenuator Control Controls the step attenuator from 0dB to 31dB attenuation. 0x00 to 0x1F 0x00 BAND LO Band Select Selects which LO matching band is used. BAND = 1 for high band. BAND = 0 for low band. 0, 1 1 CF1[5:0] LO Matching Capacitor CF1 Controls the CF1 capacitor in the LO matching network. 0x00 to 0x1F 0x08 CF2[5:0] LO Matching Capacitor CF2 Controls the CF2 capacitor in the LO matching network. 0x00 to 0x1F 0x03 CHIPID Chip Identification Bits Factory set to default value. 0x00 to 0x03 0x00 DCOI[7:0] I-Channel DC Offset Controls the I-channel DC offset over a range from –200mV to 200mV. 0x00 to 0xFF 0x80 DCOQ[7:0] Q-Channel DC Offset Controls the Q-channel DC offset over a range from –200mV to 200mV. 0x00 to 0xFF 0x80 GERR[5:0] IQ Gain Error Adjust Controls the IQ gain error over a range from –0.5dB to 0.5dB. 0x00 to 0x3F 0x20 HD2IX[7:0] HD2 I-Channel X-Vector Controls the I-channel HD2 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD2IY[7:0] HD2 I-Channel Y-Vector Controls the I-channel HD2 Y-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD2QX[7:0] HD2 Q-Channel X-Vector Controls the Q-channel HD2 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD2QY[7:0] HD2 Q-Channel Y-Vector Controls the Q-channel HD2 Y-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD3IX[7:0] HD3 I-Channel X-Vector Controls the I-channel HD3 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD3IY[7:0] HD3 I-Channel Y-Vector Controls the I-channel HD3 Y-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD3QX[7:0] HD3 Q-Channel X-Vector Controls the Q-channel HD3 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 HD3QY[7:0] HD3 Q-Channel Y-Vector Controls the Q-channel HD3 Y-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IM2IX[7:0] IM2 I-Channel X-Vector Controls the I-channel IM2 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IM2QX[7:0] IM2 Q-Channel X-Vector Controls the Q-channel IM2 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IM3IX[7:0] IM3 I-Channel X-Vector Controls the I-channel IM3 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IM3IY[7:0] IM3 I-Channel Y-Vector Controls the I-channel IM3 Y-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IM3QX[7:0] IM3 Q-Channel X-Vector Controls the Q-channel IM3 X-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IM3QY[7:0] IM3 Q-Channel Y-Vector Controls the Q-channel IM3 Y-vector adjustment if EADJ = 1. 0x00 to 0xFF 0x80 IP3CC[1:0] RF Input IP3 CC Adjust Used to optimize the RF input IP3. 0x00 to 0x03 0x02 IP3IC[2:0] RF Input IP3 IC Adjust Used to optimize the RF input IP3. 0x00 to 0x07 0x04 LF1[1:0] LO Matching Inductor LF1 Controls the LF1 inductor in the LO matching network. 0x00 to 0x03 0x03 LVCM[2:0] LO Bias Adjust Used to optimize mixer IP3. 0x00 to 0x07 0x02 PHA[8:0] IQ Phase Error Adjust Controls the IQ phase error over a range from –2.5 Degrees to 2.5 Degrees. 0x000 to 0x1FF 0x100 RFSW RF Switch Input Select Controls the RF switch state with a logical AND of the RFSW pin. 0, 1 1 SDO_MODE SDO Readback Mode Enables the SDO readback mode if SDO_MODE = 1. 0, 1 0 SRST Soft Reset Writing 1 to this bit resets all registers to their default values. 0, 1 0 32 5586f For more information www.linear.com/LTC5586 LTC5586 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC5586#packaging for the most recent package drawings. UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 REF (4 SIDES) 3.45 ±0.05 3.45 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ±0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ±0.05 R = 0.05 TYP 0.00 – 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 31 32 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 ±0.10 3.45 ±0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ±0.05 0.50 BSC 5586f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC5586 33 LTC5586 TYPICAL APPLICATION Simplified Schematic of a 0.3GHz to 6.0GHz Receiver, (Only I-Channel Is Shown) L1, 68nH C9 10pF C10 22pF L2, 68nH C11 C12 10pF 22pF MIP MIM ANTI-ALIAS FILTER AIM AIP LTC5586 RF INPUT 0.3 - 6.0GHz IFIP C2 0.3pF IFIM LOM LOP C8 1000pF R1 49.9Ω C17 12pF R2 25Ω C18 12pF R3 68Ω R4 68Ω L6, 120nH VCM L7, 120nH C20 39pF R7 200Ω R8 200Ω L8, 120nH C23 22pF LTC2158-14 AIN+ R9 25Ω AIN- C24 22pF C21 39pF C45 0.01µF DA12_13 • • • C1 1000pF RFA C6 1000pF LO INPUT 0.3 - 6.0GHz L5, 120nH ADC DDR LVDS DA0_1 VCM C47 0.01µF R32, 10Ω 5586 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Infrastructure LTC5569 2dB Gain, 26.7dBm IIP3 and 11.7dB NF at 1950MHz, 3.3V/180mA Supply LTC6409 LTC5549 300MHz to 4GHz Dual Active Downconverting Mixer 10GHz GBW Differential Amplifier 2GHz to 14GHz Mixer with Integrated LO Doubler DC-Coupled, 48dBm OIP3 at 140MHz, 1.1nV/√Hz Input Noise Density Ultra-Wideband Bidirectional Up-, or Down-Conversion Mixer, +22.8dBm IIP3 at 12GHz, 0dBm LO Drive, 500MHz to 6GHz IF Bandwidth LTC5548 2GHz to 14GHz Mixer with IF Frequency Extending Ultra-Wideband Bidirectional Up-, or Down-Conversion Mixer, +18.7dBm IIP3 at to DC 12GHz, 0dBm LO Drive with On-Chip Frequency Doubler, DC to 6GHz IF Bandwidth LTC5588-1 200MHz to 6GHz Quadrature Modulator +31dBm OIP3, –160dBm/Hz Output Noise Floor, Excellent ACPR Performance RF PLL/Synthesizer with VCO LTC6946-3 Low Noise, Low Spurious Integer-N PLL with 640MHz to 5.79GHz, –157dBc/Hz WB Phase Noise Floor, –100dBc/Hz Closed-Loop Integrated VCO Phase Noise LTC6948 Ultralow Noise Fractional-N Synthesizer with 370MHz to 6.39GHz PLL, No Delta-Sigma Modulator Spurs, 18-Bit Fractional Integrated VCO Denominator, –226dBc/Hz Normalized In-Band Phase Noise Floor ADCs 73.1dB SNR, 90dB SFDR, 95mW/Ch Power Consumption LTC2145-14 14-Bit, 125Msps 1.8V Dual ADC LTC2185 16-Bit, 125Msps 1.8V Dual ADC 76.8dB SNR, 90dB SFDR, 185mW/Channel Power Consumption LTC2158-14 14-Bit, 310Msps 1.8V Dual ADC, 1.25GHz Full68.8dB SNR, 88dB SFDR, 362mW/Ch Power Consumption, 1.32VP-P Input Range Power Bandwidth 34 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC5586 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC5586 5586f LT 0616 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2016