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Analog Integrated Circuits
Fundamental Building Blocks
Basic OTA/Opamp architectures
Faculty of Electronics
Telecommunications and
Information Technology
Gabor Csipkes
Bases of Electronics Department
Outline
 definition of the OTA/opamp
 cascade of amplifier stages – the general opamp architecture
 the uncompensated Miller opamp – small signal model at low and high frequencies
 step response of a second order system with unity feedback
 the two stage opamp with Miller compensation – models and parameters
 sizing algorithm for the two stage Miller opamp
 the telescopic opamp – voltage budget, models and parameters
 sizing algorithm of the telescopic opamp
 the folded cascode opamp – small signal low and high frequency model
 sizing algorithm for the folded cascode opamp
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
2
The ideal opamp - definitions
 ideal opamp = a differential input, voltage controlled voltage source with very large
open loop gain
 the ideal gain is frequency independent, but real gain can be modeled with a set of poles
and zeros → typically low pass behavior
 very large input resistance and near zero output resistance
 opamps with strictly capacitive loads can have large output resistance → Operational
Transconductance Amplifiers (OTA) often also called opamp
 the output may be single ended (referenced to ground) or differential
 single or symmetrical supply voltages
Vout  a V   V  
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The opamp – a cascade of elementary stages
 the typical opamp architecture → a differential amplifier followed by a high gain
inverting stage and a voltage follower for low output impedance
 the voltage follower may be missing if the load is known to be strictly capacitive
 frequency compensation for closed loop stability probably required (more on this later)
 elementary amplifier stages → subsequent V-I and I-V conversions
 most simple form → the two stage opamp
V-I
I-V
I-V
cascade of elementary stages
V-I
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The two stage or Miller opamp
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The two stage opamp
 the small signal low frequency model with two equivalent stages
 no capacitive effects → low frequency or DC voltage gain
 each stage can be analyzed individually → Gm and Rout specific to each configuration
V
Gm1  g m1,2

 Rout1  rDS 2 || rDS 4

Gm 2  g m 6
 R  r || r
 out 2 DS 6 DS 7
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
a0  Gm1 Rout1 Gm 2 Rout 2





a1
a2
6
The two stage opamp
 the small signal high frequency model → consider load and parasitic capacitances
V
C1  C2  CGD1,2

C3  CGS 3  CGS 4  CDB1  CDB 3
C4  CGD 4

C5  CGS 6  CDB 2  CDB 4
C  C
GD 6
 6
C7  CL  CDB 6  CDB 7  CL
a(s) 
a0
1  sRout1C5 1  sRout 2C7 
The frequency response
is dominated by C5 and
C7 due to the large Rout1
and Rout2 !
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The two stage opamp – with negative feedback
 the closed loop model of an opamp with negative feedback
a( s)
A( s ) 
1  a( s)  r
The closed loop gain:
a( s) 
a0

s 
s 
1 
 1 

  p1    p 2 
a0
  p1 p 2 1  a0 r 
1  a0 r
a( s)
A( s ) 
 2
1  a ( s )  r s  s  p1   p 2    p1 p 2 1  a0 r 
The standard form of a second order transfer function:
(DC gain A0, resonant frequency ωn and damping factor ξ )
A0  n2
A( s )  2
s  2n s  n2
 p1   p 2
a0
1
A0 

; n   p1 p 2 1  a0 r  ;  
1  a0 r r
2  p1 p 2 1  a0 r 
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Frequency response of a second order system
 the effect of the feedback transmittance r on the magnitude response
A0 

1
r
A0 decreases
with r
 Overshoot of the frequency response at ωn →
complex poles → under damped step response
 worst case stability for unity gain (r=1 and
A0=1) → lowest ξ for given a0, ωp1 and ωp2
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Step response for unity gain feedback
 A( s ) 
 s 
 the time domain step response is calculated as Vout (t )  L 1 
 damping of the oscillation amplitude depends on ξ
 typically, if poles ωp1 and ωp2 are close to each other ξ<1 → under damped system with
fading oscillations of the step response



2 

1


e nt
Vout (t )  1 
sin n 1   2  t  arctan 

  

1  2







fading exponential
envelope
oscillations with the period
depending on ωn and ξ
 since the sin function varies between -1 and 1 → time domain overshoot around the unit
step → the overshoot and number of cycles until settling increases with a smaller ξ
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Step response for unity gain feedback
 step response of the two stage opamp in unity gain feedback configuration
 
optimal
response
 
 the circuit is unusable as amplifier for small ξ due to the very long settling time
 the response stability depends on the phase margin (mφ) → optimal response for mφ=65°
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Stability and phase margin
a( s)
 closed loop gain for unity feedback: A( s ) 
1  a( s)
What if denominator is 0 ???
a ( s )  1
 the closed loop gain approaches ∞ → even for no input any perturbation is amplified
with under damped transients → sustained oscillations occur, feedback turns positive and
system becomes unstable
 a ( j )  1
 Barkhausen's stability criteria: 
a ( j )  180
a0
solve for ω

 
  1
1 j
1  j



 p1 
 p2 

f 0dB
m  180  a  jodB  
 0 dB
 180  arctan 

 p1

 0 dB
  arctan 

  p2



Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
12
Pole locations and phase margin
 the relation between pole frequencies and f0dB defines mφ and the stability of the step
response
This is what
we need !
f p 2  f 0 dB
f p 2  f 0 dB
f p 2  f 0 dB
m  45
m  45
m  45
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Frequency compensation
 need fp2>f0dB so that mφ>45° → impossible to achieve by simply cascading a differential
amplifier and a common source inverting amplifier
1

f

 p1 2 R C

out1 5

1
f 
 p 2 2 Rout 2C7
Typically:
 Rout1  Rout 2

C7  C5
fp1 and fp2 are close to each other !!!
We need to manipulate pole
locations to separate fp1 and fp2 →
→ frequency compensation
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Miller frequency compensation
 idea 1: push p1 to lower frequencies by increasing C5 → must have very large values for
a satisfactory mφ → not practical for the integrated opamp
 idea 2: use the Miller effect to virtually increase C5 → practical solution since the gain of
the second stage is usually large → connect CM that emphasizes the capacitive shunt around
the inverting second stage
V

Gm1Vin  R  sC5V  sCM V  Vout   0

out1

G V  Vout  sC V  sC V  V 
L out
M
out
 m 2
Rout 2
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
15
Miller frequency compensation
 capacitances C1,C2, C3,C4 and C6 considered small and neglected for simplicity
 the frequency dependent gain a(s) results:


CM 
G
G
R
R
1

s


m1 m 2 out1 out 2 
G
m2 

a( s) 
dominant terms

2
k2 s  k1s  1

k  R R  C C  C C  C C 
out1 out 2
5 L
5 M
L M
 2
k1  Rout1C5  Rout 2CL   Rout1  Rout 2  CM  Gm 2 Rout1 Rout 2CM
 use the dominant pole approximation to find pole and zero locations

C 
Gm1Gm 2 Rout1 Rout 2 1  s M 
Gm 2 

a( s) 
Rout1 Rout 2CL CM s 2  Gm 2 Rout1 Rout 2CM s  1

s 
a0 1 
  zp 


a( s) 

s 
s 
1
 1 





p1 
p2 

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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Miller compensation – frequency response
One dominant pole, one high
frequency pole and one right
half plane zero:
a0  Gm1Gm 2 Rout1 Rout 2

1
 f p1( d ) 
2 Gm 2 Rout 2 Rout1CM


Gm 2

f

 p 2 2 C
L

Gm 2

 f zp  2 C

M
GBW  a0  f p1( d )
Gm1

2 CM
 GBW
m  90  arctan 
 f
 p2
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures

 GBW
  arctan 

 f zp



17
Miller compensation – step response
 assume unity gain negative feedback and apply an input step to the follower
A( s ) 
 step response calculated as Vout (t )  L 1 
 s 
 Slew Rate (SR) → variation rate of the output voltage
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
V
SR 
t
18
The two stage compensated opamp – slew rate
 the total capacitance of every node must be charged and discharged in each cycle
 charging rate depends on the largest supplied current
 every node limits the variation rate of Vout → the slew rate is imposed by the most
stringent limitation
Vout

 SR  t  min  SR1 , SR2 

 SR1  I 5 ; SR2  I 7
CM
CL

Typically I5<<I7, while CM and
CL are comparable
I5
SR 
CM
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The two stage opamp design algorithm
 specifications given (others are also possible)
 the low frequency open loop gain a0 larger than a critical value
 slew rate (SR)
 unity-gain bandwidth (GBW)
 the right half plane zero frequency relative to GBW (ratio k imposed by the
designer!)
 the typical load capacitance CL
 supply voltages
 phase margin mφ chosen according to the application (often unconditional stability !)
 typical transistor VDSat voltages (unless resulting from design constraints ! )
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
20
The two stage opamp design algorithm
 Step 1 → calculate the required compensation capacitor CM relative to CL
Gm1

GBW


2 CM


 f  Gm 2
 p 2 2 CL
Gm1

GBW  2 C

M

 f  Gm 2  k  GBW
 zp 2 CM
C
GBW Gm1 CL


 L
f p2
Gm 2 CM kCM
Gm1 1

Gm 2 k
m  f  GBW , f p 2 , f zp  
CM 
GBW

 1 
 tan 90  m  arctan   
f p2
 k 

CL

 1 
k  tan 90  m  arctan   
 k 

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
21
The two stage opamp design algorithm
 Step 2 → calculate the differential stage bias current for a given SR and CM
SR 
I5
CM
I 5  SR  CM
 Step 3 → calculate the transconductances Gm1 and Gm2
Gm1
GBW 
2 CM
Gm1  2  GBW  CM
Gm 2  k  Gm1
 Step 4 → find VDSat and the geometry of the input transistors
Gm1  g m1 
22II D1,2
VDSat1,2

I5
VDSat1,2
 Step 5 → choose VDSat for M3, M4 and M5
VDSat1,2
I5

Gm1
W 
 
 L 1,2
W  W 
  ; 
 L 3,4  L 5
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
22
The two stage opamp design algorithm
 Step 6 → balance the M3-M4 current mirror by choosing VDSat3=VDSat4=VDSat6 and find
the geometry of M6
Gm 2 
2I D6
2I7

VDSat 6 VDSat 6
I7 
1
 Gm 2  VDSat 6
2
 Step 7 → choose VDSat7=VDSat5 and determine the geometry of M7
W 
 
 L 6
W 
 
 L 7
Further ideas:
 remember the body effect and the parasitic capacitances → Gm-s will always be
smaller than expected while capacitances will always be larger → oversize
 try to set all currents to be integer multiples of a given bias current
 use a current mirror based biasing scheme instead of voltages
 iteratively simulate and optimize the design until all specifications have been met
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
23
The folded cascode opamp
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The folded cascode opamp
 another typical opamp architecture → a differential amplifier followed by a current
buffer and a cascode output stage for large Rout
 an additional output voltage follower may be used if the load is not strictly capacitive
 no need for frequency compensation (more on this later)
 elementary amplifier stages → a single V-I and I-V conversion pair
I-I
cascade of elementary stages
(transconductance, common gate
and transimpedance)
I-V
V-I
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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The folded cascode opamp
 the small signal low frequency model with two equivalent stages
 no capacitive effects → low frequency or DC voltage gain
 the current buffer → a subsequent I-V and V-I conversion pair with Rp and Gmp adjusted
to provide a unity current gain
V p1
Vp 2
Gm  g m1,2

a0  Gm Rout
R  1  1
 p G
g m 6,7
mp

 R   g r r  ||  g r r 
m 9 DS 9 DS 11
m 7 DS 7 DS 5
 out
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
26
The folded cascode opamp
 the small signal high frequency model → consider the load and the dominant parasitic
capacitances
C p1  C p 2  CDB1  CDB 4  CGD 4  CSB 6  CGS 6


C p1 C p 2

C p 

2
2
a( s) 
a0
1  sRout CL  1  sR pC p 
Since Rout>>Rp and CL>>Cp, the poles are always
separated and the phase margin will be typically large
(mφ>70°), even if mirror singularities are considered
No need for frequency compensation
→ the circuit typically works at
larger frequencies than the stable two
stage opamp
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
27
The folded cascode opamp – frequency response
One dominant pole and one
high frequency pole (mirror
singularities neglected):
a0  Gm Rout

1
 f p1( d ) 
2 Rout CL


Gmp
1
 f p2 

2 R p C p 2 C p

GBW  a0  f p1( d ) 
Gm
2 CL
 GBW
m  90  arctan 
 f p2

Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures



28
The folded cascode opamp – step response
 assume unity gain negative feedback and apply an input step to the follower
A( s ) 
 step response calculated as Vout (t )  L 1 
 s 
 Slew Rate (SR) → variation rate of the output voltage
V
SR 
t
 large phase margin → no overshoot
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
29
The folded cascode opamp – slew rate
 the total capacitance of every node must be charged and discharged in each cycle
 charging rate depends on the largest current supplied to the node capacitances
 the folding node is charged rapidly → SR limited by the output node
SR 
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
IB
CL
30
The folded cascode opamp design algorithm
 Step 1 → calculate the required input stage transconductance
GBW 
Gm1
2 CL
Gm1  g m1,2  2  GBW  CL
 Step 2 → calculate the required input stage bias current
SR 
I
IB
 3
CL CL
I 3  SR  CL
 Step 3 → calculate the VDSat1,2 voltage and the differential transistor pair geometry
g m1,2 
22II D1,2
VDSat1,2

I3
VDSat1,2
W 
 
 L 1,2
VDSat1,2  g m1,2  I 3
 Step 4 → choose VDSat3 and calculate the geometry of M3
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
W 
 
 L 3
31
The folded cascode opamp design algorithm
 Step 5 → choose ID6,7=ID8,9=ID10,11=(1.5....2)·ID1,2 to avoid completely turning off the
cascode stage when the opamp is slew rate limited (all I3 flows through M1 or M2)
I D 6,7  1.5....2   I D1,2
I D 4,5  I D1,2  I D 6,7   2.5....3  I D1,2
 Step 7 → choose VDSat for all transistors (except M1, M2 and M3) and determine the
geometries
Further ideas:
 remember the body effect and the parasitic capacitances → Gm-s will always be
smaller than expected while capacitances will always be larger → oversize
 try to set all currents to be integer multiples of a given bias current
 use a current mirror based biasing scheme instead of voltages
 iteratively simulate and optimize the design until all specifications have been met
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
32
Bibliography
 P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002
 B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002
 D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996
 P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated
Circuits, Wiley,2009
 R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rd edition, IEEE Press, 2010
Analog Integrated Circuits – Fundamental building blocks – Basic OTA/Opamp architectures
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