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A 1.2 V, 0.84 pJ/Conv.-Step Ultra-low Power Capacitance to Digital Converter for Microphone based Auscultation Neelakantan Narasimmanǂ*, Dipankar Nagǂ, Kevin Chai Tshun Chuanǂ, and Tony T. Kim* ǂ Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore *VIRTUS, IC Design Centre of Excellence, School of EEE, Nanyang Technological University, Singapore Abstract— In this paper, we propose a novel Capacitance to Digital Converter (CDC) architecture using a second order continuous time delta-sigma modulator (CT-ΔΣM) with multi-bit quantization. The proposed architecture embeds a Capacitance to Voltage Converter (CVC) in the delta-sigma loop for improving the dynamic range and the energy efficiency of the CDC. VCO-integrator/multi-bit quantizer, used as one of the loop filters, helps in reducing the swing at the output of CVC. Measurement results from a test chip fabricated in 0.18 µm CMOS technology show that the CDC achieves 13-bit resolution with a measurement time of 0.125 ms while consuming only 42 μA at 1.2V. This corresponds to a state-of-the-art figure-of-merit (FoM) of 0.84 pJ/conversion-step. Keywords— Capacitance to Digital Converter, Capacitive Sensor Interface, Delta-Sigma Modulator, VCO-based integrator. I. INTRODUCTION Early detection of subtle disorders in the human heart may be done using a non-invasive, highly sensitive, portable cardiac sound recording system. Capacitive MEMS microphones, whose capacitance is modulated by the acoustic pressure wave caused by heart sound, are promising candidates for the recording system. The energy consumption in the recording is dominated by that of the interface circuit that converts a capacitance value to a digital output. Recently several ultralow power energy efficient CDCs have been reported [1-5]. Even though period modulation based CDC could achieve higher resolution [2], additional overheads such as larger measurement time and high-resolution time reference decrease the overall energy efficiency. Delta Sigma (ΔΣ) modulation is another popular technique when high resolution is desired. Discrete Time ΔΣ Modulators (DT-ΔΣM) are predominantly used for the same [3-5]. However, there are two main disadvantages for this technique. The sampling operation at the input of the DT-ΔΣM causes noise folding and results in increased KT/C noise [7], thereby reducing SNR. Although SNR can be improved by increasing the over sampling rate (OSR), it degrades energy efficiency. Secondly, DT-ΔΣM employs a sensing capacitor as the sampling capacitor. Hence, large off-chip and parasitic capacitors are charged and discharged at the same rate as the sampling frequency, which consumes additional energy. However, Continuous-Time ΔΣ Modulators (CT-ΔΣM) do not have these problems and are This work comes from the joint project between NHCS and IME and supported by A*STAR grant no. 1421480021. 978-1-5090-5191-5/17/$31.00@2017 IEEE VDD CP1 RPSEUDO CX CF CP2 CREF VCM VOUT + Fig. 1 Capacitance to voltage convertor based on charge balancing widely used because of their low power capabilities. Existing CT-ΔΣM, however, needs an additional CVC, which limits the noise performance and the dynamic range of the CDC. In this paper, we propose a novel CT-ΔΣM that embeds CVC inside a second order ΔΣ modulator for better energy efficiency. This work also employs dual VCOs as an integrator, which provides multi-bit quantization that alleviates the output swing/biasing current requirements for the amplifiers. II. PROPOSED CDC ARCHITECTURE USING CT-ΔΣM A. Conventional capacitance to voltage conversion Fig. 1 shows a conventional CVC that performs charge balancing. The sensor capacitor, CX, and a reference capacitance, CREF are connected in series between VDD and GND. CREF could be selected to cancel out any baseline capacitance of the sensor. CF is the feedback capacitor, RPSEUDO is a bias resistor and CP1 and CP2 are parasitic capacitances associated with the sensor capacitor plates. The negative feedback in the amplifier sets the virtual ground to VCM, i.e. VDD/2. By virtue of charge balancing, the difference in charge contained in CX and CREF is stored in CF. The output voltage of the amplifier, VOUT, can be derived by VOUT = ((CREF-CX)/CF) ∙ VDD/2 + VDD/2. (1) Note that the output voltage is indicative of the sensor capacitance and immune to CP1 and CP2. A traditional ΔΣ modulator could be used for digitizing the output voltage of the CVC. However, this approach suffers from two major disadvantages. Firstly, the maximum voltage swing achievable at the output of CVC sets the dynamic range of the CDC. Since the voltage swing at the CVC output is limited by the SW<0:N> SWB<0:N> supply/ground rails, as per (1) the maximum capacitive signal gain obtainable for the CVC is unity. Secondly, noise contributions from both CVC and the first integrator of the CT-ΔΣM are decisive in achieving desired SNR. Thus both stages need to meet respective noise requirements at the cost of additional current consumption. RPSEUDO CX 0 CF - CDAC<0:N> 1 VCM CREF + - CIN VOUT + ʃ N Fig. 2 Proposed CT-ΔΣM with embedded CVC B. Proposed CT-ΔΣM structure with embedded CVC In the proposed structure, the CVC performs delta operation inside a CT-ΔΣM as depicted in Fig. 2. Multi-bit output from the quantizer is feedback to the CVC using a capacitive DAC, CDAC<0:N>. One end of each unit capacitor in CDAC is tied to the floating node while the other end is switched between VDD and GND depending on the previous output through a switch, SW/SWB. The switch when set to 1 or 0, positions CDAC parallel to either CX or CREF respectively, which in turn balances the charge for all the capacitances connected to the virtual ground. With every switching, CDAC is charged/discharged from -VCM to VCM or vice versa. Hence, the amount of charge pumped in or out by CDAC for every switching is ±CDAC∙2∙VCM. Therefore, the output of the amplifier from (1) becomes VOUT = [(CREF -CX ± 2∙CDAC)/CF] ∙ VDD/2 + VDD/2. (2) If 2∙CDAC corresponds to the quantized value of CX from the previous sampling interval, then the circuit in Fig.2 performs the delta operation in the ΔΣ modulator. The voltage swing at the output of CVC, which now accounts for the difference between CX and CDAC, is hence reduced. This provides two inherent advantages. Firstly, the dynamic range of the CDC is improved as the output swing of the CVC becomes larger. Secondly, the capacitive signal gain for the CVC could be larger than unity, which alleviates the noise requirements of CVC + - VCO Integrator RC Integrator 2 1 __ 4S + - 2 __ DOUT S 0.75 Fig. 3 Architecture for the 2nd order CT-ΔΣ Modulator the integrator. Even though a larger value of capacitance CF is desirable in terms of noise and dynamic range, it would increase the swing at the output of the CVC. Thus, choosing an optimal value of CF enhances the energy efficiency of the proposed CDC architecture. C. Proposed CDC architecture using second order CT-ΔΣM with multi-bit quantization The proposed architecture showing CVC embedded in a second order ΔΣ loop is illustrated in Fig.3. The coefficients for CVC, loop filter and the feedback DAC corresponds to a normalized sampling frequency of 1Hz. An active-RC integrator and a VCO-integrator realize the loop filters for the modulator. A cascade of integrators with distributed feedback (CIFB) topology is employed to keep the inputs to the VCO within its linear range of operation. The CVC is designed with a voltage gain of two so that noise requirements of the amplifier used in the RC integrator could be relaxed. The coefficients of the active-RC integrator and the current DAC are determined to reduce the swing at the output of the active RC integrator by half. The VCO-integrator yields a 5-bit quantized output, which is fed back to the CVC using a multibit capacitive DAC. Since cardiac auscultation demands recording over a nyquist bandwidth of 4 kHz, the modulator is designed for an OSR of 125 with a 1MHz sampling clock. III. CIRCUIT IMPLEMENTATION OF THE PROPOSED CDC A. Schematic of the proposed CDC The schematic implementation of the proposed CDC is shown in Fig. 4. Two single-ended capacitive sensors are arranged in a full bridge configuration with differential chopping so that they imitate a differential sensor. A large pseudo resistor is used to set the DC bias at the input of the amplifier. This adds an undesired zero with the capacitor CF at the frequency around a few tens of Hz, which increases the inband quantization noise at the output. To mitigate this problem, the capacitive input is chopped to a higher frequency at the input to the CVC and chopped back at the output of the CVC. Since chopping could also reduce the input offset and lowfrequency flicker noise of the op-amp, the chopping frequency is chosen to be larger than the flicker corner of the op-amp. In the proposed CDC implementation, we have used a chopping frequency of 15.625 KHz. Lowering VDD increases the mismatches in the chopping switches. Therefore, Utilizing a lower chopping frequency reduces the distortion added by the mismatches in the chopping switches. The output of the CVC is integrated using an active RC integrator. Even though noise requirements of the integrator are alleviated by the gain of the CVC, the input offset and the flicker noise from the amplifier could degrade the overall SNR. Hence, the active-RC integrator is also chopped. Unlike the CVC, the amount of charge handled by the chopping switches for RC-integrator is much lesser. This enables us to use a higher chopping frequency of 500 KHz. A dual VCO-based integrator is used as the second integrator [6]. The phase of a VCO is proportional to the integral of its input. Thus, the VCO can act as a linear integrator if its input is within its linear range. Comparing the phase outputs of the dual VCOs with the differential inputs gives integral of the input. Sampling this multi-phase output Charge Balancing CF VCO Integrator & Quantizer IDAC 2 CINT IDAC 2 CX 0 Chop 1 + - - Cho CREF p Chop RINT CF 31 Stage VCO - + 31 31 Stage VCO D DOUT DFF 31 CLK <0:30> <0:30> CINT SW VBIAS1 31 SWB VBIAS2 RPSEUDO 31 RIN SW CDAC 1 <0:30> CREF + + SWB CX RIN - Chop 0 RINT - + Chop CDAC Chop SW<0:30> SWB<0:30> Chop RPSEUDO SW<0:30> SWB<0:30> NRZ Current DAC DAC Driver Fig. 4 Schematic details of the proposed CDC : 0.75 M1 V+ VCMFB VV+ : M2 M0 Vout+ - M9 0.75 Vout- A 1 : 3.5 VVCMFB VBIAS M8 Vout- Vout+ 1 M4 M10 RCM RCM The test chip was designed and fabricated in a commercial 0.18 µm CMOS technology. The die photograph is illustrated : M6 + IV. MEASUREMENT RESULTS 3.5 M5 M3 A + VCMFB + B. Symmetric cross-coupled OTA Symmetric cross-coupled OTA, as illustrated in Fig. 5, was used for designing CVC and an active-RC integrator. This OTA topology was chosen considering its large gain bandwidth and ability to drive resistive loads with given amount of current. Cross-coupled transistors M5 and M6 offer a negative gm, and boost the DC gain of the OTA. Since transistors M3-M6 were the predominant contributors for the flicker noise, PMOS transistors were used for the same. A pair of resistors and a single-ended differential amplifier sets the output common mode voltage. Owing to the CIFB architecture, the OTA output swing used in the active-RC integrator is large. Consequently, output chopping for the active RC integrator was performed at node 'A' as indicated in Fig. 5. This helps in minimizing the distortions added by the chopping. The amplifier for the CVC has the DC gain of 52dB and the unity gain bandwidth of around 10 MHz with the current consumption of 21 μA. The OTA for the RC integrator is designed for a DC gain of 40dB and unity gain bandwidth of 4MHz with a total current consumption of 14 μA. M7 - using a D-Flip-flop (DFF) quantizes the phase in the time domain. Each VCO consisting of 31 stages of differential inverters performs 5-bit quantization. The multi-bit NRZ current DAC used in the feedback path keeps the input to the VCO within the linear range of the VCO. A 5-bit output is fed back to the CVC using a capacitive DAC. The output of the VCO-based integrator is inherently Clocked Level Averaged (CLA), which is one form of Dynamic Element Matching (DEM) technique [6]. The CLA output of the VCO modulates any nonlinearity arising from the DAC mismatches around twice the center frequency of VCO. The active-RC integrator provides first order shaping for the intrinsic noise contribution from the VCO obviating the need for additional noise reduction techniques. - VCM Fig. 5 Symmetric cross-coupled OTA with CMFB in Fig. 6(a). The chip occupies an active area of 0.42mm2. Since the actual sensor for microscope-based auscultation was not available, two measurement setups were used to gauge the performance of the sensor. Commercial pressure sensor [8] was used off-chip to take measurements from a controlled pressure chamber. The digital output from the CDC, which represents the measured pressure, is filtered and decimated off-chip at rate of 125. A box-plot illustrating the mean and variance of pressure measurement across 100 decimated output samples is presented in Fig. 6(b). The proposed design could sense pressure changes as small as 0.24 mmHg. To measure the noise and distortion performance across 4 KHz bandwidth, sinusoidal testing was carried out on a slightly modified replica design. A 10 pF static capacitance excited 0 19.2 18.454 CVC 830µm VCO INTEG RC INTEG Decimated output (#) 19 18.8 18.45 18.448 18.6 18.4 Sinusoid Input Fixed capacitance DAC Mismatches -40 -60 -80 -100 18.2 18 CVC Chopping -20 18.452 Ampitude [dBFS] 500µm σ = 0.0012 750 800 850 900 950 Pressure (mmHg) (a) (b) -120 2 10 10 3 10 4 Frequency (Hz) 10 5 10 6 (c) Fig. 6 (a) Die photograph, (b) box-plot illustrating the decimated output from the CDC, and (c) measured FFT Spectrum. TABLE I PERFORMANCE COMPARISON Parameter Process (nm) [2] [3] [4] [5] This work 160 180 350 350 180 Period DT- DT- DTMethod CT-ΔΣM Mod: ΔΣM ΔΣM ΔΣM Input range (pF) 0-8 0-24 NA 0.5-1 0-10 Measurement Time(ms) 6.86 0.23 0.02 0.8 0.125ǂ SNR (dB) 80.6 94.7 104.7 69.6 79.2 Power (µW) 14 33.7 15000 10.3 50.4 FoM* (pJ/Conv.-Step) 10.6 0.175 5.5 3.4 0.84 *FoM = Power ˣ Measurement Time/ 2ENOB ǂ Corresponds to 4 KHz Bandwidth with a sinusoid input emulates a sinusoidal change. Hence a differential sinusoid with 500 mVpp amplitude at 1.34 KHz frequency, which corresponds to the capacitance change from 0.8 pF to 9.2 pF at the same frequency, was used for measurement. Fig. 6(c) demonstrates the FFT spectrum for 214 output samples, convolved with a Hanning window. Similar FFT spectrum measured for static capacitance of 10 pF is superimposed in the same figure. The output spectrum shows the chopping spurs at 15.625 KHz and the up-converted DAC mismatches around twice the center frequency of the VCO. The proposed CDC achieves an SNR of 79.2dB over its full range of 0-10 pF corresponding to an effective resolution of approximately 0.4 fF. The CDC consumes 42 μA at 1.2 V supply resulting in a FoM of 0.84 pJ/Conv.-step. Table-I compares the proposed CDC design with several state-of-theart ones. Even though the design proposed in [3], using zoomin architecture with coarse and fine quantization, reports lower FoM, its usability is limited to slow changing or static capacitance measurements. V. CONCLUSION In this paper, we introduced a novel CDC utilizing CTΔΣM. The proposed continuous time implementation alleviates the noise requirements of the circuit components, thereby reducing current consumption. The VCO-based integrator/ quantizer help to reduce the voltage swing at the output of the CVC, which improves energy efficiency and dynamic range. The test chip fabricated in 0.18 µm technology demonstrates that measuring capacitance using CT-ΔΣM achieves better FoM over existing DT-ΔΣM or period modulation techniques. The proposed design could be interfaced with capacitive MEMS microphone for auscultation purposes or other capacitive sensors for ultra-low power applications. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] J. Wanyeong, J. Seokhyeon, S. Oh, D. Sylvester, and D. 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