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Special Features of PIC 16F877 Configuration Bits • The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. • The erased, or unprogrammed value of the configuration word is 3FFFh. • These bits are mapped in program memory location 2007h. • It is important to note that address 2007h is beyond the user program memory space, which can be accessed only during programming. Oscillator Configurations • The PIC16F87X can be operated in four different oscillator modes. • The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: – LP Low Power Crystal – XT Crystal/Resonator – HS High Speed Crystal/Resonator – RC Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS • In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation. • When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin RC OSCILLATOR • For timing insensitive applications, the “RC” device option offers additional cost savings. • The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. • The user also needs to take into account variation due to tolerance of external R and C components used. RESET • The PIC16F877 differentiates between various kinds of RESET – Power-on Reset (POR) – 𝑀𝐶𝐿𝑅 Reset during normal operation – 𝑀𝐶𝐿𝑅 Reset during SLEEP – WDT Reset – WDT Wake-up (during SLEEP) – Brown-out Reset (BOR) • The 𝑇0 and PD bits are set or cleared differently in different RESET situations • These bits are used in software to determine the nature of the RESET in different RESET situations SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-On Reset (POR) • A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). • To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. • This will eliminate external RC components usually needed to create a Power-on Reset. Power-up Timer (PWRT) • The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. • The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. • The PWRT’s time delay allows VDD to rise to an acceptable level. • A configuration bit is provided to enable/disable the PWRT. • The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. Oscillator Start-up Timer (OST) • The Oscillator Start-up Timer (OST) provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT delay is over (if PWRT is enabled). • This helps to ensure that the crystal oscillator or resonator has started and stabilized. • The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or Wake-up from SLEEP. Brown-out Reset (BOR) • The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. • If VDD falls below VBOR (about 4V) for longer than TBOR (about 100μS), the brown-out situation will reset the device. • Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. • The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit. Time-out Sequence • On power-up, the time-out sequence is as follows: The PWRT delay starts (if enabled) when a POR Reset occurs. • Then OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). • When the OST ends, the device comes out of RESET. Power-down Mode (SLEEP) • Power-down mode is entered by executing a SLEEP instruction. • If enabled, the Watchdog Timer will be cleared but keeps running, the 𝑃𝐷 bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. • The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance). • The following peripheral interrupts can wake the device from SLEEP: – PSP read or write (PIC16F874/877 only). – TMR1 interrupt. Timer1 must be operating as an asynchronous counter. – CCP Capture mode interrupt. – Special event trigger (Timer1 in Asynchronous mode using an external clock). – SSP (START/STOP) bit detect interrupt. – SSP transmit or receive in Slave mode (SPI/I2C). – USART RX or TX (Synchronous Slave mode). – A/D conversion (when A/D clock source is RC). – EEPROM write operation completion I2C System Overview • The I2C system communicates on the “SCL” and “SDA” pins • The “SCL” is the clock and the “SDA” is the data line • I2C module can operate in master mode or slave mode • Slave device has a unique “address” code I2C System • The slave’s addresses may be either 7-bits long or 10-bits long • The slave devices in the I2C system cannot initiate a data transfer to the master • For example, for simplicity we are working with 7-bit slave addresses • Suppose that the master in the I2C system wants to write data to a slave • The master first looks for activity on the “SDA” and “SCL” lines to see if another master device is using the system. • If and when there is no activity, the master sends out 9 clock pulses on the “SCL” line and sends out 8 bits on the “SDA” line • The eight bits are the 7-bit slave address and a “read/write” bit which is set (=1) for a “read” or reset (=0) for a “write”. • Then the master holds the “SDA” line “high” (=1) and looks for an “acknowledge” state from the slave also on the “SDA” line • If the slave acknowledges the master, it will bring the “SDA” line to ground, or “low” (=0), and the master will proceed to send its data