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PIC microcontroller: All microcomputer systems based on building blocks. These are shown in Figure 1 and consist of the following: CPU - the part that does all logic and arithmetic functions RAM - storage for programs and/or program variables ROM - read-only parts of programs I/O - connection to external devices Figure1.6: Basic building blocks of Computer Figure 1.7: Microcontroller Based System The CPU or microprocessor is the core component of any microcomputer and it requires the external components such as the ROM, RAM and I/O etc. 1. The processor Registers : Storage locations in the processor Arithmetic logic unit Control unit program counter contains the address of the next instruction to be executed status register flags the instruction execution result. 2. The microprocessor A processor implemented on a very large scale integration (VLSI) chip Peripheral chips are needed to construct a product. 3. The Microcontroller The processor and peripheral functions implemented on one VLSI chip. PIC 18 microcontrollers is of 16 bit. There are various PIC 18 families that share the same instruction set and the peripheral design. The PIC microcontroller is a single chip consists of CPU, Memory I/O ports, timers and other peripherals. Features of the PIC18 microcontroller 1. PIC 18 is a 8-bit microcontroller 2. It is having 2 MB program memory space 3. The data memory organization is from 256 bytes to 1KB of data EEPROM Up to 3968 bytes of on-chip SRAM 4. PIC 18 micro controller consist of flash program memory 4 KB to 128KB 5. It consist of sophisticated timer functions that include: input capture, output compare, PWM, real-time interrupt, and watchdog timer 6. There are different Serial communication interfaces: SCI, SPI, I2C, and CAN 7. PIC 18 is of 10-bit A/D converter 8. The important feature is Memory protection capability 9. Instruction pipelining Architecture of the PIC microcontroller PIC18F8720 has internal 8-bit data bus connecting all the peripherals as shown in fig. Let us discuss each of these blocks along with their associated pins .There are three memory blocks in each of the PIC18F87XA devices. The program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is “Data EEPROM and Flash Program Memory 1. Program Memory Organization The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x 14 bit .Program memory space. The PIC16F876A/877A devices have 8K words x 14 bits of Flash program memory, while PIC16F873A/874A devices have 4K words x 14 bits. Accessing a location above the physically implemented address will cause a wraparound. 2. 8 Level Stack It is provided for sorting the return address in program counter, and hence the RAM is not to be used for purpose since the stack size is 8 levels, it can be store up to 8 return addresses and hence up to 8 levels of nested execution can be handled. Figure 1.8: Block Diagram of PIC 18F877A 3. Data RAM Internal data RAM is also provided whose data lines are connected to the system data bus, while the address is taking through FSR, a file select registers that provide the 8 bit address required to access the RAM. The address may be provided in the instruction itself; hence the Instruction Register (IR) is also one of the inputs. A bank select register is also connected. 4. ALU The ALU gets one of the input operand from W register or IR. The other operand may be given either from register or memory location, and hence the other input side of ALU is connected to the internal data bus. 5. The PIC18 has multiple reset mechanisms. The PIC 18F877 devices differentiate between various kind of reset : a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during sleep d) Watchdog Timer (WDT) Reset during normal operation e) Programmable brown-out Reset(PBOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Description of above is as follows: a) Power-on Reset (POR): A Power on Reset pulse is generated on-chip when VDD rise is detected b) MCLR Reset during normal operation/ MCLR Reset during sleep: This pin is cleared during normal operation or sleep, the PIC18F device restart. c) Watchdog Timer (WDT) Reset during normal operation : A WDT is a device that continuously keeps on counting .The programmer should write the program in such a way that it continuously reset this timer, because if timer overflows it resets the processing. If this timer doesn’t resets it indicates that the process has hanged. d) Programmable brown-out Reset(PBOR): A configuration bit, BOREN can enable or disable the Brown-out Reset circuitry. If VDD falls below a particular voltage it can cause abrupt behavior of processor. This voltage level is called as Brown-out level or BVDD. The chip will remain in Brown-out Reset until VDD rises above BVDD 6. I/O ports: There are five I/O (Ports A, B, C, D, and E) ports available on PIC 18F877A device. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device .Each port have three registers for its operation. These registers are: 1. TRIS Register (Data direction Register) 2. PORT Register (Read the levels on the pin of device) 3. LAT Register (Output latch): The data latch (LAT register) is useful for readmodify-write operations on the value that the I/O pins are driving. 7. Timers: There are three Timer of 8-10 bit with different features in each of them like support for Compare, Capture and PWM.The Timer0 module timer/counter has the following features: 1. 8-bit timer/counter 2. Readable and writable 3. 8-bit software programmable prescaler 4. Internal or external clock select 5. Interrupt on overflow from FFh to 00h 6. Edge select for external clock • CAPTURE/COMPARE/PWM MODULES: Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle registers Both the CCP1 and CCP2 modules are identical in Operation, with the exception being the operation of the special event trigger. a) Capture Mode: In Capture mode, CCPR1H:CCPR1L captures the 16-bit values of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge b) Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged c) PWM Mode (PWM) In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. 8. ANALOG-TO-DIGITAL CONVERTER (A/D) : The analog digital converter module 16 for the PIC 18F8x20 devices. The module allows conversion of analog input signal to corresponding 10-bit digital number. There are three control registers to do control various operations of the ADC like selecting one of the 16 input channels, enabling or disabling the ADC, reference voltage source etc. There are two registers to hold the lower 8-bit and the upper 2bit of digital equivalent. 9. Analog Comparator This comparator can compare two analog voltages. The input to the comparator is multiplexed with the pins RF1 to RF6 .A single comparator is along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure represent the uncertainty due to input offsets and response time. Figure 1.9: A single Comparator SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four Modes of SPI are supported. To accomplish communication, typically three pins are used: • Serial Data out (SDO) – RC5/SDO • Serial Data In (SDI) – RC4/SDI/SDA • Serial Clock (SCK) – RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RA5/AN4/SS/C2OUT 10. UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that Can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) The PIC18 Memory Organization 1. Data Memory and Program Memory are separated 2. Separation of data memory and program memory makes possible the 3. Simultaneous access of data and instruction. 4. Data memory are used as general-purpose registers or special function registers On-chip Data EEPROM are provided in some PIC18 MCUs. Data Memory and Program Memory Implemented in SRAM and consists of general-purpose registers and Special-function registers. Both are referred to as data registers. A PIC18 C 8 MCU may have up to 4096 bytes of data memory. Data memory is divided into banks. Each bank has 256 bytes. General-purpose registers are used to hold dynamic data. Special-function registers are used to control the operation of peripheral functions. Only one bank is active at any time. The active bank is specified by the BSR register. Bank switching is an overhead and can be error-prone PIC18 implements the access bank to reduce the problem caused by bank Switching. Access bank consists of the lowest 96 bytes and the highest 160 bytes of the data memory space. There are two sets of registers, General-Purpose Register(GPRs) and Special Function Register(SFR).GPR are used to hold user random data when the PIC18 is executing a program .SFR are control registers used for CPU and on chip peripheral devices. The SFR begin from the lowest address and go upward, whereas GPR must be used from highest address and go upward. The first 32 bytes are SFR and remaining is GPR. Figure 1.10: PIC PIC18 Data Memory and SFR basics Program Memory Organization The program counter (PC) is 21-bit long, which enables the user program to access up to 2 MB of program memory. The PIC18 has a 31-entry return address stack to hold the return address for subroutine call. After power-on, the PIC18 starts to execute instructions from address 0. The location at address 0x08 is reserved for high-priority interrupt service routine. The location at address 0x18 is reserved for low-priority interrupt service routine. Up to 128KB (at present time) of program memory is inside the MCU chip. Part of the program memory is located outside of the MCU chip. Figure 1.11: Program Memory Space of PIC18F877