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Analog Layout Exercise
Building a Simple Operational Amplifier
Introductory exercise for the MSc. course System Design Laboratory where detailed circuit
and layout design has to be done for an analog circuit – mostly an operational amplifier
(OpAmp), -- which was previously specified on system level,. This exercise demonstrates the
basic steps of analog integrated circuit design and introduces the students to working with the
design tool. The exercise, if well prepared, can be performed in the course of a 4 hours laboratory session. The participants are supposed to have a working knowledge of the Virtuoso
Schematic Editor. (The preceding preparations include "getting familiar" with the task and
after the session the final specification and documentation has to be done.)
Tool:
Cadence 6
Technology:
AMS 0.35µm
Dr. Peter Gärtner
Department of Electron Devices
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Contents
1. The schematic diagram of the task
3
2. Preparation of the circuit diagram
3
3. Checking the properties by simulation
4
3.1. Prepare a symbol
5
3.2. Construction of the test-bench
5
3.3. Analyses by simulation
6
a) DC transfer characteristics
6
b) Common mode amplification
6
c) Power supply rejection
6
d) Bias-current sensitivity
6
e) AC transfer characterristics
6
f) AC transfer without phase compensation 6
g) Quasi-static transient simulation
7
h) Slew-Rate
7
4. Composing the data-sheet.
7
5. Preparing the floor-plan
7
6. Preparations of the layout-editor
9
7. Placement of the components
9
7.1. Coarse placement of the N-transistors
10
7.2. Positioning
10
7.3. Placement of the P-transistors
10
7.4. Placement of the feed-back capacitor
10
7.5. Specification of the guard-ring
11
7.6. Placement of the guard-ring
11
7.7. Closing the guard-ring
12
7.8. Preliminary DRC
12
8. Routing: making the connections
13
8.1. Connecting the gates on poly1
13
8.2. Completing the connection between T3A and T3B
8.3. Further connections, N-transistors
15
8.4. Further connections, P-transistors
15
8.5. Completing the routing, metal2
16
8.6. Placement of the pins
16
9. DRC
18
10. Extract
18
11. LVS
18
12. Post-Layout simulation
19
13. Complete the documentation
19
Appendix: Full layout of the OpAmp
21
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2
1. The schematic diagram of the circuit is given.
The task is to design the layout of a simple two-stage OpAmp with phase compensation (Fig.
1.). The differential input consists of NMOS transistors – this determines the structure of the
whole circuit.
VDD
T5
T6
QN
QP
T7
INP
OUT
INN
T3
T4
CV
IB
Ubias
TB
T1
T2
Fig. 1. The circuit structure of the OpAmp
Fig. 2. (next page) shows the detailed circuit diagram, developed by LTspice. The 8 kOhm
resistor of the phase compensation is realized by the channel resistance of transistor T8 because it occupies much less silicon area. The power supply is 3 volt. The quiescent current
(operating point) is determined by an external bias current of 50 µA, provided at the pin UB.
In preparation for the exercise familiarize with the structure and operation of the circuit before
the session. Estimate the node voltages and the branch currents. Consider different testbenches that could "ask questions" to the circuit which in response would deliver important
specification data of the amplifier.
2. Prepare the circuit diagram.
Start Cadence6 (cog-wheel icon on the desktop). Establish a new library
(FileNewLibrary) with a meaningful name referring to your project. All the cells defined
in the project will be stored here. For the new library Cadence requests the specification of a
technology. Select Attach to an existing technology library and in the window Attach Library
to Technology Library specify TECH_C35B3. Open a new cell in the Library Manager
(FileNew Cell, view=schematic) and construct in this cell the circuit of Fig. 2. It is recommended to use the instance and node names of Fig. 2. Fetch the transistors n4 and p4 from
the library PRIMLIB and the phase compensation capacitor CV has to be realized with the
capacitance cpoly. Other components for the test-bench you should find later in the library
analoglib.
Cadence does not use the multiplication factor mm. Instead, the instance name has to be
formed as an array of two elements using the addition of <0:1> (e.g. T7<0:1>). The comparison of the schematic and the layout (LVS) can only work correctly if both networks, the
netlist of the schematic and that extracted from the layout consist of strictly the same number
of components.
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CX
Fig. 2. Circuit diagram of the amplifier
(drawn with the schematic editor of LTspice)
3. Checking the properties of the circuit by simulation
In this exercise the circuit is given. Its specification has to be determined by running detailed
simulations. For this purpose a simulation environment has to be constructed.
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3.1. Prepare a symbol.
The hyerarchical symbol (icon) has to be prepared, which enables the placement of an instance of the amplifier into the test-bench. This operation can be started from the Schematic
Editor: CreateCellviewFrom Cellview
In the window which opens you have to specify From Schematic and To Symbol. The program offers the choise for the placement of the pins of the amplifier. The inputs should be on
the left, the output on the right, and VDD as well as the bias current input UB on the top. The
graphic symbol editor opens and the program automatically generates a rectangle-shaped
symbol. However, the usual form of an OpAmp-symbol is a triangle. Therefore, the rectangle
should be deleted from the drawing and a triangle should
be made by the command
DrawShapePolygon
Then the pins have to be adjusted to the triangle. The last
step is the creation of the embordering rectangle by the
command CreateSelection Box, in Automatic mode.
Then, after saving, both windows of the Symbol Editor
and the Schematic Editor can be closed. The program
automatically stores the symbol in the library as a new
view beside the schematic of the OpAmp (Fig. 3.).
Fig. 3. The symbol of the OpAmp
3.2. Construction of the test-bench.
Open a new schematic cell in the Library Manager (FileNewCell). The name of the new
cell should be that of the OpAmp with a pre- or suffix of tb separated by an underscore. Using
the command CreateInstance invoke the recently built icon and place it in the right half of
the window. This is the first element of the test-bench. Further components have to be added
Fig. 4. The test-bench of the OpAmp.
In the first runs the sources are vdc and idc.
as it is shown in Fig. 4. using the same node-names. This is a universal test-bench circuit for
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fication of differential as well as common mode input signals and performing almost all openloop examinations with appropriately selected signal sources.
3.3. Analyses by simulation.
The recently completed test-bench is capable of performing four DC-sweep analyses without
modifications. The Virtuoso Simulator has to be started from the Schematic Editor Window
(LaunchADE L). Invoke the mode-selecting window: AnalysesChoose…Here select DC
mode, and in the field Sweep Variable activate the button Component Parameter. Returning
to this very point you should analyze the dependance of the behaviour of the circuit upon the
signals of all four generators.
a)
First of all analyze the differential transfer characteristics. The generator to be swept is
VDIF. Write /VDIF into the field Component Name. The name of the parameter is dc.
The voltage swing extends from -100µV to +100µV, the step is 1µV. Sweep Type has
to be set linear. The specified simulation mode should be enabled by the button Enable and then a finishing OK closes the window. The next step is choosing signals for
displaying. In the Virtuoso window activate OutputsTo Be PlottedSelect from
Schematic. The Schematic Editor window comes up and you can select signals by
clicking on the leads. Click on the OUT lead. The selection is acknowledged by changing the color of the lead. (A click on a terminal of a component selects the current
flowing into the terminal and is acknowledged by a colored ring around the terminal.
An inadvertent click can be undone by a second click on the same spot.) Return to the
Virtuoso window. In the field Outputs the name of the selected node (pin) appears
with the column Plot activated. Activate the column Save, too. Now the simulation can
be started by clicking on the green spot on the left. After a successful simulation run
the Waveform window opens with the differential transfer characteristics of the amplifier. Click at MarkerPlaceTrace Marker to add a marker for the curve and add
another one by clicking MarkerAdd Delta. Set the markers to VDIF = ±10µV and
determine the differential amplification factor.
b)
Similarly, study the common mode behaviour of the amplifier. In the Analyses field of
the Virtuoso window activate the Choosig Analyses window. Change the sweeping
generator to /VCOM. The voltage has to be swept from 1 to 2 volts with 1mV steps.
Run the simulation. Then set markers to 1.4 and 1.6 volts and determine the common
mode amplification factor (it is lower than 1!).
c)
Similarly, check the influence of the power supply, /VDD should sweep 2.5–3.5 volt.
d)
The last DC-sweep is the check of the output as a function of the bias current. The
generator IB should be swept from 40µA to 60µA in steps of 1µA.
e)
With just a little modification you can use this test-bench to determine the AC transfer
characteristics, too. Select the generator VDIF by a left click and depressing q invoke
its property sheet. Write 1 in the AC field (unit AC input voltage) and give OK. Start
the simulator Virtuoso and select AC simulation mode. In the opening fields specify
the frequency range from 1Hz to 1GHz, in logarithmic mode, 30 points per decade.
Activate the Enable button and give OK. Back in the Virtuoso window the simulation
has to be started. The result will be displayed in the Waveform window, only the absolute value in linear mode. In the Virtuoso window activate ResultsDirect
PlotMagnitude and Phase by a left click. The Schematic Window comes up with the
schematic of the OpAmp. Select the lead OUT by a left click so its color changes.
Now depress ESC. In the Waveform Window the Bode diagram appears, the amplification in dB and the phase linear.
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f)
g)
h)
Now modify the value of the feed-back capacitor CV to 1fF (this is practically open
circuit, the feed-back is switched off) and repeat the AC simulation at this setting.
Compare the Bode diagrams and restore the original value of CV.
The next analysis is a quasi-static transient simulation which gives a very good overview of the amplification properties of the circuit depending upon the common-mode
input voltage. Put aside the present test-bench for later post-layout simulation. Make a
copy of the test-bench (FileCopy…). Replace the added tb in the name of the new
testbench by tran. Replace both simple vdc generators VDIF and VCOM by the type
vpulse, also from the library analogLib. The common mode input voltage increases
very slowly from zero to VDD. Select the generator VCOM by a left click and depressing q invoke its property sheet. Set the following parameters: beginning voltage 0V,
max. voltage 3V. Delay 0, rise time 1sec, fall time 1sec, pulse width 50µsec, periode
2.1 sec. Onto this very slow changing voltage a much quicker but still slow small signal will be superimposed. Invoke the property sheet of VDIF and set the following parameters: beginning voltage -25µV, max. voltage 25µV. Delay 0, rise time 9µsec, fall
time 9µsec, pulse width 1msec, periode 20msec. Now start the simulator and choose
transient simulation. The length of the run should be 1 sec. For display select the output signal OUT and the common-mode input voltage UCOM. Run the simulation and
zoom the time axis for the interval 400…600msec. Evaluate the results!
Determine the Slew-Rate. This is done at strong overdrive of the amplifier. Restore the
generator VCOM to the type vdc with constant 1.5V common-mode voltage. Set the
VDIF puse generator to the followings: beginning voltage -2mV, max. voltage 2mV.
Delay 0, rise time 0.1µsec, fall time 0.1µsec, pulse width 10µsec, periode 20µsec. The
lengthof run should be 50µsec. Have the output OUT and the input UP displayed. In
the Waveform Window separate the curves by activating AxisStrips.
4. Composing the data-sheet.
From the simulation data prepare the data-sheet of the OpAmp containing the following specification data:
Power supply, bias current, current consumption (static),
Amplification factor at UCOM=VDD/2,
Common mode rejection ratio CMRR (ADIFF[dB]-ACOM[dB]),
Operating range of UCOM, (The "usable" range based upon the section g)
Power Supply rejection ΔUOUT/ΔVDD
Bias current sensibility ΔUOUT/ΔIBIAS
Frequency of the first (dominating) pole, f3dB
Unity gain frequency f1, phase margin Δφm,
Slew Rate SR [V/µsec]
After the layout design the size of the cell will be added.
5. Preparing the floor-plan.
The first step is to make a scratchy placement of the components together with finding an
optimal arrangement for the wiring.
In order to have transistors of identical characterisT3B
T4B
tics the layout has to be composed using unittransistors. In addition, the identicalness of the tranT4A
sistors of sensitive circuit parts can be enhanced by
T3A
applying common centroid structures.
Fig. 5. Common centroid structure for T3-T4
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In the schematics each transistor (except T2 and T8) consists of two units (the N- and Pchannel transistors have different sizes). These can be constructed as double transistors turned
to each other, having a common source. Their hight is, according to two channel length and
the contacts, about 7-8µm. The width of N-transistors is 13-14µm, that of P-transistors is 1820µm. The differential pair T3 and T4 will be built cross-coupled, as Fig. 5. shows them.
A sketch of the complete transistor arrangement is shown in Fig. 6.:
T5
T6
T7
T5
T6
T7
T1
T3
T4
TB
T1
T4
T3
TB
T8
T2
Fig. 6. The sketch of the transistors
The P-transistors will be placed in a common N-well. With this sketch the final floorplan with
wiring can be designed. Fig. 7. shows it, in form of a stick-diagram-like sketch.
CX
IB
OUT
INP
INN
Fig. 7. The sketch of the complete floorplan
The sketch is self-explaining. METAL1 is blue, METAL2 is ocher. Black X is contact, purple
X is via. Green is the active diffusion, dashed red line shows the N-well of the P-transistors.
Printed in black-and-white the drawing is a little confusing, however, on a colored screen it is
easy to overview. Guard-rings are not included, only the contacts of the N-well to VDD are
marked. When the design will be finished, it will be engirdled by a P+ ring, connected to the
ground. The differential inputs are furnished with a via bringing the connection to the layer
METAL2 since they are blocked on the layer METAL1. The shape of the compensating capacitor CV has to be aligned to the width of the transistor block afterwards, and it will be connected to the nodes CX and OUT. (Remark: the sketch illustrates the principle that 20 and 30
µm wide transistors can be composed of 10 and 15 µm wide unit-transistors. In a "real" design even these should be halved using 5 and 7.5 µm wide unit transistors.)
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6. Preparations of the layout-editor
Start Cadence. Select the name of the amplifier in the Library Manager. Left click
FileNewCellview. The New File window opens with the name of the amplifier entered.
Set Type=layout and click OK. The Virtuoso Layout Editor opens with a new empty cell.
Before starting the work some settings have to be done. Left click OptionsDisplay. In the
field Display Controls set the number of displayed hierarchy levels (Display Levels) from 0 to
9 and activate the switches Pin Names and Instance Pins.
In the field Grid Controls set the size of the grid (X snap, Y snap) to 0.025µm and the Snap
Mode in both cases to anyAngle. The editor accepts objects only at grid points. Since the minimum distance is 350nm, and a path is specified by its middle, for setting 175nm a grid of
25nm is necessary.
The settings have to be saved together with the cell. Switch on the buttons Cellview and Save
To and click OK. Therefore, these settings will be automatically activated when the cellview
will be opened later.
The Snap Mode determines the handling of objects with reference to the grid. It is worthwhile changing it frequently when doing edition. By depressing <F3> a local menu opens for
changing it. For instance, if you want to move an object horizontally. The grid is only 25nm
and the mouse is uncertain, the object can slip a couple of vertical grids, too. So for this single
action the Snap Mode can be set to horizontal and then the system will not allow any vertical
movement.
Even so, exact positioning can be tiresome, but strong zooming can help. You can zoom in
and out either using CTRL + mouse-wheel or selecting the area to be zoomed by a right drag.
Then you can restore the previous display by typing w, or f for the full cell.
Switch on the display-control for the layers: WindowAssistantsLayers. In this window
you can select the layer on which you want to create a shape. First set all layers for display.
Later on, in an advanced situation you may want to display only the layers you are just working on. There are general switches in the upper part of the layout window:
 AV – all visible, all layers are displayed
 NV – none visible, only the activated (selected) layer is displayed
 AS – all selectable, shapes on each layer are selectable
 NS – none selectable, only shapes of the activated layer are selectable.
Display and selectability of shapes on a given layer can be controled one by one. This can be
useful when you are working on shapes which are covered by shapes on other layers and only
shapes on the uppermost layer can be selected. In such a case the "superfluous" layers can be
temporarily switched off.
Switch on the continuous design rule check function.: in the menu item OptionsDRD Edit
set Interactive Mode to Notify. So the system will automatically check the most important
(and easy to compute) rules and prompt with warning if they are violated when you are moving or drawing a shape.
Dimensions can be checked by the ruler function. After typing k you can create rulers with
scale by a left drag between points of interests. Is the check/measurement done, the rulers
disappear if you type (SHIFT+k). If the distance between two objects is given, you can draw a
ruler from the existing one, showing where to place the other one.
7. Placement of the components. The placement is not independent of the wiring. Fig. 7.
shows that the wires form the most dense web in the region of the differential pair (T3 and T4).
Therefore, these transistors (each consisting of two units) have to be placed first, ensuring just
enough room for the wires, too. This can be followed by the other N-transistors and then by
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the P-transistors. However, in this exercise, in order to simplify the task, the coordinates of
the components are given in advance.
7.1. Coarse placement of the N-transistors. Let's begin with T1. Left click CreateInstance. The Create Instance window opens. Click at Browse and find the cell nmos4
in the library PRIMLIB, set view=layout. The Create Instance window takes the form of the
property sheet of nmos4, showing its parameters. The following parameters have to be set:
Width=20u, Width Stripe=10u, Length=2u, Number of Gates=2. Switch on the Top and Bottom Contact and set Join Gates=no. Leave the other parameters at their default values. Click
at Hide. The property sheet closes and the transistor comes up, linked to the cursor.
In the editor pane the axes of the coordinate system are white lines. Bring the transistor with
its reference point in the lower left corner near the origin and place it there by a left click. The
placement mode does not change, shifting the cursor you can place further instances of
nmos4. In accordance with Fig. 7. place three more instances of the double transistor in a horizontal row, near to their final place. Then depress i for Create Instance and activate nmos4
for T2: Width=10u, Width Stripe=10u, Length=2u, Number of Gates=1. This simple transistor
should be placed at the end of the row.
7.2. Positioning. If the final coordinates (X and Y) are given then it is easy to do the final
placement. Depressing <ESC> the placement mode is abandoned. At the left lower corner of
the editor pane you can check that the mouse is again in its base (selecting) mode (mouse L:
SingleSelectPt). Now the transistor can be selected by a left click. The selection is indicated
by a dashed yellow (or white) line enclosing the contour of the transistor. Then evoke the Edit
Instance Properties window by depressing q. Activate the tab Attribute. Here you will see the
coordinates of the reference point and these can be modified as needed. Clicking OK the new
coordinates will be finalized. In the lower row the final coordinates of the N-transistors are
Y=0 and X=0, 12µ, 27µ, 39µ and 51µ.
7.3. Placement of the P-transistors. The P-transistors will reside in the second row above
the N-transistors. Find the pmos4 transistor in the Create Instance window and set the common data of the transistors T5, T6 and T7: Width=30u, Width Stripe=15u, Length=2u, Number
of Gates=2. Then place them coarse in accordance with Fig. 7. followed by T8 at the right
edge with parameters Width=4.2u, Width Stripe=4.2u, Length=2u, Number of Gates=1. Now
the P-transistors should be brought to their final place. The common Y is 10.5µ, while the X
values are 0, 17.2µ, 34.4µ and 53.8µ.
The N-wells of the P-transistors will be extended to one common N-well. Select the layer
NTUB in the Layers window. Activate the command Rectangle by depressing r. Zoom to the
lower right corner of the N-well of T8. and make here a left click. The common N-well begins
here. Bring the cursor to the upper left corner of T5 and set the coordinates X=-1.2µ and
Y=18.75µ. Finish the rectangle here with a left click. (The left edge of the rectangle should
coincide with the left edge of the N-well of T5.)
7.4. Placement of the feed-back capacitor. The next component is the CV feed-back capacitor. It is constructed by the layers poly1 and poly2 and you can find it as a parametrizable cell
in the library PRIMLIB under the name cpoly. The parameters can be specified in the Create
Instance window: Width=15.2u, Length=60.3u. The Ground Plane Right Contact as well as
Top Plane Contact Middle switches have to be activated. (These data will deliver a good approximation of the needed 800fF.) The capacitor should be placed above the transistors and
then set the final position: X=-2.05µ, Y=21.6µ.
7.5. Specification of the guard-ring. The capacitor is automatically enclosed in a guard-ring.
It consists of a p+ diffusion, over it a grounded MET1 lead which is connected with the diffusion by a series of contacts. The placed transistors will also be enclosed by a similar guardring. Its upper side will be the lower edge of the guard-ring of the capacitor. The side-edges
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will continue those of the capacitor's downwards. The lower edge will be the ground lead
which can be seen on the lower edge of Fig. 7.
For construction of the guard-ring first select MET1/drawing in the Layer window. Then left
click at CreateMultipart Path. Depressing <F3> invoke the Create Multipart Path window
(Fig. 8.). Beside the Multiple Part Path (MMP) Template select from the roll-down menu the
structure pdiff_sub. (Behind it there is a hidden file which defines the details in TCL language.)
Fig. 8. Create Multipart Path window
After closing the window by activating the Hide button you can draw the guard-ring by left
clicks just like a simple lead. At the end either make a quick double click or one click and
then get out of the command by depressing <ESC>.
7.6. Placement of the guard-ring. The tactics is here, too, a coarse placement by the mouse
and then refinement by numerical correction. Select the placed parts by a left click and then
invoke the Edit ROD Multipart Path Properties window by depressing q (Fig. 9.).
Fig. 9. Edit ROD Multipart Path Properties
Having activated the attributes (Attribute) the coordinates of the corner points (Points) appear.
Because of the Manhattan-style construction, only one of the coordinates changes at the
neighbouring points. Set the final coordinates: (-2 20.4) (-2 -1) (62.5 -1) (62.5 20.4). If you
activate the changes by the button Apply then the window does not close. So, if necessary,
you may correct values at once.
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7.7. Closing the guard-ring. Zoom in to the left joint of the new guard-ring to the guard-ring
of the capacitor with high magnification. In the Layer window MET1 is still selected. Switch
off the display of the other layers by clicking at the button NV. Only the blue MET1 parts remain on the screen. You can see that the MET1 part of the multipart path is not connected to
the guard-ring of the capacitor, there is a gap of 0.1µm. If it had gone up to abuttment then it
would have generated a DRC violation at the contact windows. Therefore, you have to activate the Rectangle command (r) and fill in the gap with a MET1 rectangle: left click at the
lower left corner and then at the upper right corner.
However, the situation is similar on the layer DIF, too. Click AV (all visible), select the layer
DIF, and then NV for the other layers. Now fill in the gap of DIF like you did it with MET1.
When finished, go to the other joint of the guard-ring and correct the gaps there, too.
7.8. Preliminary DRC. At this pointof the job "only" the connections are missing. Before
doing that make a design rule check (DRC). Left click VerifyDRC. The DRC window
opens. Click at Set Switches – the window of the same name opens, where you can set the
parameters. Activate the switches no-coverage and no_erc because these checks are not relevant now. Clicking at OK the names of the switches appear in the DRC window. They remain
there as long as the layout window stays open. In case of repeated checks you need not set
them again (Fig. 10.).
Fig. 10. DRC window
Giving OK the DRC is run. If there are violations they produce flashing white markers. Some
violations may be small and difficult to perceive, therefore, it is better to have Virtuoso make
a list and then zoom to them one by one. Left click VerifyMarkersFind – the Find
Marker window opens. Here the Zoom To Markers button can be switched on and with next
you can go to the violations one by one. For each fault an explanation appears in the Marker
Text window.
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8. Routing: making the connections. Connections are usually made by means of the instruction Path. First the layer of the connection has to be selected in the Layers window. Then the
command Path is activated by depressing p. In default mode the width of the path is the minimum for the selected layer, the leads are laid in Manhattan style (horizontal and vertical).
Depressing <F3> the property-sheet of the instruction can be activated and there the parameters can be modified. During this activity, and mainly if the place is not ample, it is advisable
to make DRC frequently, because the sooner a violation is detected, the easier is to correct it.
8.1. Connecting the gates on poly1. If possible, gates are connected with each other on their
own layer, using frequently the command Rectangle instead of Path. First of all both gates of
the transistor T1 should be connected with a 0.8µm wide rectangle. 0.8µm is wider than the
minimum of 0.35µm, however, this is necessary for the contacts to be laid later. The length of
the rectangle is aligned to the full width of the gates, about 5µm. Select poly1 in the window
Layers. Zoom in the left edge of T1. Depress r, then right click at the upper left corner of the
upper gate, this will be the upper right corner of the rectangle. Move the cursor down and left
to find the lower left corner of the rectangle. The lower edge of the rectangle has to be aligned
to the lower edge of the lower gate (Y direction). The width of 0.8µm in the X direction can
be set based upon the display of (dX,dY) which can be seen at the lower edge of the menu bar
(Fig. 11.). Just left to them the position (X;Y) of the cursor can also be read.
Fig. 11. Display of coordinates and distances
Details of the connection are shown in Fig. 12. In the upper part of the rectangle you can see
the 0.8x0.8µm square for the would-be contact. The placement of the rectangle may happen to
be inaccurate. Then you may correct it using the commands s (Stretch) and m (Move) at a
strong zooming
Fig. 12. poly1 rectangle at the left of the transistor T1
You can do the other poly1 connections in similar manner:
 Connect both gates of TB on the right. Then extend the gate of T2 till TB.
 Connect the gates of T7 on the left.
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 Place one rectangle between T5 and T6 which can connect all the gates there.
The connection of the gates of T5 and T6 is somewhat complicated for the leads cross each
other. Place at the right of the gate of T3B a horizontal rectangle, length 2µm, width 0.8µm,
aligned to the middle of the gate. Similarly place another rectangle of the same size at the
right of the gate of T4A. Then place 0.8µm square at the left of the gate of T3A aligned to the
middle. Now connect the gates of T4A and T4B in two steps. First activate the command Path
(p). As a default, the width of the path will be 0.35µm. Start from the middle of the gate of
T4B, bring it to the left 1.5µm. Turn it downwards by a click, bring it approximately to the
hight of the middle of the gate T4A. Finish it here by a quick double-click. Now close the gap
with a 0.8µm wide rectangle which is aligned to the extension of the gate of T4A as well as to
the path (Fig. 13.). Check it by DRC not later than at this point (or earlier, too).
Fig. 13. poly1 connection between the gates of T4A and T4B
8.2. Completing the connection between the gates of T3A and T3B. This will be done combined with preparation of the inputs to the differential pair. First complete the surronding by
connecting the sources by metal1. Select metal1 drawing and invoke Path. Lay a short horizontal path between the sources in the middle. Because of this piece of metal1 the connection
of the gates has to be done on the metal2 layer with layer changes: poly1  metal1  metal2
and back to poly1. The next task is laying 3 poly1 contacts. Left click CreateVia. The Create Via window opens. At the Via Definition field select from the roll-down menu the poly1
contact: P1_C (Fig. 14.), everything else can remain default. Then click on Hide.
Fig. 14. Selecting the poly1 contact
The poly1 part of the contact is a 0.8µm square. It can be easily aligned to the right of the
2µm rectangles (from inside!) and onto the square at the gate of T3A. You can place them by
left clicks and then exit with <ESC>. Now you can go on with placing vias in order to get to
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metal2. In the Create Via window you have to select VIA1_C and place them. The X coordinate is 25.25µm for both, the Y's are 1.85 and 4.85µm. They have to be connected by metal2:
select metal2 drawing, activate Path (p) and lay a vertical lead. The next step is connecting
the vias with the poly1 contacts beside them on metal1. Select metal1 drawing and activate
the Rectangle command (r). The upper via should be connected so that the height of the rectangle is aligned to the metal1 part of the poly1 contact. The lower rectangle has to be aligned
to the metal1 part of the via and then formed so that it encases the metal1 part of the contact.
Fig. 15. shows the result together with the results of the next two steps.
Fig. 15. Metal1 parts for connecting T3A and T3B and the inputs
Missing in this group are the connection of the drains of T4A and T4B as well as forming the
input pins. Two vias are needed for the connection of the drains. X=22.675µm is common, the
Y's are 0.35 and 6.35µm. When placing vias you should place two vias for the input, too. For
them Y=0.35, common, X=24.025 and 26.2µm. Using the first two vias now you can connect
the drains of T4A and T4B as it is shown in Fig. 7. then two short metal1 leads have to be laid
from the gates to the second two vias. These vias are necessary for system-level connections
because the inputs are accessible only on metal2.
8.3. Further connections, N-transistors. Lay down the following metal1 leads in accordance
with the stick-diagram of Fig. 7.
 The source of T1 left to the ground of the guard ring.
 The source of TB downwards to the ground of the guard ring.
 The source of T2 downwards to the ground of the guard ring.
 Connect the two drains of T1 on the right and then connect them to the common
sources of T3 and T4.
 Connect the drains of T3A and T3B.
 Connect the gate of T1 with the gate and the drains of TB. At both transistors place a
contact on the poly1 rectangle which connects their gates. From the gate contact of T1
lay a metal1 path till the lower drain of TB including the gate contact, too. Then place
a short lead from the upper drain of TB to the path.
8.4. Further connections, P-transistors. The first step is the placement of the power rail
(VDD). This will be aligned to the common N-well of the P-transistors. Place two wellcontact aligned to the left and right upper corner of the well. Left click at CreateVia. Select
ND_C in the field Via Definition and place vias at both corners. They have to be connected by
a 0.7µm wide metal1 path. Select metal1 drawing, depress p and then <F3>. Set Width=
0.7µm and lay down the path. Afterwards return to the placement of well-contacts and place
six more of them along the path.
In the followings continue with normal width (0.4µm) paths.
 Connect the common source of T5 with VDD on the left side.
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



On the right of T5 and on the left of T6 connect the drains of the double transistors
with each other. T5 is working as a MOS diode, therefore add a poly1 contact (P1_C)
to the path over the gate.
Connect the sources of T6 and T7 with each other and then connect them to VDD laying a short vertical path.
On the right of T7 connect the drains with each other.
On the left of T7 place a P1_C contact at the lower end of the rectangle connecting the
gates. From here lay a metal1 path downwards and to the right until the lower electrode of T8. (T8 acting as a resistor, there is no need to distinguish between source and
drain.) Connect the drain of T6 to this lead, too.
8.5. Completing the routing, metal2.
 At X=22.675µm you have already connected the drains of T4A and T4B. Now continue
the lead upwards aiming at the drain of T6. Place a via at the same X direct beside the
drain of T6. Connect the metal2 lead to the via and go on with a metal1 path to the
drain of T6.
 Place a via on the lower corner of the lead, connecting the drains of T5. From here lay
a vertical metal2 path to the vicinity of the drain of T3B. Place a via here and continue
on metal1 to the drain of T3B.
 The next step is to connect the drains of T2 and T7 and the lower electrode of CV.
Place a via (V1_C) at X=51.7µm and Y=6.35µm. Connect it on metal1 with the drain
of T2. Lay a metal2 path upwards until Y=24µm. Lay a metal1 path from the lower
corner of the lead connecting the drains of T7 to the recently laid metal2 path and
place a via here. Then place another via at the upper end of the metal2 path and go
right to the metal1 connector of the lower electrode of CV.
 The last connection goes from the upper electrode of T8 to the lower electrode of CV.
Place two vias at X=55µm and Y=16.5 and 30µm. Lay between them a metal2 path.
Then connect the vias on metal1, downwards to T8 and to the left to the upper contact
of CV.
8.6. Placement of the pins. The pins aare the terminals of the circuit for external connections.
They must be identical with those on the schematics: the same name, same case (!) and direction. The only exception is the ground, represented in the schematics by the icon of the global
gnd!, which automatically has the character of in/out. However, in the layout a regular pin has
to be placed with the same name and with the property I/O Type=inputOutput. The pins will
be placed onto metal1 leads. Their type will be rather pin than drawing. Activate the layer
MET1-pin in the Layers window (Fig. 16.).
Fig. 16. Selecting MET1-pin
Now left click CreatePin, so the window Create Shape Pin opens (Fig. 17. next page). Start
with the node gnd!. Type the name and activate the Display Terminal Name switch. This is
very important because without the display of the names the layout can work but the overview
will be restricted. If you forget it, it cannot be modified later, the pin has to be deleted and
newly placed. Activate the button Display Terminal Name Option beside the switch. It invokes the window Terminal Name Display (Fig. 18. next page) where the display of the name
has to be specified. Here you have to set only that the name of the pin should appear on the
text layer, which may be already the default. The window can be closed by clicking at OK.
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Fig. 17. Create Shape Pin window
Now in the Create Shape Pin window only the type of the pin has to be set. For gnd! switch
on the button inputOutput, then click at Hide. The window will be closed and you can draw
Fig. 18. Terminal Name Display window
the pin in rectangle style. Near the lower left corner draw onto the metal1 lead of the guardring an aligning rectangle, possibly a square. After the second click the square is ready and
the name of the pin appears – linked to the cursor. It has to be
placed nearby with a left click. The result can be seen in Fig. 19,
showing only the relevant layers. Following this place into the
layout the four input pins: INP, INN, UB, VDD, as well as the
only output pin OUT. Even if the room is limited, the input pins
of the OpAmp can be placed on the short metal1 path between
the via and the poly1 contact.
Fig. 19. the gnd! pin
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9. DRC. The checking of the design rules was already introduced in section 7.8 and it was
advised that it should be executed after each critical step. Here it is only emphasized that before doing electrical verification the last step must always be a DRC. After the last DRC the
cell has to be saved.
10. Extract. The extracting program analyses the drawings of the cell and generates a Spice
netlist representing the graphic information in the cell. Left click VerifyExtract. The Extractor window opens. Activate the switch capall (Set Switches, Fig. 20.). So the parasitic
capacitances, too, will be extracted and included in the netlist. They will be necessary at the
post-layout simulation. After OK the extractor does the job and generates the extracted view
of the cell OpAmp. The extracted view can be opened. It looks similar to the layout, and at
strong zoom you can see the symbols of the extracted components beside the corresponding
graphic elements.
Fig. 20. ábra: Extractor window
11. LVS. Layout Versus Schematic – comparison of the original and the extracted netlists.
This is the most stirring step of the layout design because it verifies whether the layout will
really implement the network which was the origin of the design.
Open the extracted view. Left click VerifyLVS. The Artist LVS window opens (Fig 21, next
page). Switch on in the row Create Netlist both schematic and extracted. Underneath you can
invoke the library with the Browse and specify the cells to be compared – the extracted usually appears as default. The Rules File field remains empty, the Rules Library field atomatically gets the value TECH_C35B3. In the field LVS Options only the button Terminals has to
be activated, all others remain switched off. Then start the comparison with the button Run.
The process is running in the background and after a while a message appears. If it brings the
eagerly awaited "The netlists match" then you may go on happily to the next task. However,
the typical result of the first run is usually an error message. Then open the report file with a
click at the button Outputs. In the report file LVS lists and explains the differences which have
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been found during the comparison. Then usually the layout has to be corrected and the LVS
repeated.
Fig. 21. Artist LVS window
12. Post-Layout simulation. The netlists match, the layout is correct. However, there are
stray capacitancies which may influence the behaviour of the OpAmp more or less. So you
have to check the final Bode-diagram of the OpAmp with the stray capacitancies included.
Return to section 3.7.e). As a preparation repeat the AC simulation of the schematics. When
the Bode-diagram appears on the screen stop the simulation and return to the settings.
In the simulation the netlist of the schematics has to be replaced by the extracted netlist of the
layout, as follows. In the Virtuoso Simulator window left click on SetupEnvironment. The
Environment Options window opens (Fig. 22, next page). In the first row the content of the
field Switch View List has to be extended so that you add the extracted view before the schematic. Close the window with OK. If you start the simulation now then it will deliver the postlayout results. Compare the results with those of the schematic, check whether there are differences.
13. Complete the documentation. The documentation of the OpAmp (catalogue data sheet)
which was prepared according to section 4, should be finalized by adding the size of the cell.
If necessary, modify the AC data based upon the results of the post-layout simulation.
In conclusion the Appendix presents the complete layout of the OpAmp, as the result of the
exercise described in this leaflet.
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Fig. 22. Environment Options window
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Appendix: Full layout of the OpAmp
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