Download 4/2 PAM Serial link Transmitter with Tunable Pre

4/2 PAM Serial link Transmitter with Tunable Pre-Emphasis
Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen and Shyh-Jye Jou
Department of Electrical Engineering, National Central University, Chung-Li, Taiwan R.O.C.
Abstract
In this paper, we will implement a 4/2 PAM transmitter of
the high-speed data serial link over cable and demonstrate a
newly development of the pre-emphasis circuit. The overall
circuit is implemented in TSMC 0.18um 1P6M 1.8v CMOS
process. The performance of the transceiver can reach
20/10 Gbps over the 1-5 meter long cable.
I.
INTRODUCTION
Due to the multimedia applications, demand of bandwidth
for the transmission has increased. This demand has
resulted in the development of high speed and low cost
serial link technology [1-8]. In this high data rate
application, the high-speed links play an important role in
computer-to-peripheral connections [10][11], local area
network [12]s, memory-busses, flat plane display, etc. With
the data rate up to Gbps range, the propagation of the
signaling is affected by two limitations.
The first
limitation is due to the package parasitic and bandwidth of
cable. The second limitation is due to the processing speed
of CMOS circuit. The chip package dominates the output
pin performance because of the pin’s loading and bonding
wire. The pin’s loading causes one RC time constant that
lowers the location of the -3dB frequency. Thus, when the
loading is larger, the -3dB bandwidth is smaller. The
bonding wire results in the pattern dependent data jitter and
lowers the signal to noise ratio. When the frequency is
higher, the bonding wire and cable becomes more and more
critical in the performance of the whole system.
n order to gain higher data rates without operating
frequency increasing, we apply four level pulse amplitude
modulation (4PAM) [1] to our system. Furthermore, we
propose a pre-emphasis architecture that can enlarge the
high frequency components, so the overall frequency
response in the receiver side is uniform within the desired
frequency range. The goal of the pre-emphasis circuit is to
handle cable length from 1 m to 10 m. The paper is
organized as follows. Section II shows the architecture of
the transmitter. The circuit design of functional blocks are
described in Section III. Section IV shows the
implementation and simulation results. Finally, a
conclusion is made in section V.
II. ARCHITECTURE DESIGN
This section describes the proposed transmitter for a 4/2
PAM 20/10 Gbps serial link. Fig. 1 and Fig. 2 show the
proposed transceiver structure and the block diagram of the
4/2 PAM transmitter. The transceiver uses pull-up
resistance for terminator matching in the TX and RX nodes.
This transmitter contains MSB and LSB block as shown in
Fig. 2 (a) and each starts with high-speed parallel data
stream, and follows a 5:1 multi-phase multiplexer as shown
in Fig. 2 (b) which transmits the 20/10 Gbps data into the
transmission line using a 2 GHz five phase clocks. The
architecture also contains a 2-tap pre-emphasis decision
blocks, parallel data synchronizer and 4PAM output driver.
The MSB block contains two drivers as compared to one
driver in LSB blocks. However, the length of the cable line
is not always the same, and this design issue is discussed in
the next section. The MSB block can be enable / disable so
that the transmitter can transmit 4PAM/2PAM signals.
Fig. 1 Conventional transceiver structure
(a)
(b)
Fig. 2 Block diagram of the proposed transmitter.
III. CIRCUIT DESIGN
A.
Cable
We know that the attenuation of cable increases in higher
frequency. We must first calculate the skin effect resistance
(Rnf) from the datasheet of the cable manufacturer. Once
we have Rnf, we can use Hspice Welement cable model to
model the frequency response of a 5m cable [5][9][13][14].
The –3 dB frequencies of the simulation and measurement
results are quite the same and is around 1.6 GHz (5M) and
300MHz (10M). The skin effect distorted the signaling
because the attenuation of the low frequency and high
frequency is not uniform. Thus, a pre-emphasis scheme is
required to compensate the distortion.
B.
Package effect
The chip-package interface is shown in Fig. 3. The location
of the termination resistor (on chip or off chip) has the
impact on the receiver’s frequency response. The data pulse
to propagate over the package is seriously distorted in the
off-chip termination case because the bonding wire effect
distorts the transmitting signal. As shown in Fig. 3, the
trans-impedance of the off-chip termination will generate a
high frequency zero. So there is more chance to have high
frequency ringing in the time–domain pulse as shown in Fig.
4. In the design, we use on-chip termination method with
the resistor made of poly resistance in parallel with PMOS
device.
R2
( SCR + 1) * ( S 2 LCR + SL + 2 R )
such that for a different cable length, the signal amplitude
received is the same. Fig. 6 shows that without
pre-emphasis, cable output pulse is decayed and has a long
tail (ISI). So we must apply pre-emphasis mechanism to
cancel the loss of cable by using Tap A and B for different
frequency components.
Fig. 5 The function of Pre-emphasis
R (SCR+ 2)
(SCR+ 2) *(S3LC2R + S2LC+ SC+ SC(R +1) + 2)
(a)
(b)
Fig. 3 Termination on chip (transmitter)
(a)
(b)
Fig. 4 The frequency response of trans-impedance and time-domain
waveform of the on chip and off chip node for 5-m cable
C. Pre-emphasis
The cable line is a low pass function. Pre-emphasis circuit
plays a role of high pass filter and that in the receiver the
frequency response is flattened within the bandwidth of our
desired frequency range. The pre-emphasis either amplify
the high frequency component or attenuate the low
frequency component [1][3]. The frequency response of our
transmitter is depicted in Fig. 5. The dotted line means the
overall frequency response. In the method, it enlarges the
high frequency component so that the receiver signal
amplitude for different transition is fixed. Moreover, the
main driver and pre-emphasis driver capability can be tuned
Fig. 6 Signaling in TXRX and ISI cancellation
D. Tap decision
In order to increase the high frequency components, we
enlarge the transition amplitude of the signaling. In Fig. 7,
the signal without pre-emphasis is decay to wrong
amplitude in RX node. On the other hand, when the signal
is pre-shaped in Tx node, we can maintain the correct
amplitude in RX node. We apply current “A” into the
differential pair nodes (signal level is shifted down) to
enhance the data amplitude when data is changed. As
shown in Fig. 7, we can apply 2 tap (A,B) to pre_shape the
signal to cancel ISI effect of different frequency component.
Because delay circuit design is easier to design than
transition detector logic, we use tap 1, 2 to replace tap A, B
for signal pre-shaping as shown in Fig. 8. Tap 1 is the input
data that delays one bit time to apply to different node (D-)
in Fig. 9. Similarly, Tap 2 is the input data that delays 2 bit
time. So we can use tap 1, 2 to replace A,B,C in Fig. 8 by
using algebra transfer. According to Fig. 8 in RX-node.We
can adjust the tap1 and 2 current to have correct signal
amplitude for different cable length .It works like as a FIR
as shown in below.
Vo(n) = (1 + a0) * Vi(n) - a1 * Vi(n - 1) - a2 * Vi(n - 2) (1)
In this way, the signal amplitude in the receiver is the same
for different cable length. Also, the maximum transient
amplitude for both the differential line are the same.
In our post-layout simulation, the maximum operating
frequency of Fig. 11(a) is 8GHz. The advantage of Fig.
11(b) is that all block is operating in 1/5 bit rate. So it’s
maximum frequency is higher and can achieve to 16GHz.
But it occupies larger area because of more pre-drivers are
required.
Fig. 7 The pre-shaped signal in the transmitter
Fig. 11 Two kinds Architecture of PISO
Fig. 8 Pre-emphasis with Tap 1 and 2
Fig. 9 Driver architecture: main driver and pre-emphasis
G. Driver
The driver includes the main driver, tap1 and tap2, and all
have five data path and their structures are similar. For an
example, we employ the difference of phase1 and phase2b
to transmit one branch of data as shown in Fig. 12. Because
PISO is also the output drivers, the drivers suffer some
charge sharing effect. The effect includes two kinds of
source. The first one is to pull down the output signal level
when M1 is turned on. The other one will reduce current
source magnitude so that output signal will be pulled up
when M2 is turned on. To reduce these two effects, we add
a clk5 to control the turn-on of M2. In this way, M2 in data
path 1 and M1 in data path 5 will turn on simultaneously.
So the two effects will cancelled each other.
E.
Synchronizer
The five parallel data operate at 2Gbps rate, and we need
multi-phase clocks to transform the parallel data to serial
data operating at 20/10 Gbps (4/2 PAM) rate over the cable.
A parallel data synchronizer should be used as shown in Fig.
10 to synchronize with the multi-phase clock and enlarge
the time margin when multiplexing the parallel data. So we
must skew the data in different phase.
s e r ia l d a ta
D 1
D 2
Fig. 12 Main driver circuit and charge sharing effect
D 3
IV.
D 1
D 2
p a r a lle l d a ta
D 3
c lk 1
c lk 2 b
1 /5
p e r io d
Fig. 10 Synchronization of the skewed parallel data with the multi phase
clocks
F.
PISO
A conventional architecture is shown in Fig. 11(a), where
PISO is located before pre-driver and output driver.
Another structure is to combine the PISO into the output
driver as shown in Fig. 11(b). The maximum operating
frequency of Fig. 11(a) is lower than Fig. 11(b) because all
block is operating in symbol rate. But it occupies few area.
IMPLEMENTION AND SIMULATION
RESULTS
Fig. 13 shows the waveform without / with pre-emphasis in
RX node. Obviously, the amplitude without pre-emphasis is
smaller than 300 mV and is incorrect. The waveform in the
TX nodes is shown in Fig. 14. Because we apply
pre-emphasis to the transmitter, the output signal amplitude
is enlarged when the data changes. The detail eye diagrams
of the RX nodes in symbol rate are shown in Fig. 15. Each
eye’s differential amplitude is 300mV. Its data jitter is 6.5ps
for binary data. Finally main driver and tap1, tap2 current
source magnitude are 21mA, 6.6mA, 1.4mA respectively
for 5-m cable in our system.
The overall circuits including PLL, transmitter, and PRBS
are implemented by using the full custom design flow.
Clock buffers are used to insure the equal driving capability
of multi-phase clocks. The circuit is implemented by using
the process of TSMC 1P6M 0.18um CMOS process. Fig.
16 and Table. 1 show the overall layout and chip summary.
5 meter. This design can transmit binary or 4PAM data
using input control circuit. We use a five phase clocks in
the transceiver to achieve the 20/10Gbps data rate over the
cable with 5m length. All the transmitter and PLL circuit
use full custom flow to handle 2GHz clock rate. The chip is
implemented in TSMC1P6M 0.18um CMOS technology.
Bypass Cap.
4PAM preemphasis TX
(Tap2 Tap1
Main_drv)
PRBS
PLL
Fig. 13 The simulation result in RX-node without / with pre-emphasis
Fig. 16 Overall chip layout
Table. 1 Overall circuit performance summary
Technology
Supply voltage
Clock rate
Data rate
Fig. 14 The simulation result in TX-node with pre-emphasis
Total Power (in 20 Gbps)
Total Area
Gate count
VI.
[1]
[2]
[3]
[4]
[5]
Fig. 15 The eye diagram of receiver (post-layout simulation)
V. CONCLUSIONS
In this paper, we describe the limitation of the transmitter
due to package and cable and introduce a better method to
design the proposed transmitter. We have described the
specification of the cable and we make a cable model with
skin effect for the cable to be simulated in Hspice. The
multi-phase multiplexer driver can relax the speed
requirement. Moreover, the current of Tap1 and Tap2 can
be tuned digitally to pre-emphasize the signal to improve
the signal quality in the receiving end. By doing so, the
length of the coaxial cable can be in the range of 1 meter to
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
TSMC1P6M 0.18 um
1.8v
2 GHz (5 phase)
20 Gbps for 4PAM;
10 Gbps for 2PAM
252 mW
1300 x 1200 um2
1185
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