Download Implementation Of Low Power 3-Bit Flash ADC Using

ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
IMPLEMENTATION OF LOW POWER 3-BIT FLASH ADC
USING TUNABLE DOUBLE GATE MOSFET
Ayindrila Ganguly, Sagar Mukherjee
Department of ECE,
MCKV Institute of Engineering,
Howrah, India
ABSTRACT- This paper present a Low
power 3 bit Flash Analog to Digital converter
using tunable Double gate MOSFET. The
proposed Flash ADC is derived by using of
Double gate MOSFET model. Various
leakages, ambient threshold voltages, charge
mobility, low power property will be
preserved into well account for in the model
of DG MOSFET. The resulting expression of
Drain –current with respect to drain-source
voltage and gate-source voltage for DG
MOSFET are continuous in all operation
regions i.e., linear, saturation , and sub
threshold becoming it suitable for compact
modeling. Simulation result of Flash ADC
shows less power consumption and less time
and which is also suitable for gigahertz
applications. The model has been
implemented in Simulation Program with
Verilog A. The simulation result shows that
this proposed Flash ADC achieve an effective
resolution band of 800MHz, while
consuming maximum 5.48mW of power.
proposed architecture Double Gate MOSFET
is used. Contrary conventional bulk MOSFET,
Double gate MOSFET reduces the leakage
currents, the drain induced barrier lowering
and other short channel effects, power
dissipation and fastest switching capacity
because of its tunable functionality[1][5].
Very high sample rate of these type of ADC
enable gigahertz applications like radar
detection, satellite communication, wide
band
radio
receivers,
sampling
oscilloscopes, optical communication links.
More often the Flash ADC is embedded in a
large IC containing many digital decoding
functions.
Flash type adc :
Flash ADC architecture is parallel in
structure. A Flash ADC is formed of generally
three building block Resistor ladder,
Comparator Array and one thermometer to
binary encoder. N bit Flash ADC required 2N
resistors to generate different reference
voltages and 2N-1 comparators to compare
those reference voltages with incoming
analog signal[2]. Power consumption of
Flash ADC decreases with increase in
resistor value. The equation for power
consumption of resistor (PR) is given by:[3]
Index Terms – Double gate MOSFET model,
Comparator, Thermometer to Binary
Encoder, Flash ADC.
INTRODUCTION:
ADCs are the most necessary and
fundamental building block among all the
electronics devices which process real world
data. Flash type architecture is simplest and
fastest among all ADC architecture and also
known as parallel ADC[2]-[4][7]. Flash ADCs
are suitable for very large bandwidth
application, but consumes more power than
other ADC architecture[6][8]-[10]. For this
seven comparator and one thermometer to
binary encoder converts analog signal into
digital bit for the proposed three bit Flash
type analog to digital converter. Eight
PR =
Where Vref is input reference voltage, NR is
total number of resistors Ru , the value of
resistance for the particular resistor. So
suitable value for resistor should be selected
to eliminate offset error.
resistors divides Vref voltages passed
through seven different comparator which
compares with Vin voltage produces seven
different values at the output of the
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
comparators
and
also
known
as
Thermometer Code . Encoder converts this
Thermometer Code into corresponding
binary number depends on due to the
present of number of one present at the
outputs of the comparators.
connected together and in asymmetrical
driven mode, separate biasing is provided to
the front and back gates. Controlling the
back gate of DG MOSFET, provide the drain
current on the front gate. Due to controlling
the tunability of back gate, the DG MOSFET
performance is adjusted.
The drain current of Double gate MOSFET
can be derived as [1]
=µ
=µ
Where r=
/
is a structural
parameter. β is an intermediary parameter.
β is a function of V.V is the electron quasiFermi potential.
and
are β at the
source and drain, respectively. Where q is
the electronic charge,
is the permittivity
of silicon,
is the permittivity of oxide,
Fig:1. Basic building block of Three Bit Flash
ADC
and
are the silicon and oxide
thicknesses. k is the Boltzmann’s constant. T
is absolute temperature.
is the intrinsic
carrier density. W is channel width. L is
channel length.
Figure 2 depicts the variation of drain
current ID with gate –to-source voltages VGS
for a given value of VDS. The transfer
characteristic shows that for when VGS is
positive ID rises slowly at first then rapidly
with increasing VGS.
Double gate MOSFET:
The conventional model of bulk MOSFET
have evolved various problem due to
saturation on scaling parameters, various
leakages, ambient threshold voltages ,charge
mobility etc. Contrary bulk MOSFET, Double
gate MOSFET has two gates controlling the
channel instead of one gate [5]. The gates
surrounding the conducting channel ensure
that a better control over channel can be
applied, which reduces the leakage currents,
the drain induced barrier lowering and other
short channel effects and power dissipation.
Depletion charges in Double gate MOSFETs
are negligible due to lightly doped silicon
film. The main advantage is that the
threshold voltage can be set as a function of
the applied second gate bias, this depends on
the ratio of the capacitances of the two gate
dielectrics. Due to higher controllability,
Double gate MOSFET has relatively high
ION/IOFF ratio. The DG MOSFET is operating in
two modes symmetrical driven and
asymmetrical driven mode to design analog
tunable circuits.[1] In symmetrical driven
mode, the front and back gates are
Fig:2. Drain to Source VDS of a DG MOSFET
as a function of Drain Current and Gate to
source voltage obtained from the DG
MOSFET model.
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
The gate-source threshold voltage VT at
which ID attains a specified small value after
crossing VT drain current ID increases rapidly
with increasing VGS.
Vin voltage is greater than the Verf voltage.
Output of comparator is low when Vin
voltage is lesser than the Vref voltages.[3]
Fig:4. Schematic diagram of a
comparator using DG nMOSFET along
with two inverter at the output. Two
stage of inverter carry out signal produce
fout for more accuracy of the out signal.
Fig:3. Gate to Source VGS of a DG MOSFET
as a function of Drain Current and Drain
to source voltage obtained from the DG
MOSFET model.
Double gate MOSFET will be used for the
proposed comparator where both the gate of
double gate MOSFET is short and becoming
a common gate shown in figure 4. If gatesource potentials of two MOSFET are
identical so channel currents should be
equal so m6 and m7 MOSFET acts as current
mirror also acts as load of circuit. As both the
gate and drain of MOSFET m1 and m2 are tied
together so they are always is in saturation
region and acts as a pn junction diode. This
MOS diode part is used as a component of
current mirror. MOSFET m4 and m5 acts as
current drivers and m3 acts as a current sink
that flows current from current driver to
ground. Two amplifiers will be used at the
output to amplify out signal. One of the input
gate of the comparator fixed with DC voltage.
V2 equals to dc voltage where as V1 equals to
sinusoid signal applies another output of
comparator if V1 >V2 as long as m7 MOSFET
remains in saturation, current flow from m7
MOSFET, m6 MOSFET and m4 MOSFET is
greater than m5 MOSFET so out is equal to
Vdd. So that fout become high. When V1< V2,
current flows from m7 MOSFET, m6 MOSFET
and m4 MOSFET is less than m5 MOSFET so
out continues to decrease so that fout become
low.
Comparator output Waveform:
Figure 3 curve displays the variation of drain
current ID with the drain-to-source voltage
VDS for a fixed value of gate-to-source voltage
VGS. For a given value of VGS (exceeding the
VT), the drain voltage is made slightly
negative with respect to source so that ID is
proportional to VDS. This gives the linear
region of the characteristic. The channel
resistance increases with increasing VDS
causing of drain characteristic to bend.
When VDS attains the value for which VGS - VDS
= VT, the channel thickness at the drain end
goes to zero. This is referred to as the pinchoff-point. At this point, the drain current
saturates at a value IDsat, the corresponding
value of VDS being denoted by VDsat. As VDS
increases further, the pinch-off-point moves
towards the source but the drain current
remains almost same. This region is named
as saturation region.
Comparator
Specification:
Circuit
and
Design
Two voltages, Vin and Vref, will be applied to
the two input of the comparator. Positive
input terminal of comparator receives Vin
correspondingly Vref is received by negative
input terminal of comparator receives Vref .
Output of the comparator become high when
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
D2= O3
D1= O5+O3’O2+O1O2’
D0=O6O5+O5’O4+O3’O2+O1’O
Fig:5.
Comparator
characteristics
simulated with Verilog A. Output
measured by the comparison between
analog signal and reference signal.
Fig: 6. Architecture of Thermometer to
Binary Encoder using AND, OR and NOT
gates.
Two different gate input of comparator
assign to have two different signal sinewave
signal and refference signal. Output become
high at high sinewave signal compare to
reference voltage. Output become low at low
sinewave signal compare to reference
voltage.
TABLE I
Truth table of thermometer to binary code.
Thermometer to Binary Encoder Encoder
Circuit and Design Specification:
The outputs from the comparator array in a
flash ADC will be in thermometer code
format. Each seven comparators in a three
bit flash ADC produce one comparison
output. Seven thermometer bits are present
at the output of each comparator.
Thermometer to binary code encoder
encodes this thermometer code into binary
code and provides speed of the entire
architecture. Truth table for thermometer
code and its corresponding binary code is
given in table I. According to the truth table,
number of one present in the thermometer
code is converting into binary no. Depending
on 0 to 1 transition change, equation will be
plotted. D2 changes same as O3. There is
many 0 to 1 transition in D1 and D0.The
conversion of Thermometer code to binary
code is done using the basic logic gates (AND,
OR and INVERTER) by the equations shown
in figure 6. [2]
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THERMOMETER CODE
BINARYCODE
Inputs
Outputs
O6 O5 O4 O3 O2 O1 O0 D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
Encoder output Waveform:
Results:
According to the truth table, D0, D1,D2 is set.
From the result it is clear that O6 ,O5 ,O4 ,O3 ,O2
,O1 is changes same as truth table.
The 3-bit Flash ADC is designed by using DG
MOSFET and simulation done by Verilog A.
Resolution bandwidth 800MHz at average
power 4.75mW is obtained from the
simulation result where power range varies
from 5.48mW to 4mW.
INL and DNL is an important parameter of
ADC that measures non linearity errors.
INL is defined as the difference between the
actual step transitions from their ideal value
without considering the effect of gain and
offset errors.[3] It also measures the
accuracy and precision of ADC output.
Fig: Thermometer to Binary
Characteristic with Verilog A
DNL has having all the value greater than -1
so it is having no missing bit and has good
linearity, monotonicity. INL is defining as
the integral of the DNL errors, so good DNL
guarantees good INL.
Encoder
Flash ADC output Waveform:
TABLE II
Sinewave signal is used as input signal for
proposed 3-bit Flash ADC simulated
transient analysis which is implemented by
using Verilog A.
Table for the Study of DNL and INL
BIT
DNL
INL
0
-0.84631
0.039409
1
0.153695
2.782759
2
0.565025
-1.88374
3
0.919212
4.946305
4
-1.00985
0.934975
5
2.852217
0.499015
6
-0.5069
3.903941
7
0.59803
1.307882
Fig:9. Output waveform for 3 bit Flash ADC
designed using DGMOS.
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
Conclusion:
3.
In conclusion, low Power Flash ADC using
Tunable DG-MOSFET is presented. In DGMOSFET the gates surrounding the
conducting channel ensure that a better
control over the channel can be applied,
which reduces the leakage currents, the
drain induced barrier lowering (DIBL)
effects, short channel effects and various
other defaults of conventional bulk CMOS.
This low Power Flash ADC using Tunable DGMOSFET can be extended to medium-to-high
resolution applications because this
simplicity of the circuit. From the simulation
result it is obtained that the proposed Flash
ADC consumes an average power 4.75mW,
while obtains resolution band width
800MHz for all possible inputs.
4.
5.
6.
7.
Acknolodgement:
The author would like to thank Sagar
Mukherjee in the Department of Electronics
And Communication Engineering, MCKVIE.
The author is also grateful of Department of
Electronics
And
Communication
Engineering, MCKVIE. The device was
designed and implemented using Verilog A
which is made available by department.
8.
References:
1.
2.
Huaxin Lu and Yuan Taur, “An Analytic
Potential Model for Symmetric and
Asymmetric DG MOSFETs”, IEEE
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Flash
ADC
in 0.18µm
CMOS,
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and Engineering (IJSCE) ISSN: 22312307, Volume-1, Issue-5, November
2011.
9.
10.
665
P. E. Allen and D. R. Holberg, “CMOS
Analog Circuit Design,”2ndedition ISBN
0-19-5116445.
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Liao and Yuh-Shyan Hwang, “A New
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©2007 IEEE.
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ISSN No: 2309-4893
International Journal of Advanced Engineering and Global Technology
I
Vol-03, Issue-05, May 2015
Street Building, Manchester M60
1QD, England, UK.
Ayindrila Ganguly received the B.TECH
degree in Electronics And Communication
Engineering from Saroj Mohan Institute of
Technology, West Bengal, India, in 2012
and is currently working toward the
M.TECH degree in ECE VLSI DESIGN at
MCKV Institute of Engineering, Howrah,
West Bengal, India.
Sagar Mukherjee the B.TECH degree in
Electronics
And
Communication
Engineering from MCKV Institute of
Engineering, Howrah, West Bengal, India,
in 2009 and MTECH in VLSI from
Jadavpure University, West Bengal, India,
in 2012 and is currently working as
Assistant Professor in MCKV Institute of
Engineering, Howrah, West Bengal, India.
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