Download 1. RELIABILITY OF NANOELECTRONIC DEVICES

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1. RELIABILITY OF NANOELECTRONIC DEVICES
1.1
Introduction
Every manufacturer worries about the lifetime of their product. Apart from potential
warranty costs, issues such as customer satisfaction and liability are of great concern. The ability
to predict lifetime based on few samples and limited time for tests require a deep understanding
of the reliability physics. Understanding the failure mechanisms will ensure that there are no
surprises lurking to cause premature failure. This chapter will focus on the reliability concerns in
various types of electronic components and distinguish between manufacturing variations and
reliability. We will conclude with a brief look at various failure mechanisms in CMOS
technologies.
1.2
Electronics Landscape is Broadening, so are the Reliability Concerns
Most electronic systems can be broadly classified based on their performance and
footprint (area) as figures of merit. This is best illustrated in Fig. 1.1. The highperformance/small footprint region is occupied by microprocessors and ASICs.; the other
extreme covers electronic applications such as solar panels and large format displays. Between
these wide ranges of applications, we encounter various materials (e.g. silicon, GaAs, polymers,
etc.) and several forms of the same material (for example, crystalline and poly-crystalline
silicon).
Consider the challenges for the IC industry. The industry depends on aggressive scaling
of transistors to keep up with Moore’s law. Innovations in silicon technology such as strained-Si
channels, high-k/metal gate stacks and non-planar multi-gate transistor structures have all
enabled the scaling and performance trends. Uniaxial compressive strain in the channel of PMOS
and a tensile strain in the channel of NMOS have shown to enhance hole and electron mobility
for PMOS and NMOS transistors, respectively. An epitaxial SiGe film is used to form the
source/drain (S/D) regions of the PMOS transistor
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Fig. 1.1 Landscape of electronics is evolving rapidly.
to provide the compressive strain in the channel and a high tensile stress silicon nitride cap is
used to induce uniaxial tensile strain in the channel of the NMOS transistor.
Next, for gate oxide, the high-k/metal gate stacks have been used effectively to mitigate
the gate-oxide scaling (leakage and breakdown) issues. Intel’s 45nm technology has combined
high-k/metal gate stacks with strained Si channels to achieve a high drive current performance
with very low gate leakage. It has also been shown that these high-k/metal gate stacks would be
useful even for emerging nanoelectronic devices such as III-V Quantum Well (QW) InSb
transistors, Carbon nanotubes and Si-nanowires. Owing to their superior electron mobility (50100x), III-V materials have attracted significant attention. InSb QW transistors have
demonstrated the lowest energy-delay product and are particularly suitable for very low
operating voltages (Vdd = 0.5V). InGaAs is another contender for integration on to silicon
substrates. It has been shown that InGaAs and InAlAs device stacks can be grown virtually
defect free on Si substrates, and used as transistor channel materials.
At highly scaled gate lengths, short channel effects dominate and device electrostatics
are harder to control, resulting in higher leakage and lower ION/IOFF ratio. Non-planar structures
such as double-gated devices and FinFETs (Tri-gate) offer improved gate to channel coupling
and hence better control over channel electrostatics. Intel’s tri-gate transistors (or FinFETs) on
fully depleted substrates have demonstrated a 30-60% increase in drive current compared to
planar transistors at iso-IOFF. SOI technology is particularly interesting because of the
performance and power gains it offers. IBM’s partially depleted SOI devices (planar and non-
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planar) offer a 30% increase in performance and 35% reduction in leakage compared to bulk
processes, due to reduced parasitic capacitances.
This brief survey of high-performance electronics area drives home the fact that the
industry uses a diverse range of materials and processes to manufacture products. It is claimed
that such diversity will result in a wide range of reliability issues governed by different physical
mechanisms.
A different set of reliability issues arise for large area technologies, such as solar cells.
For example, silicon based solar cells with p-substrate suffer from bias temperature instability,
charge trapping in the passivation layer, metal intrusion from the contact, shadow degradation,
etc. The organic solar cells are desirable due to their high flexibility and disposable nature.
However, their efficiency degrades rapidly as the polymers segregate form the organic mixture in
to isolated phases. Additional issues of moisture induced failure and delamination of other types
of solar cells have also been reported.
In short, every technology is characterized by a set of reliability issues that must be
addressed before one can attest to the viability of technology. Despite the difference however,
the fundamental aspects of design of experiments for accelerated testing, small sample data
analysis to robust prediction of lifetime, the physics and mechanics of defect generation can
often be analyzed in a very similar framework. Although, we will focus on CMOS reliability in
this book, the similarity of issues across technologies make the discussion broader than CMOS
technology alone. We will consider some of the general issues now.
1.3
Variability and Reliability Are Related, But Not The Same
Standardization launched industrial revolution. If is often said that the standardization
and interchangeability of screw-threads ushered the era of Industrial revolution. This uniformity
of parts (no matter their provenance) facilitates the construction of complex systems with several
million individual parts (example, aircraft carriers) with predictable reliability and performance.
A striking modern example comes from the 1950’s Japanese auto industry. Japanese auto makers
doubled the tolerance specifications on auto transmission parts, which translated to a smoother
ride and a significantly longer lifetime for the transmission (compared to American transmission
parts at that time) and resulted in significantly improved sales.
Likewise, a fundamental reason for success of IC technologies is its ability to ensure
uniformity of function compared to a bipolar or vacuum tubes circuits composed of individual
components. Modern microprocessors and GPUs are packing in 500M to 3 billion transistors on
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a single die; hence each transistor’s drive strength is expected to conform to a narrow
distribution, such that the whole chip has a predictable performance.
Variability vs. Reliability. The term ‘variability’ is used to characterize the
deviation in some characteristics of the device during manufacturing; for example, the blue
region in Error! Reference source not found. describes the distribution of drain current in a
MOS transistor [Hiramoto, TED, 2011]. Variability is known to reduce as the process matures,
but as will see below, that there are fundamental reasons why it cannot be eliminated completely.
On the other hand, ‘reliability’ is a time dependent phenomenon, which alters the device
characteristics over an extended period of use, because newly generated of defects cause
additional shift in performance. Error! Reference source not found. shows that while original
process variation (in blue) may have been restricted to few percent of the target value, reliability
degradation (in red) occurring over time and could dramatically worsen the deviation. The term
‘Reliability’ is formally defined later in this section.
1.4
Classification of Process Variability
In terms of the scale of process inhomogeneity, one expects wafer-to-wafer, die-to-die,
layout-dependent, and random variability of transistor performance. The first three could be
presumed systematic and improvement in processing could reduce variability, the last one is
fundamental and is related to the discreteness of matter, as discussed below.
Line edge roughness (LER) is a lithography-induced variation. LER causes variations in poly
gate length (front end variations) and metal interconnect width (back end variations), resulting in
a distribution over timing and power characteristics of transistors. For current technologies, LER
is on the order of few nanometers. This can cause a significant variation in the transistor channel
length; however, its effect on the diffusion widths is minimal. Metal shape distortions caused by
LER can have a pronounced effect on timing of global signals (clocks for example). To mitigate
such lithography induced effects, manufacturers use extensive geometry corrections at the mask
level which are known as Optical Proximity Corrections (OPC). Sub-90nm technologies also
suffer from several non-lithographic sources of variation. Random dopant fluctuation (RDF)
causes a significant shift in the threshold voltage of transistors.
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Fig. 1.2 Examples of line-edge roughness, random dopant fluctuation, and grain-boundaries in
poly-silicon transistors.
Random dopant fluctuation (RDF). It is predicted that a 16nm bulk transistor will have 53
Silicon atoms and 3.5 boron atoms in the channel; at this level purely random variations in the
number of atoms in the channel can have a disastrous effect. Fig. 4 shows an illustration of LER
and simulated placement of dopant atoms in the channel. Layout dependent stress effects are
commonly observed in strained silicon technologies. Well-proximity effect and rapid thermal
anneal (RTA) induced variations also need to be considered for accurate estimation of transistor
performance. Most of these variations manifest as intra-die, inter-die and lot-to-lot distributions.
Oxide thickness variation (Tox-Variatiion) Modern gate oxides are only 5/6 atoms thick (~1nm),
therefore statistical variation of even a few transistors will lead to considerable variation in gate
leakage current. Design with such variability has long been an important concern for modern
integrated circuit design.
Grain-size distribution. Low temperature poly silicon TFTs are used as display switches and
using the same technology for peripheral circuits can cut costs. Due to their high mobility, polySi TFTs can be used to fabricate touch panel and sensor circuits on the display panel itself.
However, TFT devices suffer from variations caused by a diverse grain structure in the poly-Si
film. Specifically, grain-size is distributed log-normally [Thomson, MIT], with typical sizes of 1
micron. Since the TFT channel length is only 2-3 micron long, the number and orientation of
grains in a given transistor varies widely. Such variations in TFTs can cause significant nonuniformities in the display image, especially in displays based on organic light emitting diodes
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(OLED). The manufacture of TFTs includes re-crystallization of poly-Si grains in the channel
region using laser pulses. Fluctuations in the laser energy can cause differences in the grain size
(Fig. 5) and hence their electrical characteristics. Such local variations can result in significant
device to device variations. This effect can be directly observed in the enormous increase in
complexity of the pixel driver circuitry.
1.5
Reliability Classification in Microelectronics
Let us now consider the origin of shifts of device performance over time. In this
discussion, it is helpful to distinguish between degradation of transistor performance (front-end
process) and degradation of interconnects (‘back-end’ process). The designations of front-end
and back-end process reflects the distinction between transistor fabrication (mostly
semiconductor and insulators) vs. interconnect fabrication (mostly metals and insulators).
The transistors related reliability issues involve
Time dependent dielectric breakdown (TDDB) is related to the destruction of gate oxide over
time. This type of breakdown usually occurs in two stages. First, charges build-up in the oxide
layer through trapping and cause electric field in addition to the applied field. If the sum of these
fields exceeds the breakdown threshold, it causes oxide punch through.
Negative Bias Temperature Instability (NBTI) causes an increase in threshold of PMOS devices
which results in lower saturation current.
Bias temperature instability (BTI) is cyclic time-dependent degradation. Historically, BTI
involved Na movement within gate dielectric. Modern BTI involve accumulated charge trapping
in high-k gate dielectric.
Hot carrier degradation (HCI) occurs due to the injection of carriers from the channel into the
oxide when they acquire enough energy to become ‘hot’. Hot carriers can be generated by high
electric fields and/or high temperatures. Injected carriers can get trapped in the oxide and cause
oxide reliability issues as well as a shift in threshold voltage.
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Radiation induced damage (RBD) occurs when high energy radiation such as gamma rays or Xrays directly hits the device and knocks off electrons from the lattice. When the radiation is
strong enough, there could be permanent lattice damage because of heavy ionization.
A number of reliability issues define the viability of interconnect lines as well. They are
Electro-migration (EM) problems are caused by diffusion of interconnect metal at high current
densities. This might initially result in change of interconnect resistance which affects timing,
followed by a complete failure of the metal wire.
Stress migration (SM). The metal lines must be encapsulated in dielectrics to prevent electrical
shorts. When cooled to room temperature following high temperature processing, the differential
thermal expansion leads to enormous stress within the films. This could lead to delamination as
well as void formation. Even if the films survive the original fabrication, the transient heating
during operation could lead to similar degradation effects.
Inter-level dielectric breakdown occurs when the dielectric material separating two consecutive
metal interconnects is destroyed.
Error! Reference source not found. shows the evolution of the evolution of CMOS reliability
issues through several technology generations. In the nascent years of the microprocessor
industry, NBTI was a significant problem due to high interface defect density, as we will discuss
in detail later in the book. Over the next decade, NBTI improves in NMOS transistors due to
process improvements; however, HCI becomes the dominant problem due to the use of high
supply voltages. The HCI problem was addressed in the early nineties with VDD scaling and the
use of lightly dope drain structures. Continued oxide scaling through the nineties led to the
increase in TDDB problems, and NBTI began to re-emerge due to higher fields in the devices.
HCI still remains a challenge despite the continuous scaling in supply voltages.
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Fig. 1.3 (a) Historical perspective of reliability concerns. (b) These reliability issues can
ultimately be traced to bonds that break over time during operation.
All the aforementioned reliability issues can be ultimately traced to weak bonds that
break over time during device operation. For example, BTI, TDDB, RBD, ESD are often related
to broken bonds within gate dielectric, NBTI and HCI have been related to broken Si-H bonds
that passivate the Si/SiO2 interface, movement/disruption of metallic-bonds lead to EM, etc. A
key goal of the is course to explore the physics of the degradation mechanism clearly and in
detail.
1.6
Similar theoretical tools can address reliability and variability
Although process-induced variability and stress-dependent breaking of bonds are very different
physical phenomena and are governed by very different kinetics, the statistical aspects have
many similarities and can be analyzed with the similar theoretical tools. This means that the
spatial pattern of random defects caused during the manufacturing step could be identical to
those caused by stress extended periods of usage (Fig. 6). The probability distribution of defects,
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their influence on device performance, etc. are often indistinguishable and therefore, very similar
theoretical models can be useful.
There is one subtle, but important difference: the defects generated during extended
usage appear in a sequence in time i.e. they are time ordered and can have higher spatial
correlation. On the other hand, the complete spatial pattern of defects in the manufacturing
process appears due to the process conditions. As a result, the defect generation process can be
correlated, where existing defects dictate formation of new defects (e.g. fracture or lightning). In
contrast, the defects generated during processing formed in parallel and may not have formed in
a correlated fashion. Understanding the degree of correlation for defect generation is an
important part of reliability studies. Finally, the defect generated during processing are the initial
states for the future stress-induced defects to form, therefore a correlation between the processes
are expected as well.
Fig. 1.4 Equivalence of spatial and temporal fluctuation.
1.7
Conclusion
In this introductory lecture, we focused on the need to study reliability issues in
microelectronic devices, followed by an overview of the electronic industry. The landscape of
electronics is evolving rapidly with many new applications in energy harvesting, healthcare, and
displays. Many new material systems are being introduced, process-complexity is increasing,
and the performance is being pushed to the limit. Therefore, one needs to address increasing
diverse range of reliability issues, with an emphasis on fundamental understanding of the
degradation mechanism.
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We have distinguished between process induced variations and reliability problems, and
how they affect the performance of electronics. This was followed by a brief look at the
classification of reliability issues in microelectronics and how they evolved over time.
Over the years, three different types of reliability models have been used to predict the
reliable performance of the electronic components, namely, empirical, statistical, and physical.
The goal of the book is to develop deep physical understanding of reliability phenomena. In
chapter 2, we will consider illustrative examples of different types of reliability, so as to
precisely define of the meaning ‘physical reliability’ and distinguish it from other methods of
reliability evaluation used in computer engineering and communication systems. This distinction
will lead to (in Chapter 3) a definition of physical reliability as being ‘an extreme nonequilibrium stochastic process terminated by a threshold’ and connect to the fundamental issues
of thermodynamics and irreversibility. The rest of the book will focus on consideration of
specific degradation mechanism within this broad theoretical framework.
1.8
References
[1]
Kuhn, Kelin J., et al. "Process technology variation." Electron Devices, IEEE
Transactions on 58.8 (2011): 2197-2208.
[2]
Hiramoto, Toshiro, et al. "Direct measurement of correlation between SRAM noise
margin and individual cell transistor variability by using device matrix array." Electron
Devices, IEEE Transactions on 58.8 (2011): 2249-2256.
Takeuchi, Kiyoshi, Akio Nishida, and Toshiro Hiramoto. "Random Fluctuations in scaled
[3]
MOS devices." Simulation of Semiconductor Processes and Devices, 2009. SISPAD'09.
International Conference on. IEEE, 2009. Classification of Variability
[4]
[5]
Ghetti, A., et al. "Physical modeling of single-trap RTS statistical distribution in Flash
memories." Reliability Physics Symposium, 2008. IRPS 2008. IEEE International. IEEE,
2008.Random Dopant Fluctuation
Castellani, Niccolò, et al. "Three-dimensional electrostatics-and atomistic dopinginduced variability of RTN time constants in nanoscale MOS devices—Part I: Physical
investigation." Electron Devices, IEEE Transactions on 59.9 (2012): 2488-2494. Also
see AS Spinelli, Tutorial Lecture on Variability, European Summer School, 2012.
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[6]
Asenov, Asen, Savas Kaya, and Andrew R. Brown. "Intrinsic parameter fluctuations in
decananometer MOSFETs introduced by gate line edge roughness." Electron Devices,
IEEE Transactions on 50.5 (2003): 1254-1260.
1.9
Homework Problem
1.10
Questions/Answers
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