Download VDD Stacking with Different Adder Topologies

The Effectiveness of Stacked-VDD on Different FullAdder Topologies without Voltage Regulation
by Wenlu Sun & Jiyati Verma
ECE 6332 – Fall 2011
[email protected], [email protected]
ABSTRACT
An energy efficient way to increase VDD and limit power
dissipation by suppressing is to stack circuits that run at
fractions of total supply voltage. The limitation of this
technique is the need for voltage regulation of the middle,
free node on the output side: the more this voltage point
strays from VDD/2, the harder it is to regulate the circuit, and
designing robust voltage regulators is hard. For our project,
we experimented with full adder topology and implemented
6 single-bit blocks and cascaded them into 16-bit adders.
Two varieties of static adders were used, two types of
transmission gate adders, and two dynamic adders were
assessed. Simulation results revealed that static adders stray
the least from VDD/2.
Keywords: Stacked- VDD, Adder Topology,
1. INTRODUCTION
VDD stacking is a circuitry technique to cut down ___. Figure
1
Without voluntary voltage regulation, the middle node of the
circuit on the output side is free to float with respect to
ground. Ideally, the voltage drop is the same across both the
bottom half and top half of the circuit and the currents
passing through the two halves are also equal all the time. In
reality, passing different input signals causes the current to
wobble. That current occurs because…. So what we care
about is the noise that appears at that middle node, and the
less noise, the less robust the voltage regulator needs to be.
And designing regulators is hard, so any way to alleviate that
electrical strain is useful. Assuming the circuit needs to
function as two independent 2-digit 16-bit binary adders, our
project aimed to determine which topology would have the
smallest noise margins.
Previous work in this area: A lot of work on speeding up
adders, and stacked- VDD A study involving adders and VDD
stacking is hard to find.
2. METHODOLOGY
Using Cadence, we simulated the effect of VDD stacking on a
variety of 16-bit adder topologies.
The topologies
implemented were CMOS static, Mirror Adder (static),
transmission function full adder [1], and transmission gate [1],
NP CMOS dynamic adder [from book], and the ___ dynamic
adder [1]. Be specific about the topologies used: make
citations here. Why did we choose these particular
Without stacking, we used transistors that would operate at 1.1
V VDD. With VDD stacking, the two tiers of adders would need
one 2.2 V-voltage source.
Initial Hypothesis. Suppose that [citation] if the two blocks of
circuitry somehow are symmetric, then the overall circuit is
able to balance current better. Instead of trying to judge
whether static, dynamic, or transmission gate adders are
naturally better at balancing current using just one type of
each, we did two of each type to get a slightly better idea of
how these three particular families of adders balance current.
Here are all the circuit schematics: diagrams for clarification
and implementation in Cadence. Sizing done in the ___
fashion. Cin = A justified by (does this give the worst case
noise? the worst case noise?). Benefits of the static designs
chosen. Benefits of
1.1 Problem Statement
So for all intensive purposes, in VDD stacking without voltage
regulation, the middle node is kept floating.
We
implemented this circuit (Figure 1) technique was in Cadence
using six different topologies: CMOS static, Mirror Adder
(static), transmission function full adder, and transmission
gate __, ___ dynamic, and the ___ dynamic adder. For a
variety of full adder technologies, we took a single-bit full
adder block, and cascaded for 16-bits. Using Cadence, we
simulated stacked-VDD with each of these different
topologies. In particular, we aimed to see which of the adder
topologies balanced the current coming out of the middle
node naturally.
Claim:
Figure 1- VDD stacked circuit applied to each adder
topology. More details here?
For the dynamic full adders, 10-nanosecond pulses in a 50/50
duty cycle made up the clock signal. Dynamic is an
alternative logic style to design a logic function. It has some
advantages in comparison with static mode such as faster
switching speeds, no static power consumption, non-ratioed
logic, full swing voltage levels and less number of
transistors. For an N input logic function, it requires N+2
transistors versus 2N transistors in the standard CMOS logic.
It only consumes the dynamic power. Finally high speed is
the distinct specification of this logic style.
[One graphic of how the rippling was done in the sim] The
adder’s carry out signals rippled onto the following adder
block.
[At least one graphic of this transient] Transient output
generated for A0 going from 10, B0 going from 01, A1
going from 01, and B1 going from 10. Claim: When
inputs of FA0 and FA1 swing in opposite directions then the
greatest amount of noise occurs at the output, causing the
most imbalanced Vmiddle conditions.
Transient reponse goes from 1.295 to 1.049 V. That’s 0.195
above 1.1 V and 0.051 V below VDD. Percents: 17.7% above
and 4.63% below.
3.4 14-Transistor Transmission Gate Adder
(14-T)
Transient reponse goes from 1.365 to 0.790 V. That’s 0.265 V
above 1.1 and 0.310 V below VDD. Percents: 24.1% above and
28.2% below.
Looks like short circuits happen when __ happens.
3.5 NP CMOS Dynamic Adder (NP-Dyn)
Transient reponse goes from 1.335 to 0.7 V. That’s 0.235
above 1.1 V and 0.4 V below VDD. Percents: 21.4% above and
36.4% below.
3.6 NP CMOS Dynamic Adder #2
Transient reponse goes from 1.406 to 0.861 V. That’s 0.306
above 1.1 V and 0.239 V below VDD. Percents: 27.8% above
and 21.7% below.
Safe to say this did the worst.
Figure 2- Cadence schematic of 16-bit adder implementation.
3. SIMULATION RESULTS
4. DISCUSSION
Reasons:
Evidence:
When this input pattern is applied, what is the output
supposed to be for all of them?
Graphs show the voltage noise of the central point. Besides
the smooth __ RC curves of discharging and charging noise
exists in different places, so each of these adders had a
unique signature
In general, the static CMOS full adders did the best at
balancing current. Let’s see why.
Why did __ do the best at current balancing?
Why did __ do the worst at current balancing?
What are the characteristics of adders that can balance current
well?
3.1 CMOS Static Adder (CSA)
Transient reponse goes from 1.205 to 1.050 V. That’s 0.105
above 1.1 V and 0.050 V below VDD. Percents: 9.55% above
and 4.55% below.
Inputs and outputs…
Safe to say, this did the best.
3.2 Mirror Adder (MA)
Transient reponse goes from 1.148 to 0.985 V. That’s 0.048
above 1.1 V and 0.115 V below VDD. Percents: 4.36% above
and 10.5% below.
3.3 Transmission Function Adder (TFA)
For dynamic full adders, It’s clear that in making the unit fast,
we compromise the stability of the middle voltage point by far.
Charge sharing?
The static adders gain stability by utilizing their delay in the
right way.
The transmission gate adders have charge sharing issues?
5. CONCLUSION
Noise reduction is necessary. To use VDD stacking, usually a is
needed to maintain the voltages using voltage regulator. But
building an effective voltage regulator is an additional
problem: it is difficult to make a good one because __, __, __.
In particular, we aimed to see which of the adder topologies
balanced the current coming out of the middle node naturally.
Since __ balanced the current as it was.
To alleviate the pin limitation problem, a stacked-Vdd circuit
paradigm has recently been proposed in the literature.
However, for a circuit designed using this paradigm, a
significant amount of power may be wasted if modules are
not carefully assigned to different Vdd domains.
Further work could cascade two or more 16-bit adders for
each topology. This would probably give a more realistic
idea of how these circuits balance current overall. Also we
could make this into a 4-digit 16-bit adder if we coordinated
the 16-bit adder above with the one below. But this would
probably require up or down converters for the pertinent
inputs and outputs.
6. ACKNOWLEDGMENTS
Wenlu Sun did all the Cadence simulations. Jiyati Verma
did the Wiki page and most of the documentation, and drew
up the slides for the presentation. It is fair to say that both
did 50% of the project.
7. REFERENCES
[1] Massim Alioto and Gaetano Palumbo, “Analysis and
Comparison on Full Adder Block in Submicron
Technology”, IEEE Transactions on VLSI Systems
10(6), December 2002.
[2] R. F. Mirzaee, M. H. Moaiyeri, K. Navi, “High Speed
NP-CMOS and Multi-Output Dynamic Full Adder
Cells”, International Journal of Electrical and
Electronics Engineering 4(4), Spring 2010.
[3] R. Zimmermann et al. “Low-Power Logic Styles:
CMOS Versus Pass-Transistor Logic”, IEEE Journal of
Solid-State Circuits, 32(7), 1997.