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CHAPTER 14 Exercises E14.1 (a) iA vA RA iB vB RB iF iA iB v A vB RA RB v v vo RF iF RF A B RA RB v (b) For the vA source, RinA A RA . iA (c) Similarly RinB RB . (d) In part (a) we found that the output voltage is independent of the load resistance. Therefore, the output resistance is zero. E14.2 (a) i1 v in 1 mA R1 i2 i1 1 mA v o R2i2 10 V 404 io vo 10 mA RL ix io i2 11 mA (b) v in 5 mA R1 v i3 3 5 mA R3 i1 i2 i1 5 mA v 3 R2i2 5 V i4 i2 i3 10 mA v o R4i4 R2i2 15 V E14.3 Direct application of circuit laws gives i1 v1 , R1 i2 i1 , and v 3 R2i2 . From the previous three equations, we obtain v 3 applying circuit laws gives i3 R2 v 2v 1 . Then R1 1 v3 v , i 4 2 , i5 i3 i4 , and v o R5i5 . R3 R4 405 These equations yield v o R5 R v 3 5 v 2 . Then substituting values and R3 R4 using the fact that v 3 2v 1 , we find v o 4v 1 2v 2 . E14.4 (a) v s v in R2i2 v in (Because of the summing-point restraint, i2 0. ) i1 v in v s 0 R1 i3 i1 0 (Because v s v in . ) iin i1 i2 0 v o R3i3 v s v in Thus, Av v vo 1 and Rin in . v in iin (b) (Note: We assume that R1 R2 R3 . ) v in v in R1 R v i3 i1 in R1 i1 i2 v in v in R2 R v o R3i3 iin i1 i2 R3 v in v in R1 406 2v in R Rin Av vo 1 v in R 2 E14.5 From the circuit, we can write vF v in , iF equations, we find that io vF , and io iF . From these RF v in . Then because io is independent of RL, we RF conclude that the output impedance of the amplifier is infinite. Also Rin is infinite because iin is zero. E14.6 (a) v1 v in i1 v1 R1 v 2 R2i1 R1i1 i2 v2 R1 i3 i1 i2 v o R2i3 v 2 Using the above equations we eventually find that 2 R R v Av o 1 3 2 2 v in R1 R1 (b) Substituting the values given, we find Av = 131. (c) Because iin = 0, the input resistance is infinite. (d) Because vo Avv in is independent of RL, the output resistance is zero. 407 E14.7 R2 from which we conclude that Rs R1 R2max 499 1.01 10.20 Rs min R1 min 0 49.9 0.99 We have Avs Avs max Avs min R2 min 499 0.99 9.706 Rs max R1 max 0.500 49.9 1.01 E14.8 Applying basic circuit principles, we obtain: v1 R1 Rs 1 v2 iB RB Rs 2 i1 vA RA v A R2i1 iA if iA iB v o Rf if From these equations, we eventually find vo E14.9 Rf Rf R2 v1 v Rs 1 R1 RA Rs 2 RB 2 Many correct answers exist. A good solution is the circuit of Figure 14.11 in the book with R2 19R1 . We could use standard 1%-tolerance resistors with nominal values of R1 1 k and R2 19.1 k. E14.10 Many correct answers exist. A good solution is the circuit of Figure 14.18 in the book with R1 20Rs and R2 25(R1 Rs ). We could use 408 standard 1%-tolerance resistors with nominal values of R1 20 k and R2 515 k. E14.11 Many correct selections of component values can be found that meet the desired specifications. One possibility is the circuit of Figure 14.19 with: R1 a 453-k fixed resistor in series with a 100-k trimmer (nominal design value is 500 k) RB is the same as R1 R2 499 k RA 1.5 M Rf 1.5 M After constructing the circuit we could adjust the trimmers to achieve the desired gains. E14.12 fBCL A f ft 10 5 40 0OL BOL 40 kHz The corresponding Bode plot is A0CL A0CL 100 shown in Figure 14.22 in the book. E14.13 (a) fFP SR 5 10 6 198.9 kHz 2πVom 2π (4) (b) The input frequency is less than fFP and the current limit of the op amp is not exceeded, so the maximum output amplitude is 4 V. (c) With a load of 100 the current limit is reached when the output amplitude is 10 mA 100 = 1 V. Thus the maximum output amplitude without clipping is 1 V. (d) In deriving the full-power bandwidth we obtained the equation: 2πfVom SR Solving for Vom and substituting values, we have Vom SR 5 10 6 0.7958 V 2πf 2π10 6 With this peak voltage and RL = 1 k, the current limit is not exceeded. 409 (e) Because the output, assuming an ideal op amp, has a rate of change exceeding the slew-rate limit, the op amp cannot follow the ideal output, which is v o (t ) 10 sin(2π10 6t ) . Instead, the output changes at the slew-rate limit and the output waveform eventually becomes a triangular waveform with a peak-to-peak amplitude of SR (T/2) = 2.5 V. E14.14 (a) Applying basic circuit laws, we have iin equations yield Av (b) R vo 2. v in R1 410 v in andv o R2iin . These R1 Applying basic circuit principles, algebra, and the summing-point restraint, we have R R2 v v x v y Rbias I B i1 x bias I B I R1 R1 R1 R2 B R2 R1 IB i2 IB i1 1 I R1 R2 B R1 R2 R1 v o R2i2 v x R2 I Rbias I B 0 R1 R2 B (c) The drop across Rbias is zero because the current through it is zero. For the source Voff the circuit acts as a noninverting amplifier with a gain R Av 1 2 11. Therefore, the extreme output voltages are given by R1 v o AvVoff 33 mV. (d) Applying basic circuit principles, algebra, and the summing-point restraint, we have 411 v x v y Rbias I off 2 i1 R2 I off R1 2R2 I off i1 1 2 R1 R2 2 R1 R2 2 I R 2R2 I off vo R2i2 v x R2 1 Rbias off R2Ioff R1 R2 2 2 i2 I off R2 I off v x Rbias I off R1 R1 2 R1 R2 2 Thus the extreme values of vo caused by Ioff are Vo ,Ioff 4 mV. (e) The cumulative effect of the offset voltage and offset current is that Vo ranges from -37 to +37 mV. E14.15 (a) Because of the summing-point constraint, no current flows through Rbias so the voltage across it is zero. Because the currents through R1 and R2 are the same, we use the voltage division principle to write R1 v 1 vo R1 R2 Then using KVL we have v in 0 v 1 These equations yield R v Av o 1 2 v in R1 Assuming an ideal op amp, the resistor Rbias does not affect the gain since the voltage across it it zero. (b) The circuit with the signal set to zero and including the bias current sources is shown. 412 We want the output voltage to equal zero. Using Ohm’s law, we can write v 2 RbiasI B . Then writing a current equation at the inverting input, we v v have I B 1 1 0 . Finally, because of the summing-point restraint, R1 R2 we have v 2 v1 . These equations eventually yield 1 Rbias 1 / R1 1 / R2 as the condition for zero output due to the bias current sources. E14.16 Because no current flows into the op-amp input terminals, we can use the voltage division principle to write R4 v x v1 R3 R4 Because of the summing-point restraint, we have R4 v x v y v1 R3 R4 Writing a KCL equation at the inverting input, we obtain v y v 2 v y vo 0 R1 R2 413 Substituting for vy and solving for the output voltage, we obtain R4 R1 R2 R vo v1 v2 2 R3 R4 R1 R1 If we have R4 / R3 R2 / R1 , the equation for the output voltage reduces to vo E14.17 R2 v v 2 R1 1 t t 1 v in (t )dt 1000 v in (t )dt (a) v o (t ) RC 0 0 t 1000 5dt 5000t for 0 t 1 ms 0 t 1 ms 1000 5dt - 5dt 10 5000t for 1 ms t 3 ms 1 ms 0 and so forth. A plot of vo(t) versus t is shown in Figure 14.37 in the book. (b) A peak-to-peak amplitude of 2 V implies a peak amplitude of 1 V. The first (negative) peak amplitude occurs at t 1 ms . Thus we can write 1 1 RC 1 ms v indt 0 1 10 4 C 1 ms 5dt 0 1 5 10 3 4 10 C which yields C 0.5 μF. E14.18 The circuit with the input source set to zero and including the bias current sources is: Because the voltage across R is zero, we have iC = IB, and we can write 414 1 vo C t 1 0 iC dt C t I B dt 0 100 10 9t C (a) For C = 0.01 F we have v o (t ) 10t V. (b) For C = 1 F we have v o (t ) 0.1t V. Notice that larger capacitances lead to smaller output voltages. E14.19 v y v x I B RB iC iR I B 0 iR v y / RB I B Because iC 0 , we have v C 0, and v o v y I B R 1 mV. E14.20 iin C E14.21 dv in dt v o (t ) Riin RC The transfer function in decibels is H0 H (f ) dB 20 log 1 f / f 2n B For f fB , we have 415 dv in dt H0 20 log H 0 20n logfB 20n log(f ) H (f ) dB 20 log f / f 2n B This expression shows that the gain magnitude is reduced by 20n decibels for each decade increase in f. E14.22 Three stages each like that of Figure 14.40 must be cascaded. From Table 14.1, we find that the gains of the stages should be 1.068, 1.586, and 2.483. Many combinations of component values will satisfy the requirements of the problem. A good choice for the capacitance value is 0.01 F, for which we need R 1 /(2πCfB ) 3.183 k. Also Rf 10 k is a good choice. Problems P14.1 The differential voltage is: vid v1 v2 and the common-mode voltage is: v icm 21 v 1 v 2 P14.2 An ideal operational amplifier has the following characteristics: 1. Infinite input impedance. 2. Infinite gain for the differential input signal. 3. Zero gain for the common-mode input signal. 4. Zero output impedance. 5. Infinite bandwidth. P14.3* v id v 1 v 2 cos( 2000πt ) P14.4 The terminals of a real op amp include the inverting input, the noninverting input, the output, and one or more power-supply terminals. P14.5 According to the summing-point constraint, the output voltage of an op amp assumes the value required to produce zero differential input voltage and zero current into the op-amp input terminals. This principle applies when negative feedback is present but not when positive feedback is present. v icm 416 1 2 v 1 v 2 20 cos(120πt ) P14.6* The steps in analysis of an amplifier containing an ideal op amp are: 1. Verify that negative feedback is present. 2. Assume that the differential input voltage and the input currents are zero. 3. Apply circuit analysis principles including Kirchhoff’s and Ohm’s laws to write circuit equations. Then solve for the quantities of interest. P14.7 The inverting amplifier configuration is shown in Figure 14.4 in the text. The voltage gain is given by Av R2 R1 , the input impedance is equal to R1, and the output impedance is zero. P14.8 This is an inverting amplifier having a voltage gain given by Av R2 R1 3 . Thus we have vo t 3 2 cos2000πt Sketches of vin(t) and vo(t) are P14.9* The circuit has negative feedback so we can employ the summing-point constraint. Then successive application of Ohm’s and Kirchhoff’s laws starting from the left-hand side of the circuit produces the results shown: 417 From these results we can use KVL to determine that v o 8v in from which we have A v 8. P14.10 This circuit has positive feedback and the output can be either +10 V or 10 V. Writing a current equation at the inverting input terminal of the op amp we have v x 2 v x vo 0 1000 2000 Solving we find v x 1.3333 0.3333v o For v o 10 V, we have v x 4.333 V. On the other hand for v o 10 V, we have v x 2 V. Notice that for vx positive the output remains stuck at its positive extreme and for vx negative the output remains stuck at its negative extreme. P14.11 Using the summing-point constraint, we have v iD in I s exp(v D / nVT ) and vo vD R Solving, we have v vo nVT ln in RI s 418 P14.12 Using the summing-point constraint, we have iD I s exp(v in / nVT ) and vo RiD Thus, we have vo RI s exp(v in / nVT ) P14.13 Using the summing-point constraint, we have v iD in KvD2 and vo vD R Solving, we have v v o in KR P14.14 The noninverting amplifier configuration is shown in Figure 14.11 in the text. Assuming an ideal op amp, the voltage gain is given by Av 1 R2 R1 , the input impedance is infinite, and the output impedance is zero. P14.15* The circuit diagram of the voltage follower is: Assuming an ideal op amp, the voltage gain is unity, the input impedance is infinite, and the output impedance is zero. P14.16 If the source has a non-zero series impedance, loading (reduction in voltage) will occur when the load is connected directly to the source. On the other hand, the input impedance of the voltage follower is very high (ideally infinite) and loading does not occur. If the source impedance is very high compared to the load impedance, the voltage follower will deliver a much larger voltage to the load than direct connection. 419 P14.17 (a) vo 1 k 2 mA 2 V (b) vo 6 0 5 1 V (c) No current flows through the 3-k resistor. Thus vo 0 1 4 3 V . (d) vo 0 420 (e) vo 5 2 3 V P14.18 From the circuit we can write: vo 1 v 3 v i4 i3 o 1 R Thus we have v 4 v 3 vo 1 vo 2 v 3 v 4 2vo 1 v v iin o 1 o 2 0 4R 4R v iin in R v in v o 1 v o 2 0 R 4R 4R 421 A1 A2 vo 1 4 3 v in vo 2 2vo 1 2A1 8 3 v in v in P14.19* The circuit diagram is: Writing a current equation at the noninverting input, we have v1 v A v1 vB 0 RA RB (1) Using the voltage-division principle we can write: R1 v1 vo R1 R2 (2) Using Equation (2) to substitute for v1 in Equation (1) and rearranging, we obtain: R R2 v ARB vB RA vo 1 R1 RA RB P14.20 Analysis of the circuit using the summing-point constraint yields R R v o 24 v in 1 24 10 10 Substituting the expression given for vin yields R R R v o 2 24 3 24 cos( 2000t ) 1 24 10 10 10 422 Then setting the dc component to zero, we have R R 0 2 24 1 24 10 10 which yields R2 = 10 k. P14.21 (a) v 1 0 Rio 0 v 2 io v1 v2 R Since io is independent of the load, the output impedance is infinite. (b) The circuit diagram is: 423 Writing KVL around loop #1, we have v in Riin 0 Riin Writing KVL around loop #2, we have Riin Rf io Riin 0 Algebra produces io v in Rf . Since io is independent of the load, the output impedance is infinite. P14.22 (a) This is an inverting amplifier having Av R2 R1 and Rin R1 . The v s2 v s2 input power is Pin Rin R1 v o2 The output power is Po RL 2 R22 Po v o RL 2 R1 The power gain is G Av Pin v s2 R1 RL R1RL (b) This is a noninverting amplifier having iin 0 . Therefore Pin 0 , and G . Thus, the noninverting amplifier has the larger power gain. P14.23* (a) v o Rf iin (b) Since vo is independent of RL, the output behaves as a perfect voltage source, and the output impedance is zero. (c) The input voltage is zero because of the summing-point constraint, and the input impedance is zero. (d) This is an ideal transresistance amplifier. 424 P14.24 The inverting amplifier is shown in Figure 14.4 in the text and the voltage gain is Av R2 R1 . Thus to achieve a voltage gain magnitude of 2, we would select the nominal values such that R2nom 2R1nom . However for 5%tolerance resistors, we have R1 min 0.95R1nom R1 max 1.05R1nom R2 min 0.95R2nom R2 max 1.05R2nom Thus we have Av min R2 min 0.95R2nom 1.81 R1 max 1.05R1nom Av max R2 max 1.05R2nom 2.21 R1 min 0.95R1nom Thus Av 2 plus 10.5% minus 9.5%. P14.25 The noninverting amplifier is shown in Figure 14.11 in the text, and the voltage gain is Av 1 R2 R1 . Thus to achieve a voltage gain magnitude of 2, we would select the nominal values such that R2nom R1nom . However for 5%-tolerance resistors, we have R1 min 0.95R1nom R1 max 1.05R1nom R2 min 0.95R2nom R2 max 1.05R2nom Thus we have Av min 1 R2 min 0.95R2nom 1 1.905 R1 max 1.05R1nom Av max 1 R2 max 1.05R2nom 1 2.105 R1 min 0.95R1nom Thus Av 2 5%. 425 P14.26* The circuit diagram is: R io 1 1 iin R2 Because Because infinite. behaves of the summing-point constraint, we have vin 0. Thus Rin 0. the output current is independent of RL, the output impedance is In other words looking back from the load terminals, the circuit like an ideal current source. P14.27 By the voltage-division principle, we have RT vx v in Tv in RT 1 T R Then, we can write v v x v in 1 T ix in R R v o Rix v x v in 1 T Tvin v in 2T 1 426 Thus, as T varies from 0 to unity, the circuit gain varies from -1 through to 0 to +1. P14.28 (a) This circuit has negative feedback. It is the voltage follower and has unity gain except that the output voltage cannot exceed 5 V. The output waveform is: (b) This circuit has positive feedback, and vo = +5 if the differential input voltage vid is positive. On the other hand, vo = -5 if vid is negative. In this circuit, we have v id vo v in Thus, the output waveform is: 427 P14.29* (a) This circuit has negative feedback. Assuming an ideal op amp, we have vo t vin t . (b) This circuit has positive feedback. Therefore, the summing-point constraint does not apply. From the circuit, we can write v id v in v id v o 0 R R Solving for vid, we have v v in v id o 2 If vid > 0, then vo = +5. On the other hand, if vid < 0, then vo = -5. The output waveform is 428 P14.30 Very small resistances lead to excessively large currents, possibly exceeding the capability of the op amp, creating excessive heat or overloading the power supply. Very large resistances lead to instability due to leakage currents over the surface of the resistors and circuit board. Stray pickup of undesired signals is also a problem in high-impedance circuits. P14.31 Use the inverting amplifier configuration: Pick R2nom = 10R1nom to achieve the desired gain magnitude. Pick R1nom > 10 kΩ to achieve input impedance greater than 10 kΩ. Pick R1nom and R2nom < 10 MΩ because higher values are impractical. Many combinations of values will meet the specifications. For example: (a) Use 5% tolerance resistors. R1 = 100 kΩ and R2 = 1 MΩ. (b) Use 1% tolerance resistors. R1 = 100 kΩ and R2 = 1 MΩ. (c) R2 =1 MΩ 1% tolerance. R1 = 95.3 kΩ 1% tolerance fixed resistor in series with a 10-kΩ adjustable resistor. After constructing the circuit, adjust to achieve the desired gain magnitude. P14.32* To achieve high input impedance and an inverting amplifier, we cascade a noninverting stage with an inverting stage: 429 The overall gain is: R R2 R4 Av 1 R1 R3 Many combinations of resistance values will achieve the given specifications. For example: R1 and R2 0 . (Then the first stage becomes a voltage follower.) This is a particularly good choice because fewer resistors affect the overall gain, resulting in small overall gain variations. R4 = 100 kΩ, 5% tolerance. R3 = 10 kΩ, 5% tolerance. P14.33 We use a noninverting amplifier and place a resistor in parallel with the input terminals to achieve the desired input impedance. R1 = 1 kΩ, 1% tolerance. Many combinations of values for R2 and R3 will meet the given specifications. For example: R2 = 1 kΩ, 1% tolerance. R3 = 9.09 kΩ, 1% tolerance. (These values result in a nominal gain of 10.09, which is within the specified range.) P14.34 Here are two answers: 430 Many other correct answers exist. P14.35* One possibility is to place unity-gain voltage follower circuits between the sources and the input terminals of the circuits designed for Problem P14.34. A better answer (because it requires fewer op amps) is: All resistors are 1% tolerance. P14.36 To avoid excessive variations in Avs vo v s because of changes in Rs, we need to have Rin Rs . Rin =100 kΩ is sufficiently large. Thus, a suitable circuit is R1 and R2 should be 1% tolerance resistors. P14.37 To avoid excessive gain variations because of changes in the source resistances, we need to have input resistances that are much greater 431 than the source resistances. Many correct answers exist. Here is one possibility: The fixed resistors should be specified to have a tolerance of 1% because they are more stable in value than 5% tolerance resistors. The adjustment procedure is: 1. Set v1 = 0 and v2 = + 1 V. Then, adjust the 2-kΩ potentiometer to obtain vo = 3 V. 2. Set v1 = 1 V and v2 = 0. Then, adjust the 1-kΩ potentiometer to obtain vo = -10. P14.38* A solution is: P14.39 (a) 432 From the circuit, we can write: v s Rin is Ro is AOL Rin is v o Ro is AOL Rin is Dividing the respective sides of the previous equations yields: Ro AOL Rin v Avo o v s Rin Ro AOL Rin (b) Substituting values, we obtain: 25 10 5 10 6 Avo 6 10 25 10 5 10 6 0.99999 (compared to unity for an ideal op amp) vs Z in Rin Ro AOL Rin is 10 6 25 10 5 10 6 1011 (compared to ∞ for an ideal op amp) (c) The circuit for determining the output impedance is: v i v x v AOLv i v ix x x Rin Ro v 1 Zo x 1 AOL 1 ix Rin Ro Z o 2.5 10 4 (versus Zo = 0 for an ideal op amp) P14.40 (a) From the circuit (shown in Figure P14.40 in the text), we can write: v s vi vo vi vi 0 R1 R2 Rin v o v i v o AOLv i 0 R2 Ro Algebra results in: 433 Avo vo vs R2 1 1 1 Ro R2 R22 R1 1 R R R in 2 AOL R2 Ro 1 Substituting values, we obtain: Avo 9.9989 (compared to -10 for an ideal op amp) (b) From the circuit, we can write: v s Ri is v i v i R2 Ro v i Rin is AOLv i 0 Algebra results in R2 Ro v Z in s R1 is 1 AOL R2 Ro Rin Substituting values, we obtain: Z in 1.0001 k (compared to 1 kΩ for an ideal op amp (c) To find the output impedance, we zero the input source and connect a test source to the output terminals. The circuit is: Rin 1 where Rin vx 1 R1 1 Rin R2 Rin v AOLv i vx ix x R2 Rin Ro v 1 Zo x AOL Rin 1 1 ix R2 Rin Ro Ro R2 Rin vi Substituting values, we obtain: Z o 2.75 10 3 versus Z o 0 for an ideal op amp P14.41* Equation 14.34 states: ft A0CLfBCL A0OLfBOL 434 Thus, for A0CL = 10, we have f 15 MHz fBCL t 1.5 MHz A0CL 10 For A0CL = 100, we have fBCL = 150 kHz P14.42 Equation 14.23 gives the open-loop gain as a function of frequency: A0OL 200 10 3 AOL f 1 j f fBOL 1 j f 5 For f = 100 Hz, we have 200 10 3 AOL 100 1 j 100 5 A0OL AOL 100 9987 2 1 f fBOL Similarly, we have AOL 1000 1000 AOL 10 6 1 P14.43 Equation 14.32 gives the closed-loop gain as a function of frequency: A0CL ACL f 1 j f fBCL However, the dc closed-loop gain is given as 10 so we have 10 ACL f 1 j f fBCL For f = 10 kHz, we have 10 ACL 9 2 1 10 4 fBCL Solving, we find fBCL 20.65 kHz. Then the gain bandwidth product is ft A0CLfBCL 206.5 kHz A0OLfBOL P14.44 Equation 14.32 gives the closed-loop gain as a function of frequency: A0CL ACL f 1 j f fBCL 435 The phase shift is arctan(f / fBCL ). Thus at 200 kHz, we have 10 arctan[( 2 10 5 ) / fBCL ] which yields fBCL 1.134 MHz. Then the gain bandwidth product is ft A0CLfBCL 11.34 MHz A0OLfBOL . P14.45 Alternative 1: fBCL ft 10 6 10 kHz A0CL 100 ACL f 100 1 jf 10 4 The closed-loop bandwidth is fBCL 10 kHz . Alternative 2: For each stage, we have fBCL ft 10 6 100 kHz and the A0CL 10 gain as a function of frequency is: 10 ACL f 1 jf 10 5 The overall gain is 100 A f 1 jf 10 5 2 To find the overall 3-dB bandwidth, we have 436 A f3dB 100 100 2 2 1 f3dB 10 5 Solving, we find that f3dB 64.4 kHz Thus, the two-stage amplifier has wider bandwidth. P14.46* P14.47 SR 10 7 159 kHz 2πVom 2π10 (a) fFP (b) Vom 10 V . (It is limited by the maximum output voltage capability of the op amp.) (c) In this case, the limit is due to the maximum current available from the op amp. Thus, the maximum output voltage is: Vom 20 mA 100 2 V (d) In this case, the slew-rate is the limitation. v o t Vom sinωt dv o t ωVom cosωt dt dv o t ωVom SR dt max 437 Vom (e) P14.48 SR 10 7 1.59 V ω 2π10 6 The desired output voltage is v o t Vom sinωt and the rate of change of the output is dv o t ωVom cosωt dt The maximum rate of change of the output is dv o t ωVom dt max Thus, we require the slew rate to be at least as large as the maximum rate of change of the output voltage. SR ωVom 2π10 5 5 3.14 V μs P14.49 To avoid slew-rate distortion, the op-amp slew-rate specification must exceed the maximum rate of change of the output-voltage magnitude. For the gain and input given in the problem, the output voltage is v o (t ) 0 t 0 10t exp( t ) t 0 The rate of change is dv o (t ) 0 t 0 dt 10 exp( t ) 10t exp( t ) t 0 438 The maximum value occurs at t = 0, and is 10 V/s. Thus the required minimum slew-rate specification is 10 V/s or 107 V/s. P14.50 To avoid slew-rate distortion, the op-amp slew-rate specification must exceed the maximum rate of change of the output-voltage magnitude. For a voltage follower, the gain is unity. For the input given in the problem, the output voltage is v o (t ) 0 t 0 t 2 9 0 t 3 3 t The rate of change is vo (t ) 0 t 0 2t 0 0 t 3 3 t The maximum value occurs at t = 3, and is 6 V/s. Thus, the required minimum slew-rate specification is 6 V/s or 6106 V/s. P14.51* The output waveform is The rate of change is: SR 4 V 0.5 μs 8 V μs P14.52 SR 10 6 15.9 kHz 2πVom 2π 10 (a) fFP (b) The limit on peak output voltage is due to the current limit of the op amp. Because R2 is much greater than RL, the current through R2 can be neglected. Thus, we have: Vom 25 mA RL 2.5 V (c) In this case, Vom 10 V . (This is the maximum voltage that the op amp can achieve.) 439 P14.53 (d) In this case, the slew rate limits the maximum voltage. SR 10 6 Vom 1.59 V 2πf 2π10 5 (a) One op amp is configured as an inverting amplifier with a gain of -2 and the other op amp is configured as a noninverting amplifier with a gain +2. Thus, we can write: v 2 t 2v s t v 1 t 2v s t vo t v 1 t v 2 t 4v s t Av v o v s 4 (b) (c) The peak value of vo t at the threshold of clipping is 28 V. P14.54* See Figure 14.29 in the text. P14.55 The net effect of bias currents, offset current and offset voltage is to add a constant (dc) term to the desired output signal. Often this is undesirable. P14.56 A FET-input op amp has much lower values of bias current and offset current than a BJT-input op amp. 440 P14.57* The worst-case outputs due to the offset voltage are: R Vo ,voff Voff 1 2 44 mV R1 For the bias current, the worst case output voltages are: Vo ,bias R2I B 10 mV and 20 mV For the offset current, the worst-case output voltages are: Vo ,ioff R2 I off 2 2.5 mV Due to all of the imperfections, the extreme output voltages are: Vo . max 44 20 2.5 66.5 mV Vo ,min 44 10 2.5 36.5 mV P14.58 The circuit shown in Figure P14.58 is a poor design because no dc path is provided for the bias current flowing into the noninverting input terminal. The bias current would charge the capacitance eventually resulting in a large voltage that would exceed the linear range of the op amp. The solution is to add a resistance as shown: To minimize the effect of the bias currents, we should select: 1 RB 1 R1 1 R2 P14.59 (a) The circuit with the signal source zeroed and including the offset voltage source is: The output voltage is: 441 Vo ,voff 1 R2 R1 Voff 11Voff Thus to keep Vo ,voff less than 100 mV in magnitude, we need an op amp with Voff that is less than 9.09 mV. (b) The circuit with only the bias current sources is: The output voltage is: Vo ,bias R2I bias Thus to keep Vo ,bias less than 100 mV in magnitude, we need an op amp with I bias less than 1μA. (c) If we add a resistance Rbias 1 /(1 / R1 1 / R2 ) 9.09 k in series with the noninverting input terminal, the effects of the bias currents will cancel. The circuit is: (d) With the resistance of part (c) in place, the output voltage due to the offset current is: Vo ,ioff R2Ioff Thus to keep Vo ,ioff less than 100 mV in magnitude, we need an op amp with I off less than 1 μA. P14.60* The circuit diagram is shown in Figure 14.33 in the text. To achieve a nominal gain of 10, we need to have R2 = 10R1. Values of R1 ranging from 442 about 1 kΩ to 100 kΩ are practical. A good choice of values is R1 = 10 kΩ and R2 = 100 kΩ. P14.61 The circuit diagram is shown in Figure 14.34 in the text. To achieve a nominal gain of 10, we need to have R2 = 9R1. Values of R1 ranging from about 1 kΩ to 100 kΩ are good. A good choice of values is R1 = 20 kΩ andR2 = 180 kΩ. Any value of R in the range from 1 kΩ to 1 MΩ is acceptable. P14.62 (a) The differential and common-mode components of the input signal are: v id v 1 v 2 cos( 2000πt ) v icm 21 (v 1 v 2 ) 2 cos(120πt ) (b) As discussed in the book, the first-stage gain for the differential signal is 1 R2 / R1 which for the values given is 10. On the other hand, the first-stage gain for the common-mode component is unity. Thus the output voltages are: v X 1out 5 cos( 2000πt ) 2 cos(120πt ) v X 1out 5 cos( 2000πt ) 2 cos( 120πt ) (c) Assuming ideal op amps and perfectly matched components, the output of the circuit is v o (t ) 1 R2 / R1 v 1 v 2 10 cos( 2000πt ) P14.63* This is an integrator circuit, and the output voltage is given by: t 1 v o t v in t dt RC 0 t v o t 50 v in t dt 0 443 Each pulse reduces vo by 0.5 V. Thus, 20 pulses are required to produce vo = -10V. P14.64 This is a differentiator circuit, and the output is given by: dv in t dt dv t 10 3 in dt A sketch of vo t versus is: v o t RC P14.65 Let x t displacement in meters. Then, we have v in t 100x t and we want dx t dt dv t 0.01 in dt v 1 t and v 2 t d 2 x t dt 2 444 dv 1 t dt A circuit that produces the desired voltages is: We need R1C 1 0.01, R2C 2 1, and R3 R4 . Suitable component values are: R1 R2 1 M C 2 1.0 μF C 1 0.01 μF R3 R4 10 k P14.66* All of the circuits are of the form: This is the inverting amplifier configuration and the gain is A f (a) Z Vo 2 Vin Z1 10R 10 1 1 jfB f R jωC 1 where fB 2πRC A f 445 The magnitude Bode plot is: (b) f R 1 / jωC 1 j B R f 1 where fB 2πRC A f The magnitude Bode plot is: (c) 1 1 R jωC 1 A f R 1 jf fB 1 where fB 2πRC 446 The magnitude Bode plot is: P14.67 The gain is: 1 jC 1 1 A f R jRC jf / 7.96 In decibels, the gain magnitude is 20 log A(f ) 20 log(f / 7.96) The sketch is: 447 P14.68 The gain is: A f R jRC j (f / 159.2) 1 jC In decibels, the gain magnitude is 20 log A(f ) 20 log(f / 159.2) The sketch is: 448