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Impact of Pass-Transistor Logic (PTL) on Power, Delay and Area Kalyana R Kantipudi ECE Department Auburn University Dec. 1, 2005 ELEC 6970-001 Class Presentation 1 Outline: Introduction Pros & Cons of PTL A PTL Design Need for an Improved Design A Transmission gate Design A new improved PTL Design Conclusions Dec. 1, 2005 ELEC 6970-001 Class Presentation 2 Introduction: The power equation: Ptotal = CLVDD2 + TscVDDIpeak + VDDIleakage Pdyn = VDD2fclk.Σan.cn + VDD.ΣIsc n Pleakage = VDDIsubleakage = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt} Dec. 1, 2005 ELEC 6970-001 Class Presentation 3 What Can We Reduce? Activity in the circuit Switching capacitance 1. Reducing Width and Length Supply voltage reduction Short-circuit reduction Dec. 1, 2005 ELEC 6970-001 Class Presentation 4 What PTL Can Offer? One pass-transistor network is enough. Reduction in number of transistors. Decrease in width and length of transistors. Results in smaller ‘input’ and ‘driving’ loads. Dec. 1, 2005 ELEC 6970-001 Class Presentation 5 The Catch… Reduction in level of the signal (VDD-Vth-IR). 1. 2. Needs level restoration at gate outputs in order to avoid static currents. Adjust threshold voltages (Vthp > Vthn). Only one single path through each network must be active at a time. (To avoid shorts between the inputs) 1. A multiplexer kind of structure is to be implemented all the time. Dec. 1, 2005 ELEC 6970-001 Class Presentation 6 PTL Logic Formulation and Implementation: Dec. 1, 2005 ELEC 6970-001 Class Presentation 7 Dec. 1, 2005 ELEC 6970-001 Class Presentation 8 Why 250nm Instead Of 180nm Technology For 180 nm: Vthn=0.51V Vthp=-0.52V VDD VDD - VTp If a pass transistor is feeding an inverter: Vi(t) Vo(t) Volt Vin(inv) = VDD – Vthn – IRdrop = 1.8 – 0.51 – 0.2 = 1.09 V VTn Other solutions: But for the p-transistor in an inverter to switch-OFF, the Vin should be atleast (VDD – |Vthp| = 1.28 V) 1. Keep Vthn of the NMOS pass transistors as low as possible. 2. Keep Vthp of the inverter higher than Vthn. Dec. 1, 2005 ELEC 6970-001 Class Presentation 9 Trade-offs Needed Delay due to load Vs. Delay due to gate Widths of the pass transistors: 30-9-7-5-3-1 Dec. 1, 2005 ELEC 6970-001 Class Presentation 10 Trade-offs needed Delay due to load Vs. Delay due to gate Widths of the pass transistors: 30-9-7-5-3-7/3-7/7-1 Dec. 1, 2005 ELEC 6970-001 Class Presentation 11 Transmission Gate Maintains the voltage swing of the signal Strong ‘1’ and strong ‘0’. As there are two channels conducting, the device speed improves. It is found that the transmission gate has robust characteristics compared to a CMOS gate. Dec. 1, 2005 ELEC 6970-001 Class Presentation 12 The AND Gate: CMOS AND gate: Static Power: 31.1411 pW Dynamic Power: 1.8285 uW Critical Delay: 214 pico secs. TX gate based AND: Static Power: 43.177 pW Dynamic Power: 417.863 nW Critical Delay: 172 pico secs. Dec. 1, 2005 ELEC 6970-001 Class Presentation 13 How to get to those features: Parameters: Lpass_p/Lpass_n Wp/Lp,Wn/Ln Static Power Dynamic Power Delay in Pico secs. (1/1,9/2,5/2) 59.88pW 618.57nW 173 (1/1,1/1,1/1) 4.42uW 24.01uW 184 (1/1,3/1,2/1) 2.67nW 32.03uW 145 (1/1,3/2,2/2) 146.54pW 368.18nW 184 (1/1,6/2,3/3) 43.17pW 417.86nW 172 (4/2,6/2,3/3) 43.18pW 1.07uW 366 (2/2,6/2,3/3) 43.18pW 609.96nW 260 Dec. 1, 2005 ELEC 6970-001 Class Presentation 14 Regarding the Robustness of Tx Gate Gate Status Static Power Dynamic Power Delay in Pico secs. CMOS 31.14pW 1.83uW 214 Feeding an inverter 78.49pW 2.14uW 257.5 Tx gate 43.17pW 417.86nW 172 Feeding an inverter 80.31pW 960.32nW 238.2 Without any load Without any load The Tx gate based “multi_cell” implementation is in progress >> Dec. 1, 2005 ELEC 6970-001 Class Presentation 15 A New XOR Design is Invented[4] Dec. 1, 2005 ELEC 6970-001 Class Presentation 16 The New “multi_cell” Design[5] In this new design, the entire “Multi_cell” needs just 15 transistors. Most of the transistors will be in their minimum size. Questions: Will it work ??? Does it has the drive capability ? Dec. 1, 2005 ELEC 6970-001 Class Presentation 17 The Waveforms Dec. 1, 2005 ELEC 6970-001 Class Presentation 18 Circuit specifications: Circuit Type Static Power Dynamic Power Delay PTL 353.36pW 79.24uW 8.45ns CMOS 356.56pW 12.49uW 551ps New PTL 105.15pW 16.63uW 662ps Dec. 1, 2005 ELEC 6970-001 Class Presentation 19 Regarding The Area Specs. CMOS has 38 transistors while the PTL has 39 transistors (most of the transistors having minimum feature size). Considering the ( ΣLW ) the area of CMOS cell is (960□/233□ = 4.12) times the size of the PTL cell. Dec. 1, 2005 ELEC 6970-001 Class Presentation 20 Conclusions: The area overhead of CMOS is at least 4 times more than the PTL. The power consumption is less in case of PTL compared to CMOS. A good PTL design needs a lot of astute trade-offs. Dec. 1, 2005 ELEC 6970-001 Class Presentation 21 References: 1. 2. 3. 4. 5. 6. 7. 8. J. M. Rabaey, A. Chandrakasan, B Nikolic, Digital Integrated Circuits-A Design Perspective. Prentice Hall, 2004. R. Zimmermann and Wolfgang Fichtner, “Low-power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid-State Circuits, vol.32, pp. 1079-1090, Jul. 1997. Geun Rae Cho, Tom Chen. "On The Impact of Technology Scaling On Mixed PTL/Static Circuits," 2002 IEEE International Conference on Computer Design (ICCD'02),p. 322, 2002. Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng,“New Efficient Designs for XOR and XNOR Functions on the Transistor Level,” IEEE J. of Solid-state Circuits, Vol. 29, pp. 780-786, July 1994. H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power IO-transistor full adders using novel XOR-XNOR gates," IEEE Trans. on Circuits and Systems-I/: Analog and digital signal processing, vol. 49, no. 1, pp. 25-30, Jan 2002. H. Lee and G.E. Sobelman, “A new low-voltage adder circuit,” in Proc. 7th Great Lakes Symp. VLSI, Urbana, IL, 1997. A. Shams and M. Bayoumi, “A new full adder cell for low-power applications,” in Proc. of the 1998 Great Lakes Symposium ,1997. K. Taki, “A Survey for Pass-Transistor Logic Technologies”, Proc. Asia South-Pacific Design Automation Conference , pp. 223-226, February 1998. Dec. 1, 2005 ELEC 6970-001 Class Presentation 22