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CMOS Transistor and Circuits Instructed by Shmuel Wimer Eng. School, Bar-Ilan University Credits: David Harris Harvey Mudd College (Some materials copied/taken/adapted from Harris’ lecture notes) Jan 2015 CMOS Transistor 1 Outline MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics DC characteristics and transfer function Noise margin Latchup Pass transistors Tristate inverter Jan 2015 CMOS Transistor 2 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance – I = C (DV/Dt) → Dt = (C/I) DV – Capacitance and current determine speed Also explore what a “degraded level” really means Jan 2015 CMOS Transistor 3 MOS Capacitor Gate and body form MOS capacitor Operating modes – Accumulation Vg < 0 + - polysilicon gate silicon dioxide insulator p-type body (a) 0 < V g < Vt – Depletion + - depletion region (b) – Inversion V g > Vt + - inversion region depletion region (c) Jan 2015 CMOS Transistor 4 Terminal Voltages Vg Mode of operation depends on Vg, Vd, Vs + + – Vgs = Vg – Vs Vgs Vgd – Vgd = Vg – Vd Vs Vd – Vds = Vd – Vs = Vgs - Vgd + Vds Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation – Cutoff – Linear – Saturation Jan 2015 CMOS Transistor 5 nMOS Cutoff No channel Ids = 0 Vgs = 0 + - g + - s d n+ n+ Vgd p-type body b Jan 2015 CMOS Transistor 6 nMOS Linear Channel forms Vgs > Vt + - Current flows from d to s – e- from s to d g + - s d n+ n+ Vgd = Vgs Vds = 0 p-type body b Ids increases with Vds Vgs > Vt + - g s Similar to linear resistor + d n+ n+ Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt p-type body b Jan 2015 CMOS Transistor 7 nMOS Saturation Channel pinches off Vgs > Vt + - g Vgd < Vt d Ids s n+ Ids independent of Vds + - n+ Vds > Vgs-Vt p-type body b We say current saturates Similar to current source Jan 2015 CMOS Transistor 8 I-V Characteristics In Linear region, Ids depends on: – How much charge is in the channel – How fast is the charge moving Jan 2015 CMOS Transistor 9 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel Qchannel = CV C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt (Vgc – Vt is the amount of voltage attracting charge to channel beyond the voltage required for inversion) gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, eox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body Jan 2015 CMOS Transistor 10 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral E-field between source and drain v = mE m called mobility E = Vds/L Time for carrier to cross channel: – t=L/v Jan 2015 CMOS Transistor 11 nMOS Linear I-V Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Qchannel I ds t W mCox L V V Vds gs t 2 V Vgs Vt ds Vds 2 Jan 2015 V ds CMOS Transistor W = mCox L 12 nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current V I ds Vgs Vt dsat 2 Jan 2015 V 2 gs Vt V dsat 2 CMOS Transistor 13 nMOS I-V Summary Shockley 1st order transistor models 0 Vds I ds Vgs Vt 2 2 Vgs Vt 2 Jan 2015 Vgs Vt V V V ds ds dsat Vds Vdsat CMOS Transistor cutoff linear saturation 14 Example We will be using a 0.18 mm process for your project – tox = 40 Å – m = 180 cm2/V*s – Vt = 0.4 V Plot Ids vs. Vds – Vgs = 0, 0.3, 0.6, 0.9, 1.2, 1.5 and 1.8V. – Use W/L = 4/2 l 3.9 8.85 1014 W W mCox 350 8 L 100 10 L Jan 2015 CMOS Transistor W 2 155 m A / V L 15 Jan 2015 CMOS Transistor 16 pMOS I-V All doping and voltages are inverted for pMOS Mobility mp is determined by holes – Typically 2-3x lower than that of electrons mn Thus pMOS must be wider to provide same current – In this class, assume mn / mp = 2 Jan 2015 CMOS Transistor 17 Jan 2015 CMOS Transistor 18 DC Transfer Characteristics Objective: Find the variation of output voltage Vout for changes in input voltage Vin. Vtp – Threshold voltage of p-device Vtn – Threshold voltage of n-device Jan 2015 CMOS Transistor 19 Jan 2015 CMOS Transistor 20 Recall CMOS device CMOS inverter characteristics is derived by solving for Vinn=Vinp and Idsn=-Idsp Jan 2015 CMOS Transistor 21 CMOS inverter is divided into five regions of operation Jan 2015 CMOS Transistor 22 Jan 2015 CMOS Transistor 23 Jan 2015 CMOS Transistor 24 Jan 2015 CMOS Transistor 25 Jan 2015 CMOS Transistor 26 I-V Characteristics Make pMOS is wider than nMOS such that n = p Vgsn5 Vgsn4 Idsn Vgsn3 -Vdsp Vgsp1 Vgsp2 -VDD 0 VDD Vdsn Vgsp3 Vgsp4 Vgsn2 Vgsn1 -Idsp Vgsp5 Jan 2015 CMOS Transistor 27 Current vs. Vout, Vin Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout Jan 2015 CMOS Transistor VDD 28 Load Line Analysis For a given Vin: – Plot Idsn, Idsp vs. Vout – Vout must be where |currents| are equal in Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout Jan 2015 CMOS Transistor VDD Vin Idsp Vout Idsn VDD 29 Load Line Summary Idsn, |Idsp| Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout Jan 2015 CMOS Transistor VDD 30 DC Transfer Curve Transcribe points onto Vin vs. Vout plot Vin0 Vin5 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Vin2 Vin1 Vout Jan 2015 VDD A B Vout VDD CMOS Transistor C D 0 Vtn VDD/2 E VDD+Vtp VDD Vin 31 Operating Regions Revisit transistor operating regions Region nMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear VDD pMOS A B Vout Cutoff C D 0 Vtn VDD/2 E VDD+Vtp VDD Vin Jan 2015 CMOS Transistor 32 Beta Ratio If p / n 1, switching point will move from VDD/2 Called skewed gate Other gates: collapse into equivalent inverter VDD p 10 n Vout 2 1 0.5 p 0.1 n 0 Vin Jan 2015 CMOS Transistor VDD 33 DC Transfer function is symmetric for βn=βp Jan 2015 CMOS Transistor 34 Jan 2015 CMOS Transistor 35 Noise Margin It determines the allowable noise at the input gate (0/1) so the output (1/0) is not affected Noise margin is closely related to input-output transfer function It is derived by driving two inverters connected in series Jan 2015 CMOS Transistor 36 Jan 2015 CMOS Transistor 37 Jan 2015 CMOS Transistor 38 Impact of skewing transistor size on noise margin Increasing (decreasing) P / N ratio increases (decreases) the low noise margin and decreases (increases) the high noise margin Jan 2015 CMOS Transistor 39 Latchup in CMOS Circuits Jan 2015 CMOS Transistor 40 Parasitic bipolar transistors are formed by substrate and source / drain devices Latchup occurs by establishing a low-resistance paths connecting VDD to VSS Latchup may be induced by power supply glitches or incident radiation If sufficiently large substrate current flows, VBE of NPN device increases, and its collector current grows. This increases the current through RWELL. VBE of PNP device increases, further increasing substrate current. Jan 2015 CMOS Transistor 41 Jan 2015 CMOS Transistor 42 If bipolar transistors satisfy βPNP x βNPN > 1, latchup may occur. Operation voltage of CMOS circuits should be below Vlatchup. Remedies of latchup problem: 1. Reduce Rsubstrate by increasing P doping of substrate by process control. 2. Reducing RWELL and resistance of WELL contacts by process control. 3. Layout techniques: separation of P and N devices, guard rings, many WELL contacts (at design). Jan 2015 CMOS Transistor 43 Pass Transistors We have assumed source is grounded What if source > 0? VDD – e.g. pass transistor passing VDD VDD Vg = VDD – If Vs > VDD-Vt => Vgs < Vt – Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn – Called a degraded “1” – Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than Vtp Jan 2015 CMOS Transistor 44 Pass Transistor CKTs As the source can rise to within a threshold voltage of the gate, the output of several transistors in series is no more degraded than that of a single transistor. Jan 2015 CMOS Transistor 45 Transmission Gates Single pass transistors produce degraded outputs Complementary Transmission gates pass both 0 and 1 well Input g a b gb a b gb Jan 2015 g = 0, gb = 1 a b g = 1, gb = 0 0 strong 0 g = 1, gb = 0 a b g = 1, gb = 0 strong 1 1 g g a g b gb Output a b gb CMOS Transistor 46 Transmission gate ON resistance as input voltage sweeps from 0 to 1(VSS to VDD), assuming that output follows closely. Jan 2015 CMOS Transistor 47 Tristates Tristate buffer produces Z when not enabled EN A Y 0 0 Z 0 1 Z 1 0 0 1 1 1 EN Y A EN Y A EN Jan 2015 CMOS Transistor 48 Nonrestoring Tristate Transmission gate acts as tristate buffer – Only two transistors – But nonrestoring • Noise on A is passed on to Y EN A Y EN Jan 2015 CMOS Transistor 49 Tristate Inverter Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A A A EN Y Y Y EN = 0 Y = 'Z' EN = 1 Y=A EN Jan 2015 CMOS Transistor 50 Multiplexers 2:1 multiplexer chooses between two inputs S S D1 D0 Y 0 X 0 0 0 X 1 1 1 0 X 0 1 1 X 1 Jan 2015 CMOS Transistor D0 0 Y D1 1 51 Gate-Level Mux Design Y SD1 SD0 (too many transistors) How many transistors are needed? 20 D1 S D0 D1 S D0 Jan 2015 Y 4 2 4 2 4 2 Y 2 CMOS Transistor 52 Transmission Gate Mux Nonrestoring mux uses two transmission gates – Only 4 transistors S D0 Y S D1 S Jan 2015 CMOS Transistor 53 Inverting Mux Inverting multiplexer – Use compound AOI22 – Or pair of tristate inverters – Essentially the same thing Noninverting multiplexer adds an inverter D0 S S D1 D0 D1 S S Y S S S Y S D0 Y S D1 Jan 2015 CMOS Transistor 0 1 54 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects – Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0 – Or four tristates D0 S0 D0 0 D1 1 S1 D1 0 Y Y D2 0 D3 1 1 D2 D3 Jan 2015 CMOS Transistor 55 Sizing for Performance Cint NMOS and PMOS diffusion + diffusion-gate overlap. Cext Fan-out (input gates) + interconnects. Req Equivalent gate resistance. CL Cint Cext Capacitive load of an inverter. Cint SCiref Req Rref S S sizing factor. Cext Propagation delay: tp 0.69 Req Cint Cext tp0 1 SC int tp0 0.69 Req Cint Inverter delay loaded only by intrinsic. Jan 2015 CMOS Transistor 56 Cint Cg Intrinsic cap to gate cap ratio ≈1. f Cext Cg Effective fan-out. Cext tp tp0 1 Cg The delay of an inverter is only a function of the ratio between its external load cap to its input cap f t 1 p0 In Out Cg1 tp Jan 2015 1 N t j 1 p j 2 N t j 1 p0 Cg 1 j 1 Cg j CMOS Transistor N CL , Cg N 1 CL 57 tp Cg j 0, 1 j N 1 imply Cg j 1 Cg j Cg j Cg j 1 f , 2 j N 1 It implies that same sizing factor f is used for all stages. The optimal size of an inverter is the geometric mean of its neighbor drives Given Cg1 and CL , and F CL Cg1 the optimal sizing factor is The minimum delay through the chain is Jan 2015 CMOS Transistor Cg j Cg j 1 Cg j 1 f NF NF tp Ntp0 1 58 What should be the optimal N ? The derivative by N of tp yields N F N F ln F 0 N or equivalently f e1 f having a closed form solution f e only for γ=0, a case where the intrinsic self load is ignored and only the fan-out is considered. Jan 2015 CMOS Transistor 59