Download Tutorial - BIT Mesra

SEMESTER-IV
EC4105
DISCRETE & INTEGRATED ANALOG CIRCUITS
TUTORIAL SHEET
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Module 1:
RC Filters: RC loss pass and high pass filters and their response to sinusoidal, step, pulse, square wave
and ramp inputs.
Refer to figure 1. Explain why it is called a high pass RC circuit. Show that its transfer function is
given as
Vo (s)
-------Vi (s)
RCS
= A(s) = ----------- and
1+RCS
1
| A(s) | = ---------------------------- where fo = 1 / 2RC
[1+(f )o/ f)2] ½
C
Vs
R
V0
Fig. 1
And  = arctan (fo / f).
Where  is the angle by which output voltage leads the input voltage and fo is the cut-off
frequency. At this frequency fo, the magnitude of capacitive reactance is equal to the resistance and the
gain is 0.707.
A step voltage is applied to the circuit in figure 1, at time t = 0. (a) Determine the output v o (t); (b)
Show that the steady state is achieved (final value) if t > 5 for most of the engineering applications. (c)
Show that the voltage across capacitor cannot change instantaneously, provided that the current
remains finite.
A voltage pulse of amplitude V and duration tp is applied to the circuit in figure 1. Derive vo(f) for all t.
Sketch the output waveform for the cases RC >> tp and RC << tp.
A voltage square wave is applied to the circuit in figure 1. The average value of the square wave input
is Vd.c.
(a) Write the equations to determine the output voltage. Specialize these equations to the case if the
input were a symmetrical square wave.
(b) Sketch the output waveform vo(t) for the cases
RC>>T (ii) RC<<T and (iii) RCT where T=T1+T2, is the time period of the square wave.
A ramp (or sweep) voltage is applied at t = 0 to the circuit shown in figure 1. The slope of ramp is .
Determine the output voltage vo (t) and sketch it to an arbitrary scale for the cases RC>>T and RC<<T.
Also obtain the expression for the transmission error.
Under what conditions the circuit shown in figure 1 will act as a differentiator? What will be the output
if (i) square wave (ii) ramp signal and (iii) a sinusoidal signal is applied to its input terminals?
A symmetrical square wave of peak amplitude V and frequency f is applied to a high pass RC circuit.
Show that percentage tilt is given by:
1 – e-1/2fRC
P = -----------------x 200 percent and if tilt is small than
1 + e-1/2fRC
This equation reduces to
T
P = ------------ x 100 percent.
2RC
A 10 Hz symmetrical square wave whose peak to amplitude is 2V impressed upon a high pass circuit
whose lower 3-dB frequency is 5Hz. Calculate and sketch the waveform. In particular what is peak
output amplitude?
A 10 Hz square wave is fed to an amplifier. Calculate and plot the output under the following
conditions; the lower 3 dB frequency is (i) 0.3 Hz (ii) 3.0 Hz (c) 30 Hz.
(a) A square wave whose peak-to-peak value is 1V extends  0. 5V with respect to ground. The
duration of the positive section is 0.1 sec and of the negative section is 0.2 sec. If this waveform is
impressed upon an RC differentiating circuit whose time constant is 0.2 sec., what are the steady state
maximum and minimum values of the output waveform?
(b) Prove that the area under the positive section equals that under the negative section of the output
waveform. What is the physical significance of this result?
(c) Write the equations to determine the output voltage.
Refer to figure 2. Explain why is it called a low pass RC circuit, show that its transfer function is given
as
Vo (s)
RCS
R
-------- = A(s) = ----------- and
Vi (s)
1+RCS,
1
| A(s) | = ---------------------------- and  = tan-1 (f / f2)
[1+(f / f2)2] ½
1
Where f2 = ---------------- , the upper 3 dB frequency.
2RC
C
v0
Fig. 2
A step voltage is applied to the circuit in figure 2 at time t = 0. (a) Obtain the expression for v o(t), (b)
Obtain expression for rise time in terms of time constant RC and cut-off frequency f2.
A voltage pulse of amplitude V and duration tp is applied to the circuit in figure 2. Derive vo (t) for all t.
Sketch the waveform for the cases (i) RC >>T and (ii) RC<<T. State the rule of thumb for preserving
the shape of the pulse.
A voltage square wave is applied to the circuit in figure 2, whose average values V d.c. (a) Write the
equations to determine the output voltage vo(t). Simplify these equations for the symmetrical square
wave with zero average value and obtain the solution. (b) For voltage square wave input of part (a),
sketch the output waveform vo(t) for the following cases (i) RC << T (ii) RC  T and (iii) RC >> T
where T = T1+T2 is the time period of the square wave.
At t=0, a ramp voltage is applied to the circuit shown in figure 2, whose slope is . Determine the
output waveform vo(t) and sketch it for the cases RC<<T and RC>>T where T is the total ramp time of
interest. Also obtain the expression for the transmission error.
Under what conditions the circuit shown in figure 2 will act as an integrator? Discuss its limitations and
advantages over the differentiator of problem No. (6). If input to this circuit were (i) a ramp voltage (ii)
a square wave and (iii) a sinusoidal signal; then determine the output waveform v o(t).
An ideal 1 sec. pulse is fed to an amplifier. Calculate and plot the output waveform under the
following conditions; the upper 3dB frequency is (i) 10 MHz (ii) 1 MHz, (iii) 0.1 MHz.
A pulse is applied to a low pass RC circuit. Prove by direct integration that the area under the pulse is
the same as the area under the output waveform across the capacitor. Give physical interpretation of
this result.
A symmetrical to square wave whose peak-to-peak amplitude is 2V and whose average value is zero is
applied to an RC integrating circuit. The time constant equals the half of the square wave. Calculate
and sketch the waveform. In particular, find the peak-to-peak amplitude of the output amplitude.
A symmetrical square wave whose average value is zero and has peak-to-peak amplitude of 20V and a
period of 2  sec. This waveform is applied to a low pass circuit whose upper 3-dB frequency is 1/2
MHz. Calculate and sketch the steady state output waveform In particular, what is peak to peak output
amplitude.
Module – 2:
What are the physical origins of resistances and capacitances in the hybrid -  model of CS amplifier at
high frequencies? What is the order of magnitude of each capacitor and resistor in the hybrid - 
model?
Define fB and fT. What is the relation between them?
The following low frequency parameters are known for a given transistor at I c = 10 mA, VCE = 10 V
and at room temperature: hie = 500 ohm, hfe = 100 ohm, hoe = 10-5s, hre = 10-4, fT = 50 MHz and CC =
4pF. Compute the values of all the hybrid -  parameters.
A silicon pnp transistor has an fT = 400 MHz. What is the base thickness?
Given a germanium pnp transistor whose base width is 10 -4 cm at room temperature and for a dc
emitter current 2 mA, find
a) The emitter diffusion capacitance
b) fT
Given the following transistor measurement made at Ic = 5 mA, Vce = 10V and at room temperature: hfe
= 100, hie = 600 ohm, Ai = 10 at 10MHz, Cc= 3 pF. Calculate fB, fT, Ce, rb’,e and rbb’.
A transistor amplifier in CE configuration operating at high frequencies has the following parameters:
fT = 6MHz, hfe = 50, Rs = 500 ohm, gm = 0.04 A/v, rbb’ = 100 ohm and cc = 10 pF.
The load connected is 1 K ohm. Find voltage gain, current gain, 3dB frequency, voltage gainbandwidth product and current gain – bandwidth product.
(a) With hfe = 40, hie = 0.75 K ohm, Ce = 45 pF, Cc = 2 pF, find fB and fT for the transistor.
(b) What current gain is possible at a bandwidth of 100 MHz?
A single-stage CE amplifier is measured to have the following data:
fB = 5MHz, RL = 500 ohm, hfe = 100, fT = 400 MHz.
rbb’ = 100 ohm and gm = 100 mA/V.
Assuming Cc = 1 pF, Prove that Rs = 439 ohm gives the required bandwidth.
With the value of Rs = 439 ohms, show the midband voltage gain Vo/Vs is given by -32.5 using the
approximate analysis.
The CE current gain at high frequency is given by the expression.
 = 0 / [1+j (f/f)] Show that CB current gain can be written in the following form
 =0 / [1+j (f/f)] Where 0 = o/ (1+ 0)
f = f/(1+0)
(a) Consider hybrid -  circuit at low frequencies so that Ce and Cc can be neglected. Omit none of the
other elements in the circuit. If the lead resistance is RL = 1/gL, prove that
Vce/Vb’c = -gm + gb’c / (gb’c + gce + gL)
(b) Do the same by Miller’s theorem.
A transistor’s short circuit current gain is measured to be 25 at a frequency 2 MHz. If the fβ = 200 KHz
determine:
(a) Current gain – Bandwidth product
(b) hfe
The short circuit current gain at 10 MHz and 100 MHz.
Show that at low frequencies the Giacolectto’s model with r b’c and rce taken to be infinite reduces to the
CE h-parameters model.
A bipolar junction transistor has hie = 6 K ohm, hfe = 224 at Ic = 1 mA with fT = 86 MHz and
pF. Determine: (i) gm , (ii) rb’e, (iii) rbb’
Cb’e = 12
Deduce the relation between the hybrid -  model parameters and h-parameters.
Obtain the expression for the short circuit current gain of a CE configuration and hence draw the
frequency response curve.
Draw the high frequency equivalent circuit of a FET and explain the origin of the parameters.
For a CS amplifier using FET find (i) voltage gain, (ii) output impedance, (iii) Input impedance, (iv)
Input capacitance at high frequencies.
Deduce the expression for voltage gain of a CE amplifier considering the effect of emitter by pass
capacitor and hence draw the frequency response curve.
Derive frequency response for an amplifier with gain given
A = Ao / (1 j f/f1), for High frequency
A = Ao / (1+ j f2/f), for Low frequency
Module – 3:
Discuss different types of distortions generally encountered in an amplifier.
Why coupling of the network is required? Discuss different types of coupling.
The individual gain of the three stage amplifier is 50, 60, 70. Calculate the coverall gain in dB of this
three stage amplifier.
Three identical cascade stages have an overall 3dB frequency of 20 KHz and lower 3 dB frequency of
20 Hz. What are fL and fH.
Derive the expression for voltage gain of an RC coupled amplifier, using FET at low frequency.
Prove that at low frequency an RC coupled amplifier will act as high pass filter.
Show that at high frequency an RC coupled amplifier will act as low pass filter.
Explain briefly a) non-linear distortion b) frequency distortion c) phase shift distortion.
The mid frequency gain of RC coupled amplifier is 100. If the gain falls by 3 dB at the lower cut off
frequency calculate the gain at the cut off frequency in dB.
It is desired to have a low 3-dB frequency of not more than 10Hz for an RC coupled amplifier for
which Ry = 1K ohm. What minimum value of capacitance is required if
FETs with Rg = 1M ohm are used
BJTs with Ri = 1K ohm and 1/hoe = 40K ohm are used.
The mid frequency gain of RC coupled amplifier is 100. The value of lower and higher cut off
frequencies are 100 Hz and 100 KHz. Find the frequency at which the gain reduces to 90.
Design a single-tuned amplifier to operate at a centre frequency of 455 KHz with a bandwidth of 10
KHz. The transistor has the parameters gm = .04 S, hfe = 100, Cb’e = 1000 pF, and Cb’c = 10 pF. The bias
network and the input resistance are adjusted so that ri = 5 KΩ and RL= 500 Ω
Find the GBW of the transistor amplifier shown in the Fig. 3. All bias components have been removed
for simplicity. The components values are ri = 1 KΩ , Rc = rb’e = 100 Ω , Cb’e = 100 pf, Cb’c = 1 pF, and
hfe = 100.
Q1
Ii
Rc
ri
Fig 3
Find the GBW product of a JFET amplifier having the parameters g m = 3 mS, Cgs = 6pF, Cgd = 2 pF, rds
= 70 KΩ and Rd = 10 K Ω.
Find the gain – Bandwidth product of the single tuned amplifier.
Show that the centre frequency of the tuned circuit of Fig. 4 is
1
1
LC
and the 3 dB bandwidth is
2RC
R
C
L
Ii
Fig. 4
For the circuit shown in Fig. 5, rb’e = 1K Ω , Cb’e = 1000 pf, Cb’c = 10 pF, and gm= .05 S. Determine the
gain bandwidth product .
VCC
1K
100K
Q
20uF
Ii
10K
1kO hm
Fig. 5
A one stage FET amplifier uses a low frequency JFET having the parameters g m = 3 mS, rds = 50 KΩ ,
Rd = 10 KΩ , Rg = 500 KΩ , Cgs = 30 pF, and Cgd = 5 pF. Find the GBW product. Assume RL= ri = 10
kΩ.
Draw the circuit diagram of a cascade amplifier and explain its operation.
A cascade amplifier is shown in the Fig. 6. Find the value of R c which will set the dc component of the
output voltage to 0 V. Assume hfe = 50 for all transistors.
VCC 12V
IO1
IO2
8kOhm
Q2
15kOhm
Q1
Rc
23kOhm
Q3
V2
VL
1V
3kOhm
37kOhm
-6V
Fig. 6
Module – 4:
Discuss the effect of feedback on an amplifier
Describe various types of feedback with their basic configuration.
An amplifier has a mid-band gain A = 500 lower cut off frequency of 50Hz and upper cut off frequency
of 40 KHz. If feedback with  = 0.1 is introduced, find the gain with feedback and the new values of
cut off frequencies.
Determine the voltage gain, input impedance and output impedance with the feedback for the voltage
series feedback A= 100, ri = 10 K , R0 = 20 K for the feedback of
a) = -0.1 b)  = -0.5
Comment on the trade off between the gain and impedance of the amplifier.
An amplifier has 5% non-linear distortion generated in its final stage. The amplifier gain without
feedback is 1500. If the distortion is to be reduced to 2.5% with distortion calculated A f.
If the amplifier with the gain = -1000 and feedback of  = -0.1 has a gain change of 20% due to
temperature, calculate the change in the gain of feedback amplifier.
The overall gain of a two stage amplifier shown in fig. 7 is 200 with negative feedback of 20% applied
only to the 2nd stage has a gain of 3000 and 10% distortion without feedback find (a) the distortion of
the 2nd stage with feedback and (b) the gain of the 1st stage.
VS
A1
D1 =0
A2 = 300
D2 =0.1
 = 0.2
V0
Fig 7
An amplifier must maintain its gain at 59 within  1%. If the gain without feedback varies by 10% due
to active parameters find the value of feedback necessary to keep gain within  1% and the value of the
gain without feedback.
An amplifier has a midband gain of 105. A voltage feedback of 10 dB is introduced. Find the value of
Af and feedback gain .
An amplifier consists of three identical stage connected in cascade. The O/P voltage is sampled and
connected to the input in series opposing. If it is specified that the relative change dAf/Af in the closed
loop voltage gain Af must not exceed  f . Show that the minimum value of open loop gain A of the
amplifier is given by
A = 3 Af | 1 | / |  f |
where
1 = dA1/A1 is the relative change in the voltage gain of each stage of the amp.
For the following feedback amplifier Fig. 8, calculate Rif = Vs/Ii, Aif = - I/Ii, A’vf = Vo/Vi, Avf = Vo/Vs
and R’of.
VCC
22K
220K
4.7K
V0
Q2
220K
100 
Q1
Vs
22k
1K
22 K
100 
Fig 8
Assume transistors are identical and hie = 1.1 K, hfe = 50, hre = hoe = 0. Neglect the reactance of the
capacitors.
In the two stage feedback amplifier shown below (Fig. 9), the transistor are identical and have the
following parameters, hfe = 50, hie = 2K, hre = hoe = 0. Identical the type of feedback and calculate (a)
Aif (b) Rif and (c) Avf.
VCC
10K
15K
Q2
Q1
Is
10K
Rs=1K
V0
Ref
Fig 9
Identifies the type of feedback for the following feedback amplifier (Fig. 10) and calculate (a) F mf, (b)
Avf, (c) Rif and (d) Rof.
VCC
10K
100K
V0
Re
Assume,
Re =0
hfe = 100, hie = 1 K
hre = hoe = 0
Is
Fig 10
An amplifier with an open loop gain Av = 1000  100 is available. It is necessary to have an amplifier
when voltage gain varies by no more than  0.1%
Find the revers transmission factors of the network used.
Find the gain with feedback.
An amplifier without feedback gives a fundamental O/P of 36V and with percentage 2 nd harmonic
distortion when the input is 0.028V.
If 1.2% of the O/P is feedback into the I/P in a negative voltage series feedback, what is the input
voltage?
If the fundament is maintained at 36V but the 2nd harmonic distortion is reduced to 1%, what is the I/P
voltage?
An amplifier has an open loop voltage gain of 1000 delivers 10W of O/P power at 10% 2 nd harmonic
distortion when the I/P signal is 10mV. If 40 dB negative voltage series is applied and the O/P power is
to remain at 10W, determine (a) the required I/P signal (b) the percentage 2 nd harmonic distortion.
The h-parameter model of a transistor can be considered represent a feedback amplifier due to the
presence of hre source. Using feedback formula find (a) Rif and (b) Yof = 1/Rof taking hre, hoe and source
resistance (Rs) into account.
Justify that CE transistor Amplifier is internally voltage series positive feedback with feedback factor
nearly ( hre)
Prove that the negative feedback in an amplifier improves its sensitivity and distortion. State the
assumption made.
An amplifier with an open loop voltage gain of 1000 has an output impedance of 10 KΩ. It is desired to
modify its output impedance to 1 KΩ. What type of feedback is to be applied? Calculate the feedback
factor. Also find the percentage change in overall gain for a 10 % change in the open loop gain of the
amplifier and the voltage gain with the feed back.
Module – 5:
State and explain the condition of oscillation.
Discuss stability criteria for an oscillator.
Explain the working of (a) Hartley oscillator (b) Colpitis oscillator (c) Wien Bridge oscillator (d) RC
phase shift oscillator.
A phase shift oscillator with CE transistor has RL value of 2K ohms and R value of 1K ohm. What is
the minimum value necessary for hfe to obtain sustained oscillation?
In a phase shift oscillator shown in the following figure 11 has hfe = 60. A three stage ladder is used
with R = RK ohm. What is the value of RL necessary to achieve sustained oscillation? What value of
capacitance has to be used in each branch in order to obtain sustained oscillations at 5 KHz?
VCC
R2
R3
R1
C
C
C
Q1
R2
For the Fig. 12, prove that
Re
When, R3 = R-Ri
Ri= hie
Assume that,
hoe. Re < 0.1
Neglact the effect of
R1, R2
Ce
Fig 11
 = Vf’ / Vo = - 1 / [ 1- 5 2 – j (6- 3)]
where  = 1/RC
Assuming that the network does not load the amplifier. Prove that the phase shift of is 180 o for 2 = 6
and at this frequency  = 1/29.
Take into account the loading of the RC network in the phase-shift oscillator of Fig. 12. If R0 is the
output impedance of the amplifier ( assume that Cs is arbitrarily large), prove that frequency of
oscillation f and the minimum gain A are given by
1
f 
2RC
R
R 
and A  29  23 0  4 0 
R
 R
R
6  4 0 
R


1
2
VDD
C
Rd
R
V0
Rs
C
C
R
R
Vf
Fig 12
A two stage FET oscillator uses the phase shifting network as shown in the Fig 13, Prove that
V’f / Vi = 1 / [3+ j(RC – 1/RC)]
R
C
C
Vo
R
V’f
Fig 13
In continuation with the above problem prove that the frequency of oscillation is f o = 1/2 RC and that
the gain must exceed 3.
Find V’f / V0 for the network shown in the fig. 14.
Sketch the circuit of a phase shift FET oscillator using this network.
Find the expression for the frequency of operation (oscillation) assuming that the network does not
load down the amplifier.
Find the minimum gain required for oscillation.
C
R
c
O
C2
Vo
o
R2
V'f
u
Fig 14
Consider the two sections RC network shown Fig. 15, Find V’f/Vi function and verify that it is not
possible to obtain 180o phase shift with a finite attenuation.
Vo
C
C
R
R
Fig15
Vf
For the feedback network shown in Fig. 16, find (a) the transfer function, (b) the input impedance, (c)
If this network is used in a phase shift oscillator find the frequency of oscillation and minimum voltage
gain of the amplifier. Assume that the network does not load down the amplifier.
R
R
C
Vo
R
C
C
V’f
Fig 16
Design the wien Bridge oscillator so that the frequency of oscillation is fo = 1 KHz.
For the transistor phase shift oscillator of Fig.17 Show that frequency of oscillation is given by
1
2RC
f 
1
6  4k
where
k
Rc
R
VCC
Rc
R1
C
R3
C
C
Q1
R
R2
C'
R
Re
Fig. 17
Show that a transistor with a small signal common emitter short circuit gain less than 44.5 can not be
used in the phase shift oscillator of Fig. 17
Describe briefly a) Series - operated crystal oscillator
b) Shunt - excited crystal oscillator
Verify
j  2   s2
jX  
C '  2   p2
for the reactance of the crystal, where the symbols have their
usual meanings.
a)
Prove that the ratio of the parallel to series resonant frequencies is given approximately by
1
1 C
2 C'
b)
If C= 0.04 pF and C’ = 2.0 pF, by what percent is the parallel resonant frequency greater than the
series- resonant frequency?
A crystal has the following parameters: L = 0.33 H, C= 0.065 pF, C’ = 1.0 pF, and r = 5.5 K.
Find the series resonant frequency.
By what percent does the parallel resonant frequency exceed the series resonant frequency?
Find the Q of the crystal.
A FET phase shift oscillator having gm = 6000 S, rd = 36 KΩ and feedback resistor R=12 KΩ is to
operate at 2.5 KHz. Select C for specified oscillation operation.
Module – 6:
Define the term sweep speed error, transmission error and displacement error.
prove that ed = es/8 = et/4
An exponential sweep results when a capacitor C is charged from a supply voltage V through a resistor
R. If the peak sweep voltage is Vs, prove that the slope error is given exactly by e s= Vs/V.
Give the constructional details of UJT with electrical equivalent circuit.
Explain how UJT acts as switch for relaxation oscillator.
(a) Explain the idealized input characteristic of the U.J.T.
Is it a voltage controllable or current controllable negative resistance characteristic? Explain how it can
be used for (i) bistable (ii) monostable (iii) astable operation.
Draw the circuit for saw tooth generator using a U.J.T. With the help of waveforms explain its
operation. Derive the expression for sweep time Ts when V YY = VBB.
In the UJT sweep circuit, VYY = 50 V, VBB = 20 V, R = 5 K, Rb1 = Rb2 = 0 and C = 0.01 μF. Calculate
a) Amplitude of the sweep signal vc
b) The slope and displacement error
c) The time of the sweep d) estimated recovery time.
Design a relaxation oscillator using U.J.T. with V YY = 14V, VBB = 10 Volts for U.J.T. Assume  =
0.6 and VV = 2V, VP = 0.6V. This oscillator is to have sweep time T S = 1 msec. That is if
T r can be
neglected, then its frequency would be 1 KHz.
For relaxation oscillator of prob. No. 89, derive the expression for the retrace time T r and calculate its
value for that circuit.
A UJT is used as a switch across a sweep capacitor C which charges through R. A single supply
voltage VBB is used in the circuit. Prove that the sweep duration is given exactly by
Ts  RC ln
VBB  VV
VBB  VP
For the Q95. Prove that, if VBB >> Vv, Then
 1 
Ts  RC ln 

1   
Describe what you understand by oscilloscope time base. How is it realized?
How the linearity correction is done by the voltage time base generator?
Name few important methods of generating the time base waveform. Explain the principle of Bootstrap
time base generator. Using the appropriate equivalent circuits derive the expression for the slope error
and sweep speed. Finally deduce the requirements, which will provide an improvement in linearity.
Describe the principle of the Miller sweep generator. Using the appropriate equivalent circuit derive the
expressions for slope error es and sweep speed.
How the linearity correction is done in the current time base generator?
In the circuit of Fig. 13, Vcc = 20 V , L = 200 mH, the yoke resistance RL = 20 Ω, Rcs = 5 Ω and Rd =
200 Ω. For a 500 μ sec sweep draw the wave form of i L and vce, indicating voltage levels and time
constants. Calculate slope error of the sweep.
Draw a transistor current time base generator and explain it.
Draw and explain the transistor television sweep circuit.
Module – 7:
(a) State what is digital to analogue conversion. With the help of schematic diagram describe the
operation of a N bit D/A converter with binary weighted resistors.
(b) Explain the operation of a N-bit ladder type D/A converter with the help of schematic diagram.
Given an 8-bit binary weighted resistors D/A converter with a reference voltage V R = 12 V
What is the minimum value of R so that I max shall not exceed 10 mA?
What is the smallest quantized value of I?
Consider a 6-bit binary weighted resistors D/A converter with a resistance in LSB position of 320 K.
The reference voltage is 10 V. The binary weighted resistors are connected to summing point of an
OPAMP with A = ∞, Rf = 5 K Ω. What is the output voltage for a binary input 111010?
What are the output voltages caused by each bit in a 4-bit ladder if the output levels are 0 V and 10 V?
Find the output voltage corresponding to 1101 input.
Find the output voltage of the 8 bit binary ladder with the following input:
(a)
11010110
(b) 11101100
(c)
11000010
What is the difference between accuracy and resolution?
Define resolution, maximum conversion time and average conversion time.
Define the linearity and accuracy for D/A converter.
Explain following
i)
Monotonicity
ii)
Settling time
iii)
Stability
What are the limitations of binary weighted D/A Converter?
A D/A converter accept 12 input bits and provide an output which is 10 V maximum. Suppose that as a
result of drift of component values etc. the output may be in error by an amount ΔV. How large can ΔV
be before the least significant bit would no longer be significant?
What is the resolution of an 8 bit D/A converter which uses a ladder network? If the full scale output
voltage of this converter is+5 V, calculate the resolution in V.
A D/A converter has a full scale analog output of 10V and accepts 6 binary bits as inputs. Find the
voltage corresponding to each analog step.
With the help of block-diagram explain the operation of an A/D converter using a counter.
Describe the operation of a simultaneous A/D converter.
Describe the operation of successive approximation A/D converter.
Describe, with the help of diagrams, the operation of a continuous A/D converter.
An 8-bit counter type A/D converter is driven by a 500 KHz clock. Find (i) maximum conversion time
(ii) the average conversion time (iii) the maximum conversion rate.
What clock frequency must be used with a 10 bit counter type A/D converter if it must be capable of
making at least 7000 conversions per second?
In the dual slope converter the clock rate is 100 KHz and converter has the resolution of 10 bits. What
is the maximum rate at which samples can be converted?
If the parallel comparator A/D converter is to convert analog voltages varying from –v0 to +v0 into
twos- complement arithmetic, determine the reference voltages at each comparator input. Assume a 3bit output.
The 3 bit successive-approximation converter is to be used for analog input samples in the range 0 to
10V. What should the offset be to assure that the maximum quantization error will be the same in each
range?