Download Final Exam 2015/2016 i File - e

2
SKEL 4283
Q.1 (a)
Consider a differential circuit shown in Figure Q.1(a). Perform DC analysis to
find the following voltages. Ignore body effect and channel length modulation.
(i)
VD1.
(5 marks)
(ii)
VS1.
(5 marks)
(iii) VD2.
(5 marks)
(b) Consider an amplifier circuit in Figure Q.1(b).
(i)
Draw a small signal equivalent circuit for the amplifier. Simplify your
circuit.
(5 marks)
(ii)
Write the equations to find the voltage gain vout/vin. Do not solve the
equations.
(5 marks)
VDD = 2.5 V
M3
M4
W = 40 μm
L = 2 μm
VIN1
1.5 V
W = 40 μm
L = 2 μm
M1
M2
W = 20 μm
L = 2 μm
W = 20 μm
L = 2 μm
IBIAS
50 μA
Figure Q.1(a)
VIN2
1.5 V
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SKEL 4283
VDD
M2
vOUT
RD
vIN
M1
Figure Q.1(b)
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Q.2 Consider a differential amplifier with diode-connected load as shown in Figure Q.2. We
want to design the amplifier such that the magnitude of the differential voltage gain
|AVD,diff| = |(vo1 – vo2)/(vi1 – vi2)| = 5. For all transistors, channel length L = 2 μm. In all
calculations, ignore body effect and channel length modulation.
(a) Determine W5, the channel width for M5, to set ISS = 100 μA. Assume overdrive
voltage for M5 is 0.25 V.
(5 marks)
(b) Determine W3 and W4 so that the DC voltage at the output is at 1.5 V.
(5 marks)
(c) Determine the required value for gm1.
(5 marks)
(d) Calculate W1.
(5 marks)
(e) Determine the required VGS for M1 and M2.
(5 marks)
VDD = 2.5 V
M3 M4
vO2
vO1
vI1
M1 M2
ISS
VBIAS
M5
Figure Q.2
vI2
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SKEL 4283
Q.3
(a)
A CMOS amplifier is shown in Figure Q.3(a).
(i)
Calculate the current ID for both transistors. Assume λ = 0.
(2 marks)
(ii)
Calculate the output resistance of the amplifier, Rout.
(3 marks)
(iii)
Calculate the DC gain of the amplifier, AV = vout/vin.
(5 marks)
(iv)
Determine the -3 dB frequency, in Hertz, of the amplifier if Cgd1 = Cgd2 = 5 fF,
Cbd1 = Cbd2 = 50 fF, and CL = 200 fF.
(10 marks)
(b)
Another amplifier circuit is shown in Figure Q.3(b). Parasitic capacitances for the circuit
are Cgdn = Cgdp = 5 fF, Cbdn = Cbdp = 20 fF, while the load capacitance CL = 500 fF.
Calculate the total capacitance to ground at the output node, Cout.
(5 marks)
VDD = 2.5 V
W/L = 10 μm/2 μm
M1
vIN
vOUT
ID
M2
W/L = 2 μm/2 μm
VB = 1.75 V
Figure Q.3(a)
VDD = 2.5 V
M3
M2
W/L = 10 μm/2 μm
for all transistors
vOUT
100 μA
vIN
M1
Figure Q.3(b)
CL
500 fF
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SKEL 4283
Q.4
A standard uncompensated two-stage operational amplifier is shown in Figure Q.4. Design
the circuit to obtain open-loop gain of 1,000 with equal overdrive voltage for M3 – M7. For
all transistors, channel length L = 2 μm. You may ignore body effect in your calculations. Use
the parameter λ only for calculating rds or gds. Do not use λ in any other calculation including
your bias currents.
(a)
Set overdrive voltage for M3 – M7 to 0.3 V. Determine the maximum and minimum
output voltage where all transistors still operate in saturation region.
(3 marks)
(b)
Determine bias voltage VB.
(2 marks)
(c)
Choosing ID5 = ID7 = 25 μA, determine W3, W4, W5, W6, and W7.
(5 marks)
(d)
Determine W1 and W2 to obtain open-loop gain of 1,000.
(10 marks)
(e)
Find the input common-mode range (ICMR) of the op-amp.
(5 marks)
VDD
M3
M4
M6
vOUT
M1
M2
vIN2
vIN1
M5
vB
Figure Q.4
M7
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SKEL 4283
Q.5
(a)
Figure Q.5(a) shows a circuit for high-swing cascode current sink. The circuit must sink
a current of 300 µA. The circuit should operate normally for any output voltage > 0.5
V, i.e. VMIN = 0.5 V. All transistors use L = 2 µm.
(i)
Determine the value for resistor R1 and R2.
(5 marks)
(ii)
Determine the W for all transistors. Ignore channel length modulation.
(5 marks)
(b)
Another current sink circuit, known as regulated cascode current sink, is shown in
Figure Q.5(b). Design the circuit so that it can sink 300 µA at the output. You must
design such that overdrive voltage for all transistors is 0.25 V. You must also make sure
VDS2 = VDS1. Choose L = 2 µm. Determine W for all transistors. Ignore channel
modulation in all your calculations.
(15 marks)
VDD
R1
R2
IOUT
M4
M5
M2
+
VOUT
M3
M1
–
Figure Q.5(a)
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SKEL 4283
VDD
IREF1
IREF2
IREF1
50 µA
IREF2
10 µA
IOUT = 300 µA
M4
M1
M2
Figure Q.5(b)
M3
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SKEL 4283
FORMULAE AND DETERMINANTS
1.
2.
VDD
Drain current
2.5 V
W
1


V DS V GS  V T  V DS 
L
2


1 W
2
I D  K ' V GS V T  1   V DS 
2
L
I D  K'
VT = VT0
3.
Transistor parameters
NMOS
PMOS
4.
VT0 (V) K' (µA/V2)
0.43
115
-0.4
-30
λ (V-1)
0.06
-0.1
Small signal parameters
gm 
r ds 
2I D
  V GS  V T   2 I D
V GS  V T
1
 ID
linear
saturation