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ECE 477
Digital Systems Senior Design Project
Fall 2005
Homework 6: Printed Circuit Board Layout Design
Due: Thursday, October 6, at Classtime
Team Code Name: ___Recursively Awesome__________ Group No. __7____
Team Member Completing This Homework: ______Colleen Shea_____________
NOTE: This is the third in a series of four “design component” homework assignments, each
of which is to be completed by one team member. The completed homework will count for
10% of the team member’s individual grade.
I. Introduction
The project presented is a highly precise pan and tilt platform for a camera or associated
peripheral. The focus of this project is the continuous and smooth motion of a platform with two
degree accuracy. A sample application for this product is a video conference room. The camera
platform could be used to change the video feed from one speaker to the next. Each participant in
the conference would have an assigned seat, or degree reference. The participant could press a
button on his or her cell phone (or keypad) and the camera would rotate to face the speaker. The
PCB design layout was constructed with many considerations for both decreasing EMI
interference, and creating a friendly user interface.
II. PCB considerations
There were many considerations which went into the PCB layout design. The primary goal of
successful PCB layout is reducing EMI as much as possible. Electromechanical interference
(EMI) is a common and often overlooked problem in circuitry. Noise coupled on wires can
wreak havoc on a system, especially in the age of faster and faster switching circuitry. Signal
error on a digital signal could case an input pin to read a ‘high’ value instead of a ‘low’ value,
which potentially could prevent the circuit from working correctly. EMI associated problems are
practically impossible to debug, so it is crucial that sufficient care is taken to reduce and
hopefully eliminate such issues.
Component placement is the first step in eliminating EMI. Recall that analog noise is
caused by changing current loads, and digital noise is caused by switching devices. Hence, the
ECE 477
Digital Systems Senior Design Project
Fall 2005
analog and digital circuitry should be physically separated on the board to minimize coupling.
On this particular board, analog components are on the left hand side of the board, and digital
components are on the right hand side. The only difficulty faced with component placement was
the operational amplifier. The op-amp is being powered by +12 Volts (analog), but is directly
connected to the text to speech chip, which is being powered by +5 Volts (digital). A
compromise was made and the chip was placed towards the bottom of the board in the center.
Ground loops are another common problem which contributes to unwanted noise factors.
All grounds have finite impedance. This impedance causes voltage drops due to return currents.
These voltage drops cause unwanted noise. To decrease the severity of this problem, the analog
and digital grounds should be kept separate and tied together at a single point. This was done as
much as possible in layout, although features of the software made specific wire placement
difficult. The problem arose when a specified connection was desired between two pins, but
layout had connected them differently (such as through a third pin).
Trace length, width and via number are also important consideration factors in
layout design. Everything was done to reduce both the trace length and the total number of vias.
The board has 59 vias total. Trace length is a variable factor; there are tradeoffs every time a
component is moved. In one position certain traces will be shorter; in another a different set will
be shorter. It is important to focus on the critical trace lengths, such as the length from the ICs to
the decoupling capacitors. Each IC in the circuit has a decoupling capacitor. The purpose of the
decoupling capacitors is to provide instantaneous current to the chips during switching. The
capacitors are placed as close as possible to the respective chips because wires inherently have
inductance. It is intuitively obvious that the longer the wire, the greater the inductance. Current
cannot switch instantaneous through an inductor. If the path from the capacitor to the IC is long,
no current can be sourced, defeating the purpose of the decoupling capacitor. The capacitors are
most frequently placed directly under the chip in this particular schematic. A similar reasoning
was used for the placement of diodes D2 – D9. These diodes are designed to protect from
inductive kickback.
Trace width is also important, in that the width of the power and ground traces need to be
relatively large compared to the other traces. This is due to the higher currents that will be
traveling through these traces. A PCB trace-width calculator was used to calculate a
conservative estimate of 40 mils for these traces. Also, traces must not make 90 degree or larger
ECE 477
Digital Systems Senior Design Project
Fall 2005
turns. Current can be thought of as water flow – 90 degree angles provide too much physical
resistance to the current path for effective performance.
Floating pins provided a challenge as well. After considerable debate it was decided that
two unused PLD inputs would be placed through a resistor to ground. The purpose of this design
is the input port pins are now available for use if need be without cutting the board. All other
unused inputs are tied directly to ground, per the PALCE data sheet.
Finally, the placement of headers and potentiometers was chosen for optimal
accessibility. Wherever possible the headers were placed on the side of the board, and the
potentiometers were all placed on the top of the board. Additional headers were added to the
schematic for PLD inputs and outputs.
It is prudent to note that the board does have the team name in silk screen in the lower
right hand corner. It is not visible because it is white.
III. List of References
[1] “MAX5035 DC-DC Converter Datasheet”, [Online Document], 2005 September,
Available HTTP: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3991
[2] “PALCE16V8 Family Datasheet”, [Online Document], 2005 September,
Available HTTP: http://shay.ecn.purdue.edu/~dsml/ece270/Refs/Pld/palce16v8.pdf
[3] “9S12C Module Connections”, [Online Document], 2005 September,
Available HTTP:
http://shay.ecn.purdue.edu/~dsml/ece362/MiniPrj/module_connections.pdf
[4] “System Design and Layout Techniques for Noise Reduction in MCU-Based Systems”.
Motorola Semiconductor Application note AN1259/D [Online Document
Available HTTP: http://shay.ecn.purdue.edu/~dsml/ece477/Homework/Fall2005/AN1259.pdf
[5] “System Design and Layout Techniques for Noise Reduction in MCU-Based Systems”.
Motorola Semiconductor Application note AN1259/D [Online Document
Available HTTP: http://shay.ecn.purdue.edu/~dsml/ece477/Homework/Fall2005/AN1259.pdf
[6] “ANSI PCB Trace Width calculator”, [Online Document], 2005
Available HTTP: http://www.desmith.com/NMdS/Electronics/TraceWidth.html
[7] “PCB Trace Width calculator”, [Online Document], 2005
Available HTTP:http://www.mgchemicals.com/products/popup/calc-pcbtrace.html
ECE 477
Digital Systems Senior Design Project
Fall 2005