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Basics of Embedded Systems IAX0230 Click to edit Master title style Low-Power Design Prof. Dr. Kalle Tammemäe Prof. Dr.-Ing. Thomas Hollstein Dr. Uljana Reinsalu Outline © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Dynamic and Static Power consumption Power Scaling and Optimization techniques VDD and delay interdependency Power Budgeting in Battery-driven Applications Power supply choice and lifetime Coding Techniques for Low Power Power Measurements and Analysis LP modes of Cortex-M4 2 Motivation – why worry about power? © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Wearables IoT, CPS, “smart dust”, etc. More computation Video decoding Augmented reality processing Speech recognition and synthesis Handwriting recognition Complex communication protocols, etc. Autonomous units Sea and ocean technology Space technology, etc. Battery capacity and weight limits (10% improvement per year) Energy harvesting limits 3 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Energy Quantity 10-log J Energy UV photon -18 Neural transition -13 Varies with size CMOS transition -12 Gate with 100fF load α-particle -12 From space or IC package impurity 8-bit assignment -10 PCB transition -10 ARM instruction -8 8-bit access 16Mb SRAM -8 DEC Alpha instruction -7 Correcting DCC word -6 NiCd penlight battery 3 Can of beer 6 600 kJ Lead-acid car battery 6 5kg x 40Wh/kg Kg of coal 7 Daily human consumption 7 2500 kilocalories Man-made nuclear explosion 14 Trinity (July 16, 1944) 1906 San Francisco earthquake 17 8.3 on the Richter scale Nova 37 Big Bang 73 10 pF load [Berkel K. van, Rem M.,1994] 4 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Power density of microporocessor [F. Pollack, keynote speech, “New microarchitecture challenges in the coming generations of CMOS process technologies, “, MICRO-32, Haifa, Israel, 1999] 5 Microcontrollers: Power Management © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Dynamic power: Every time a logic gate goes through a complete switching cycle, the transistors within the gate dissipate an energy equal to ETD. Logic gates normally switch states at some relatively high frequency (switching events/second), and the dynamic power PD dissipated by the logic gate is then 2 PD CVDD f In effect, an average current equal to (CVDDf) is supplied from the source VDD. DVFS: Dynamic Voltage/Frequency Scaling: dynamic power reduction by temporary reduction of the power supply voltage and/or the clock frequency f Static Power consumption due to leakage: increasing problem in downscaled technology (0.1…0.5nA per switch) gate leaking (increasing concern, 20-30% of all leakage) Power Manipulation: fixed or DVFS © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Dynamic Voltage/Frequency Scaling (DVFS) Frequency: Can be tuned down until critical path has zero slack Supply Voltage: Delay increased with reduction of VDD Consequence: if no slack in critical path, clock rate f has to be reduced as well Deep look inside technology: where does delay come from? Overview: MOS Current Equations D S iDS G B © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein S VT defines the voltage at whish MOS starts to conduct G B D iSD © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein CMOS inverter PMOS NMOS “Short circuit” instant, 20% of total power consumption Voltage-transfer characteristic of CMOS inverter (VDD = 2.5V) 9 Deep look inside technology: where does delay come from? © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Dynamic Behavior of the CMOS Inverter High to Low Output Transition (I) MN goes from Cutoff over Saturation into Nonsaturation region for the given input. The border between Saturation and Nonsaturation is reached at the time tx and the output voltage Vout = VOH - VTn v I V DD= 5 V R in switch model M P v = 5V + 5V 0V t v O(0+) = 5V I 0 v O M N C MN saturated VOH = 5V MN nonsaturated (Vin - VTn) VOL = 0 V t t1 tX t2 Deep look inside technology: where does delay come from? © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein CMOS Inverter: High to Low Output Transition (II) In order to simplify the final expressions, the integrations on the right for computing tHL are done with the borders from VDD to V0 (V1 = 0,9 VDD, V0 = 0,1 VDD) Saturation: t x t1 COUT VDD VTn VDD dVOUT Kn VDD VTn 2 2 dV dQ COUT OUT dt dt dVOUT dt C OUT i i 2CoutVTn 2 K n VDD VTn Nonsaturation: t2 t x COUT V0 dVOUT Kn 2 2VDD VTn VOUT VOUT 2 2VDD VTn COUT ln 1 K n VDD VTn V0 VDD VTn 2C 1 VOUT OUT ln K n 2VDD VTn 2VDD VTh VOUT V0 VDD VTn Deep look inside technology: where does delay come from? High to Low Output Transition (III) © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein We have used the following integral: In our case: n 1, b 1 dx 1 xn x a bx n an ln a bx n dx 1 x ax x 2 a ln a x t HL t x t1 t2 t x therefore: t HL 2VTn 2VDD VTn ln 1 V0 VDD VTn where COUT K n VDD VTn Delay and VDD not independent !!! Increasing voltage decreases delay © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Delay vs. VDD [Carnegie Mellon's 18-322: course, Lecture 13] 13 Battery © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein [http://nerdist.com/couldhumanity-power-thematrix/] [http://money.cnn.com/20 16/09/02/technology/sams ung-galaxy-note-7-recall/] 14 Embedded Systems: Power Budgeting © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Better Model and Dynamic Behaviour during Load change: Source: TI © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Rules of thumb for the configuration of Low-Power applications: Extended ultra-low power standby mode Minimum active duty cycle Performance on-demand Use interrupts to control program flow Replace software with on chip peripherals Manage the power of external devices Configure unused pins properly, setting them as outputs to avoid floating gate current 16 Low-power efficient coding techniques: © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Optimize program flow Use CPU registers for calculations and dedicated variables Same code size for word or byte => Use word operations whenever possible Use the optimizer to reduce code size and cycles Use local variable (CPU registers) instead of global variables (RAM) Use bit mask instead of bit fields http://processors.wiki.ti.com/index.php/ULP_Advisor 17 Low-power efficient coding techniques (cont.): © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Use unsigned data types where possible Use pointers to access structures and unions Use “static const” class to avoid runtime copying of structures, unions, and arrays Avoid floating point operations Count down “for” loops (loop enrolling) Use short ISRs 18 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Interrupt-driven Code Flow maximazes power efficiency 19 7 tricks for estimating battery life accurately [Beningo engineering] Trick 1:traditional battery budget analysis © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein To estimate the required battery size To anticipate battery life For each component of the system: Determine minimum, typical, maximum current consumption Estimate percentage of time in each state [http://www.eetimes.com/author.asp?doc_id=1324160] 20 Trick 2: Software Rate Monotonic Analysis (RMA) © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Identify different tasks performed by software Identify the time of each task execution Can improve traditional battery budget „guestimations“ 21 Trick 3: Chip vendor tools © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein There are many variables concerning how microcontroller consume energy Vendor datasheets have pages about power consumption based on temperature, voltage, peripheral set, etc. Still, how are these numbers obtained and how accurate they are? E.g. ARM CortexA9 processor has 6 hardware counters which can be configured to monitor 62 local events Chip vendors starting to supply developers with tools with ability to simulate current consumption Example: STMCubeMx from STMicroelectronics 22 Trick 4: Bench-top experiments © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Test assumptions on the bench! As early as possible in the design cycle, prototype parts be tested for real-world behavior! This should not be clean test, but verifies basic assumptions Find a quick and inexpensive way to prove power portion of the design Data taken from the bench can be used to refine the model of power analysis 23 Trick 5: Battery life-cycle analysis © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Concerning rechargable batteries: Manufactured battery good lifetime may decrease dramatically after a few month of usage Peak current draw from embedded system: When the battery is partially discharged, it is possible that peak current can cause the battery voltage to dip into or below its brown out value => dead embedded system 24 Trick 6: Compiler vendor tools © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein When bench testing phase is reached Compiler-related tools can verify energy assumptions Developer can review the profile Determine tasks or functions drawing the largerst amount of energy Can focus on low-power optimizations in potential areas of code IAR Workbench and I-Scope System Profile 25 Trick 7: Get a second opinion © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Co-worker or third party could review the estimations This could result in ideas that may not be considered by original developer [https://madhavisblog.wordpress.com/] 26 Measuring power consumption Test setup for measuring average current consumption: © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein oscilloscope for measuring current with respect to time; for voltage probe use relatively small value resistor • Small enough to not affect low power circuitry • Large enough to provide voltage to measure with decent precision • Easy to calculate Why 10 ? 27 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Current consumption versus time State Time (µs) Current (mA) Wake up 496 6.1 Rx 288 22.3 Tx 104 29.3 Processing 1180 8.1 28 Formulas and calculations © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Average current during event = [(State 1 time)*(State 1 current) + (State 2 time)* (State 2 current) + …] / (Total awake time) Average current = [ (Interval – Total awake time)* (Average sleep current) + (Total awake time)* (Average current during event)] / (Interval) Expected battery life running continuously = (Battery capacity) / (Average current) 29 LP modes of Cortex M4 1/2 Run Mode All up and running, peripherals as specified by the related bits in peripheral specific RCGC registers © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Sleep Mode Forced by Wait For Interrupt (WFI) instruction Clocks for core and memory disabled Peripherals can work with the normal driving clock inputs (defined by ACG bit in RCC register) Deep-Sleep Mode The SLEEPDEEP bit (bit 2) in the System Control (SYSCTRL) Register must be set A Wait For Interrupt (WFI) instruction is executed Differs from Sleep Mode by the option that clock frequency for peripherals (defined by ACG bit in RCC register) may be reduced during Deep-Sleep Hibernate Mode next slide 30 LP modes of Cortex M4 2/2 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Hibernate mode System Clock = OFF Power can be removed except for Hibernation Module which might be independently powered Power can be restored either by : • External signal • Real-Time-Clock (RTC) event Hibernation module provides power control: • Internal switches to CPU and functions while retaining I/O pin power (VDD3ON mode) • With control signal (HIB) that signals external voltage regulator to turn on/off Hibernation module has: • RTC - counters and match registers for timed wake-up • Sixteen 32-bit words of battery-backed memory to save state during hibernation • Low-battery detection and wake-up (interrupt) • etc. next slide [Bay Y Book, p. 68] 31 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Hibernation module of TM4C123GH6PM [TM4C123GH6PM Datasheet] 32 25C TM4C123GH6PM power consumption Mode Conditions 45,1 mA 16 MHz 19,7 mA 1 MHz 10,1 mA Peripherals – all OFF, PLL 80 MHz 24,7 mA Peripherals – all ON, PLL 80 MHz 34,9 mA Peripherals – all ON, PLL 80 MHz 29,5 mA Peripherals – all OFF, PLL 80 MHz 9,73 mA Peripherals – all ON, PIOSC 16 MHz 9,29 mA Peripherals – all OFF, PIOSC 16 MHz 3,51 mA Peripherals – all OFF, LFIOSC 30kHz 1,07 mA Hibernate mode (RTC enabled, VDD3ON mode) System Clock – OFF; VBAT,VDD Hibernate Module 32,768kHz - 4,49 A Hibernate mode (RTC disabled) System Clock - OFF, VBAT only Hibernate Module 32,768kH - 1,38 A Run mode (Flash loop) Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Current 80 MHz Peripherals – all ON, PLL © Frequency Run mode (SRAM loop) Sleep mode (Flash active) Deep-sleep (Flash active) Peripherals – all ON, PIOSC [TM4C123GH6PM Datasheet] 33 © Kalle Tammemäe, Uljana Reinsalu, Thomas Hollstein Readings TM4C123GH6PM Datasheet spms376e.pdf