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Transcript
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
UNIVERSITY MALAYSIA PERLIS
EKT 101
ELECTRIC CIRCUIT THEORY
LAB 5 EXPERIMENT
SEMESTER I (2015/2016)
SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING
NAME
: ______________________________________
MATRIX NO
: ______________________________________
PROGRAMME
: ______________________________________
DATE
: ______________________________________
LECTURER’S NAME
: ______________________________________
1
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
EXPERIMENT 5
SINUSOIDAL STEADY STATE ANALYSIS – SERIES RLC CIRCUIT
OBJECTIVE
1. Measure the current in series RLC circuit using oscilloscope.
2. Apply the dual-trace method to determine the phase angle associated with each voltage of
the circuit and determine which signal leads or lags which.
3. Determine the input impedance using experimental methods.
4. Relate the phase angle between the current and voltage of a resistor.
5. Relate the phase angle between the current and voltage of an inductor.
6. Relate the phase angle between the current and voltage of a capacitor.
INTRODUCTION
PART A: DUAL-TRACE METHOD OF MEASUREMENT
The phase angle between two signals of the same frequency can be determined using the
oscilloscope using dual-trace comparison with the calibrated time base. Despite of giving better
accuracy compared to the Lissajous pattern method, it also can compare two signals of different
amplitudes and different shapes.
The procedure essentially consists of displaying both traces on the screen simultaneously (select
vertical mode button [31] to DUAL) and measuring the distance (in scale division) between two
identical points on the two traces as in Figure 5.1. The input signal is chosen as a reference, that
is, zero-phase angle. In the comparison we assume that the signal being compared is leading
(+) if it is to the left of the reference and lagging (-) if it is to the right of the reference.
V2
reference
V1
D2
D1
Figure 5.1: Measuring phase angle using dual-trace method
2
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
Procedures:
1. Connect the two signals to the two vertical channels, [10] and [12], make sure that
proper grounding are observed. For clarity, adjust the vertical sensitivity of each
waveform until both signals have the same relative size.
2. Engage (depress) GND button [9] to set both traces in the vertical center of the screen.
3. Measure the number of horizontal divisions, D1 occupied by one complete cycle of the
either waveforms. Measure the number of horizontal divisions in the phase shift, D2.
Since D1 is associated with a full cycle of 360o while D2 is associated with phase angle or phase
shift,  then the relationship is,
 
For the case in Figure 5.1:

D2
x 360 o
D1
(5.1)
1div.
x 360 o  120 o (V2 lags V1 )
3 div.
PART B: SINUSOIDAL STEADY STATE RESPONSE OF RLC CIRCUIT
All the basic circuits, Kirchoff’s laws and methods of analysis which previously applied to dc
circuits are equally applicable to ac circuit. The only major distinguish is that in ac we will be
working in phasors in analyzing ac circuits.
Let us revise the response of the individual basic R, L and C to a sinusoidal voltage or current.
For all practical purposes, assume resistor is unaffected by the frequency of the applied voltage.
The voltage source takes up this mathematical expression,
V= Vm sin t
(5.2)
Using Ohm’s law to have the current through the resistor,
IR= V/R =( Vm sin t)/R = Im sin t
(5.3)
From equations (5.2) and (5.3), it is apparent that for purely resistive circuit, voltage and current
are in phase with the peak values related by Ohm’s law.
3
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
Imaginary
VR
Vm
VR
IR
Im



t

(a)
IR
Real
(b)
Figure 5.2 (a) time domain waveform (b) phasor diagram of voltage and current of a resistive
element.
The current through the capacitor can be derived by,
dVC
 C (Vm cos t )  CVm cos t
dt
 I m sin (t  90 o )
IC  C
(5.4)
From equations (5.2) and (5.4), it is apparent that for purely capacitive circuit, current leads
voltage by 90o with the peak values related by Ohm’s law.
Im


Imaginary
VR
Vm
IR



VC
IC
t
90o

Real
Figure 5.3 (a) time domain waveform (b) phasor diagram of voltage and current of a capacitive
element.
4
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
The voltage across the inductor can be derived by,
dI L
 L(I m cos t )  LI m cost
dt
 Vm sin (t  90 o )
VL  L
(5.5)
From equations (5.3) and (5.5), it is apparent that for purely inductive circuit, current lags
voltage by 90o with the peak values related by Ohm’s law.
Imaginary
VL
IL
90o

Real
Figure 5.4 (a) time domain waveform (b) phasor diagram of voltage and current of an inductive
element.
A complete phasor diagram and schematic diagram for a series RLC circuit can be viewed as in
Figure 5.5.
Imaginary
VL
+ VC< - + VL< -
VR
IR= IL = IC


Vs
Real
90o

+
Vs
-
IR = IL = IC
+ VR< -
90o
VC
(a)
(b)
Figure 5.5 (a) Phasor diagram showing the relationship of voltages and currents in series RLC
Circuit. (b) Series RLC schematic diagram.
5
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
The magnitude of the voltage source is in a series RLC circuit is given by,
Vs  VR  (VL  VC ) 2  I
2
R 2  ( X L  X C ) 2  IZ T
(5.6)
while the phase angle of the circuit is given by,
  tan 1
VL  VC X L  X C

VR
R
(5.7)
and the impedance can be determined by,
ZT  R  j( X L  X C )
(5.8)
In a series RLC circuit, the voltage across the reactive component may be greater than the input
voltage.
EQUIPMENT/COMPONENT
Dual-trace oscilloscope (1)
Function Generator (1)
Resistor (1/4 W) – 1 k
Capacitor – 0.22 F
Inductor – 10 mH
Breadboard (1)
**For all theoretical calculation results students are strictly required to show their work in
progress (WIP in formula form/complete figures) in the PRE-LAB space provided before the lab
session. Otherwise they will be forbidden from participating the session. There will be certain
marks allocated for this part.
6
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
PROCEDURE
1. Construct the circuit as depicted in Figure 5.6 below. Insert the measured value of R in Table
1(a). The internal dc resistance of the inductor and capacitor will be ignored comparable to
R.
CC
=0.22microFarad
= 0.022 uF L = 10 mH
CH1
+ VC< -
+ VL< R = 1 k
Ip-p
+ VR< -
+
Vs
-
CH2
Figure 5.6: Circuit diagram of a series RLC circuit
2. Set the function generator to produce a sine wave input signal of amplitude 8Vp-p and
frequency 5 kHz. Use this input voltage as the reference signal.
3. Obtain the Vs and VR traces on the scope. Make sure you have done the correct settings as
instructed in Introduction (Part A). Draw the waveforms in Figure R1 and label them
completely with the details. Since the resistor voltage VR is in phase with the current I, thus
the phase difference between Vs and VR equals to the phase angle between Vs and I
waveforms.
4. Determine the number of horizontal divisions for one complete cycle of either waveform
denoted as D1 and the horizontal divisions for the phase shift between the Vs and VR denoted
as D2. Now determine the phase shift, 1 in degrees using Eq. (5.1). Insert all the measured
values in Table 1. From the results of Figure R1 and Table 1(a) represent the signals VR and I
in both polar and rectangular forms and insert the answers in Table 2. Determine Ip-p from
ohm’s law, Ip-p = VR(p-p) / Rmeasured. Also determine the total impedance, ZT = Vs/Ip-p.
5. Secondly, obtain the Vs and VC traces on the scope by interchanging the position of resistor
and capacitor as depicted in Figure 5.7. The elements need to exchange positions to avoid
“shorting-out” of the resistor and inductor if we simply place the probe of the scope across
the capacitor of Figure 5.6. In other words we must ensure the common ground between
the generator and scope. Draw the waveforms in Figure R2 and label them completely with
the details.
7
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
L
CH1 + VR< -
+ VC< -
R
+
Vs
-
CH2
+ VL< C
Ip-p
Figure 5.7: Measuring VC using the oscilloscope and ensuring common ground between the
source and output
6. Determine the number of horizontal divisions for one complete cycle of either waveform
denoted as D1 and the horizontal divisions for the phase shift between the Vs and VC denoted
as D2. Now determine the phase shift, 2 in degrees using Eq. (5.1). Insert all the measured
values in Table 1. From the results of Figure R2 and Table 1(a) represent the signal VC in both
polar and rectangular forms and insert the answer in Table 2.
7. Thirdly, obtain the Vs and VL traces on the scope by interchanging the position of resistor and
inductor as depicted in Figure 5.8. Draw the waveforms in Figure R3 and label them
completely with the details.
CH1
+ VC< -
+ VR< -
CH2
R
L
Ip-p
+ VL< -
+
Vs
-
C
Figure 5.8: Measuring VL using the oscilloscope and ensuring common ground between the
source and output
8. Determine the number of horizontal divisions for one complete cycle of either waveform
denoted as D1 and the horizontal divisions for the phase shift between the Vs and VL denoted
as D2. Now determine the phase shift, 3 in degrees using Eq. (5.1). Insert all the measured
values in Table 1. From the results of Figure R3 and Table 1(a) represent the signal VL in both
polar and rectangular forms and insert the answer in Table 2.
8
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
RESULT
Horizontal sensitivity
= _______
Vertical sensitivity
= _______
Figure R1: Vs versus VR
Horizontal sensitivity
= _______
Vertical sensitivity
= _______
Figure R2: Vs versus VC
9
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
Horizontal sensitivity
= _______
Vertical sensitivity
= _______
Figure R3: Vs versus VL
VR
Measured
Resistance ()
D1
(div)
D2
(div)
VC
1
(degree)
D1
(div)
D2
(div)
VL
2
(degree)
D1
(div)
D2
(div)
3
(degree)
Table 1(a): Experimental results of phase shift measurement between Vs and VR, Vs and VC and Vs
and VL.
Phase Angle
1
(degree)
2
(degree)
3
(degree)
1 + 2
(degree)
3 - 1
(degree)
Experimental Result
Theoretical Results (PRE-LAB)
Percentage Difference (%)
Leading or Lagging Reference
Table 1(b): Phase shift deviation between experimental and theoretical results.
10
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
MATHEMATICAL
REPRESENTATION
LABORATORY MODULE
POLAR
RECTANGULAR
XC ()
XL ()
ZT = Rmea ± jX ()
Theoretical
Result
(PRE-LAB)
Ip-p = Vs/ZT (mA)
VR (V)
VC (V)
VL (V)
VR (V)
VC (V)
Experimental
Result
VL (V)
Ip-p = VR/Rmea (mA)
ZT = Vs/Ip-p ()
Table 2: Phasor representation of circuit variables (all values in peak-peak).
11
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
PRE-LAB CALCULATION (Show your WIP)
(All calculations should be done in peak-peak values and at the operating frequency 5 kHZ.)
1. Calculate the phasor current, Ip-p and phasor impedance, ZT
2. Obtain the phasor voltages for VR, VC and VL.
3. Sketch the phasor diagram of the circuit
12
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
4. Determine phase angle between the reference signal Vs and the following and specify
whether it is leading or lagging the reference:
(i) VR
(ii) VC
iii) VL
5. Calculate the phase angle between:
(i) VR and IR
(ii) VC and IC
(iii) VL and IL
13
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
EVALUATION QUESTION
1. What do you think will happen to the phase angle of the current in this experiment if the
value of resistance increases?
Answer:
___________________________________________________________________________
___________________________________________________________________________
_________________________________________________________
2. Using the measured values of all the voltages and current, sketch the phasor diagram in
Figure E1.
Figure E1
3. Based on the series RLC circuit in Figure 5.6, suggest the possible modification to the circuit
to achieve overall phase angle of :
(i)
(ii)
(iii)
0o
900
-90
Answer:
___________________________________________________________________________
___________________________________________________________________________
_________________________________________________________
14
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit
EKT101/4 ELECTRIC CIRCUIT THEORY
LABORATORY MODULE
4. In this experiment (based on consideration that none of the circuit elements being omitted
in Figure 5.6) can we directly measure the phase angle between VL and IL or VC and IC? Justify
your answer.
Answer:
___________________________________________________________________________
___________________________________________________________________________
_________________________________________________________
15
Universiti Malaysia Perlis (UniMAP)
Lab 5 : Sinusoidal Steady State Analysis and Series RLC
Circuit