AD5304 数据手册DataSheet 下载
... Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered ...
... Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered ...
Low-Power, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable OPA2890 FEATURES
... exceptional single-supply operation. Using a single +5V supply, the OPA2890 can deliver a 0.9V to 4.1V output swing with over 30mA drive current and 210MHz bandwidth. This combination of features makes the OPA2890 an ideal RGB line driver or single-supply analog-to-digital converter (ADC) input driv ...
... exceptional single-supply operation. Using a single +5V supply, the OPA2890 can deliver a 0.9V to 4.1V output swing with over 30mA drive current and 210MHz bandwidth. This combination of features makes the OPA2890 an ideal RGB line driver or single-supply analog-to-digital converter (ADC) input driv ...
MoTeC ADL3/EDL3 User Manual Copyright
... times, fuel calculations, minimum corner speeds, maximum straight speeds and more. The ADL3 performs calculations, acquiring data from other MoTeC devices such as an ECU, Dash Logger and several VIM input modules, which enable it to log more than 300 inputs. ...
... times, fuel calculations, minimum corner speeds, maximum straight speeds and more. The ADL3 performs calculations, acquiring data from other MoTeC devices such as an ECU, Dash Logger and several VIM input modules, which enable it to log more than 300 inputs. ...
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)
... Fig. 9. The clock signals φ switches from 1 to 0, the circuit is in precharge/recharge phase. During the precharge phase, RP1 turns on and recharges the gate of EN1 to 1. Meanwhile φ switches from 0 to 1 which turns on RN1 and recharges the gate of pMOS transistor P1 to 0. Thus both EN1 and P1 turn ...
... Fig. 9. The clock signals φ switches from 1 to 0, the circuit is in precharge/recharge phase. During the precharge phase, RP1 turns on and recharges the gate of EN1 to 1. Meanwhile φ switches from 0 to 1 which turns on RN1 and recharges the gate of pMOS transistor P1 to 0. Thus both EN1 and P1 turn ...
NB6L611 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer
... NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functiona ...
... NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functiona ...
30 W 18 to 60-V Input DC/DC Converter w/Auto Track Sequencing
... voltage that can be set to one of the common intermediate bus voltages of 3.3 V, 5 V, or 12 V. The PTB78560 series incorporates Auto-Track™, a feature that simplifies the power-up sequencing of multiple power modules that operate from the same intermediate bus. During a power-up cycle, modules with ...
... voltage that can be set to one of the common intermediate bus voltages of 3.3 V, 5 V, or 12 V. The PTB78560 series incorporates Auto-Track™, a feature that simplifies the power-up sequencing of multiple power modules that operate from the same intermediate bus. During a power-up cycle, modules with ...
PC107A
... 4. Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23. 5. SDMA[10–1] are reset configuration pins and have internal pull-up resistors which are enabl ...
... 4. Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23. 5. SDMA[10–1] are reset configuration pins and have internal pull-up resistors which are enabl ...
+3.3V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers General Description Features
... RS-485/RS-422 transceivers feature one driver and one receiver. These devices include fail-safe circuitry, guaranteeing a logic-high receiver output when receiver inputs are open or shorted. The receiver outputs a logic high if all transmitters on a terminated bus are disabled (high impedance). The ...
... RS-485/RS-422 transceivers feature one driver and one receiver. These devices include fail-safe circuitry, guaranteeing a logic-high receiver output when receiver inputs are open or shorted. The receiver outputs a logic high if all transmitters on a terminated bus are disabled (high impedance). The ...
Features •
... “set” and divide by eight when DIV_CNTRL is “clear”. With a 13.0000MHz crystal, this yields an output of 3.25MHz or 1.625MHz, respectively. When CLK_ON is “clear”, no clock is available at CLK and the transmitter has less current consumption. The CLK signal can be used to clock a microcontroller. It ...
... “set” and divide by eight when DIV_CNTRL is “clear”. With a 13.0000MHz crystal, this yields an output of 3.25MHz or 1.625MHz, respectively. When CLK_ON is “clear”, no clock is available at CLK and the transmitter has less current consumption. The CLK signal can be used to clock a microcontroller. It ...
LTC2960 - 36V Nano-Current Two
... voltage monitor, ideally suited for multicell battery applications. External resistive dividers configure custom comparator thresholds. The supervisory circuit monitors the ADJ input and pulls the RST output low when the input drops below threshold. A reset timeout period delays the return of the RS ...
... voltage monitor, ideally suited for multicell battery applications. External resistive dividers configure custom comparator thresholds. The supervisory circuit monitors the ADJ input and pulls the RST output low when the input drops below threshold. A reset timeout period delays the return of the RS ...
OPA698 Unity-Gain Stable, Wideband Voltage Limiting Amplifier FEATURES
... DESCRIPTION The OPA698 is a wideband, unity-gain stable voltagefeedback op amp that offers bipolar output voltage limiting. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to ...
... DESCRIPTION The OPA698 is a wideband, unity-gain stable voltagefeedback op amp that offers bipolar output voltage limiting. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to ...
document
... function of temperature. The changes in temperature will affect the propagation speed of the delay line, and therefore the LSB duration; higher temperatures will imply a worse LSB duration. At 10 C the LSB duration is 9.8 ps and at 60 C the LSB duration will be slightly above 10.8 ps. Another phenom ...
... function of temperature. The changes in temperature will affect the propagation speed of the delay line, and therefore the LSB duration; higher temperatures will imply a worse LSB duration. At 10 C the LSB duration is 9.8 ps and at 60 C the LSB duration will be slightly above 10.8 ps. Another phenom ...
MAX8588 High-Efficiency, Low-I PMIC with Dynamic Core for PDAs and Smartphones
... RL = external inductor ESR IOUT(MAX) = maximum required load current f = operating frequency minimum L = external inductor value ILIM can be substituted for IOUT(MAX) (desired) when solving for D. This assumes that the inductor ripple current is small relative to the absolute value. Note 4: POK only ...
... RL = external inductor ESR IOUT(MAX) = maximum required load current f = operating frequency minimum L = external inductor value ILIM can be substituted for IOUT(MAX) (desired) when solving for D. This assumes that the inductor ripple current is small relative to the absolute value. Note 4: POK only ...
Asahi Keiki Co., Ltd
... Use a power voltage within the operation range; otherwise, it may result in a fire, electrical shock, or malfunction. The contents of this manual are subject to change without notice. Although the contents of this manual have been prepared with extra care, if you have any questions, or find errors o ...
... Use a power voltage within the operation range; otherwise, it may result in a fire, electrical shock, or malfunction. The contents of this manual are subject to change without notice. Although the contents of this manual have been prepared with extra care, if you have any questions, or find errors o ...
DIFFERENT TYPES OF LOGIC GATES
... • TTL Circuit features • Circuit Parameters • TTL families Ch06L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 ...
... • TTL Circuit features • Circuit Parameters • TTL families Ch06L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 ...
AD7792 数据手册DataSheet下载
... CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge ...
... CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge ...
Single-Supply, High-Speed, Precision
... Eight Decades, 100pA to 10mA 2.5V REFERENCE STABLE OVER TEMPERATURE LOW QUIESCENT CURRENT: 10mA DUAL OR SINGLE SUPPLY: +5V, +5V PACKAGE: Small QFN-16 (4mm x 4mm) SPECIFIED TEMPERATURE RANGE: −5°C to +75°C ...
... Eight Decades, 100pA to 10mA 2.5V REFERENCE STABLE OVER TEMPERATURE LOW QUIESCENT CURRENT: 10mA DUAL OR SINGLE SUPPLY: +5V, +5V PACKAGE: Small QFN-16 (4mm x 4mm) SPECIFIED TEMPERATURE RANGE: −5°C to +75°C ...
LT5554
... of input coupling capacitor sets the low frequency corner (LF) at input. The output coupling capacitors or the transformer sets the low frequency corner (LF) at the output. The LT5554 operates internally down to DC. ...
... of input coupling capacitor sets the low frequency corner (LF) at input. The output coupling capacitors or the transformer sets the low frequency corner (LF) at the output. The LT5554 operates internally down to DC. ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.