AD7665 数据手册DataSheet下载
... Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master R ...
... Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master R ...
DS1270Y/AB 16M Nonvolatile SRAM FEATURES PIN ASSIGNMENT
... 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1270 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR ...
... 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1270 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR ...
20090826_FlatPanel_status
... Our layout: – two-stage amplifier – 50W input and output termination – each stage with gain 10 operation outside recommended range… – strong noise filtering – signal GND and power GND separated ...
... Our layout: – two-stage amplifier – 50W input and output termination – each stage with gain 10 operation outside recommended range… – strong noise filtering – signal GND and power GND separated ...
Features Pin Configuration Description Pin Description
... The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels. Only one SCx/SDx channel is selected at a time, determined by the contents of the programmable control register. A power-on reset function puts the registers in their default state and initializes the I2C bus state mach ...
... The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels. Only one SCx/SDx channel is selected at a time, determined by the contents of the programmable control register. A power-on reset function puts the registers in their default state and initializes the I2C bus state mach ...
Transmitter and Receiver Circuit Design
... Intro/Background: The Ethernet is the most widely used of the current Local Area Network (LAN) technologies. It is a family of closely related protocols which share a common set of frame formats. With the increasing usage of the Internet and multi-media applications, higher bandwidth is needed to ac ...
... Intro/Background: The Ethernet is the most widely used of the current Local Area Network (LAN) technologies. It is a family of closely related protocols which share a common set of frame formats. With the increasing usage of the Internet and multi-media applications, higher bandwidth is needed to ac ...
JESD204B Survival Guide
... has the advantage over CMOS due to the lower signal swings and differential signaling. The LVDS output driver does not have to drive such a large signal to many different outputs and does not draw a large amount of current from the power supply when switching logic states, as the CMOS driver would. ...
... has the advantage over CMOS due to the lower signal swings and differential signaling. The LVDS output driver does not have to drive such a large signal to many different outputs and does not draw a large amount of current from the power supply when switching logic states, as the CMOS driver would. ...
FEATURES DESCRIPTION
... circuit situation differently. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to nea ...
... circuit situation differently. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to nea ...
DS1265Y/AB 8M Nonvolatile SRAM FEATURES PIN ASSIGNMENT
... 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1265 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR ...
... 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1265 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR ...
MAX1686/MAX1686H 3V to 5V Regulating Charge Pumps for SIM Cards General Description
... modes of operation: 3V mode or 5V mode. The devices consist of an error amplifier, a 1.23V bandgap reference, an internal resistive feedback network, a 1MHz oscillator, high-current MOSFET drivers and switches, and a power-management block as shown in the Functional Diagram (Figure 1). In 3V mode (3 ...
... modes of operation: 3V mode or 5V mode. The devices consist of an error amplifier, a 1.23V bandgap reference, an internal resistive feedback network, a 1MHz oscillator, high-current MOSFET drivers and switches, and a power-management block as shown in the Functional Diagram (Figure 1). In 3V mode (3 ...
ST3241EB
... The ST3241E device consists of 3 drivers, 5 receivers and a dual charge-pump circuit. The device meets the requirements of EIA/TIA and V.28/V.24 communication standards providing high data rate capability and enhanced electrostatic discharge (ESD) protection. All transmitter outputs and receiver inp ...
... The ST3241E device consists of 3 drivers, 5 receivers and a dual charge-pump circuit. The device meets the requirements of EIA/TIA and V.28/V.24 communication standards providing high data rate capability and enhanced electrostatic discharge (ESD) protection. All transmitter outputs and receiver inp ...
L6370Q
... deactivates itself. The following actions are taken: all the output stage is switched off; the signal DIAG2 is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Θlim-ΘH. The different thresholds with hystereti ...
... deactivates itself. The following actions are taken: all the output stage is switched off; the signal DIAG2 is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Θlim-ΘH. The different thresholds with hystereti ...
TLV1571 数据资料 dataSheet 下载
... The TLV1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the analog input should not exceed the positi ...
... The TLV1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the analog input should not exceed the positi ...
555 Timer
... and a “low” value equal to 0V. • When the Threshold comparator saturates, the flip flop is Reset (R) and it outputs a low signal at pin 3. • When the Trigger comparator saturates, the flip flop is Set (S) and it outputs a high signal at pin 3. ...
... and a “low” value equal to 0V. • When the Threshold comparator saturates, the flip flop is Reset (R) and it outputs a low signal at pin 3. • When the Trigger comparator saturates, the flip flop is Set (S) and it outputs a high signal at pin 3. ...
TS4100,01,02 - Silicon Labs
... TS4100/01/02 Data Sheet "Rail-to-Rail Plus"™, 1% RON Flatness, 0.8 V to 5.25 V Analog ...
... TS4100/01/02 Data Sheet "Rail-to-Rail Plus"™, 1% RON Flatness, 0.8 V to 5.25 V Analog ...
MAX1242/MAX1243 +2.7V to +5.25V, Low-Power, 10-Bit Serial ADCs in SO-8 __________________General Description
... When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7µF reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the internal reset time is 10µs after the power supplies have stabilized. No conversion ...
... When power is first applied, and if SHDN is not pulled low, it takes the fully discharged 4.7µF reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the internal reset time is 10µs after the power supplies have stabilized. No conversion ...
BDTIC www.BDTIC.com/infineon Power Management & Multimarket
... means of the inputs D0...D7 without any additional logic signal. The IC can replace 8 optocouplers and the 8 high-side switches in conventional I/O-Applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. The µC compatible interface allows a dir ...
... means of the inputs D0...D7 without any additional logic signal. The IC can replace 8 optocouplers and the 8 high-side switches in conventional I/O-Applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. The µC compatible interface allows a dir ...
batchmate 1500 - Red Seal Measurement
... and rate displays. An optional 16-point K-factor can linearize flow from meter outputs. The user, with the push of a button, can toggle back and forth to view the total of the batch, the rate of flow or the grand total of flow. The BATCHMATE may be thought of as two separate counters and a rate mete ...
... and rate displays. An optional 16-point K-factor can linearize flow from meter outputs. The user, with the push of a button, can toggle back and forth to view the total of the batch, the rate of flow or the grand total of flow. The BATCHMATE may be thought of as two separate counters and a rate mete ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.