DN1021 - How to Produce Negative Output Voltages from Positive
... surface-mount package. They include the DC/DC controller, inductor, power switches and supporting circuitry. These highly integrated regulators also provide an easy solution for applications that require negative output voltages. In other words, these products can operate as inverting buck-boost reg ...
... surface-mount package. They include the DC/DC controller, inductor, power switches and supporting circuitry. These highly integrated regulators also provide an easy solution for applications that require negative output voltages. In other words, these products can operate as inverting buck-boost reg ...
Programmable Logic Controllers - Goodheart
... Discrete Input Modules (Cont.) • Zener diode: – Semiconductor device that can maintain a steady voltage level. – When phototransistor becomes saturated, ensures that a steady +5 V is applied to the CPU circuit board. ...
... Discrete Input Modules (Cont.) • Zener diode: – Semiconductor device that can maintain a steady voltage level. – When phototransistor becomes saturated, ensures that a steady +5 V is applied to the CPU circuit board. ...
ZXLD1615 ADJUSTABLE DC-DC BOOST CONVERTER WITH INTERNAL SWITCH IN TSOT23-5 DESCRIPTION
... However, by varying the duty cycle of the EN signal at a suitably high frequency (f>10kHz), the control loop will see a voltage, that has an average value equal to the duty cycle multiplied by VREF. This provides a means of adjusting the output voltage to a lower value. It also allows the device to ...
... However, by varying the duty cycle of the EN signal at a suitably high frequency (f>10kHz), the control loop will see a voltage, that has an average value equal to the duty cycle multiplied by VREF. This provides a means of adjusting the output voltage to a lower value. It also allows the device to ...
FUNCTION REPRODUCTION WITH POLYCHRONOUS SPIKING NETWORKS
... testing run is performed, at which point the output of the system caps at 10 and -10. Experiments with greater numbers of hidden neurons initially seemed unpromising, but extending the training time to 299 iterations and the hidden neuron count to 10, while changing both learning and momentum gain t ...
... testing run is performed, at which point the output of the system caps at 10 and -10. Experiments with greater numbers of hidden neurons initially seemed unpromising, but extending the training time to 299 iterations and the hidden neuron count to 10, while changing both learning and momentum gain t ...
MAX9310A 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs
... to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table (Figure 1). When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, leave unconnected. The VBB reference can source or sink 500µA. Use ...
... to switch the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table (Figure 1). When using the VBB reference output, bypass it with a 0.01µF ceramic capacitor to VCC. If the VBB reference is not used, leave unconnected. The VBB reference can source or sink 500µA. Use ...
Implementation of Ternary Logic Circuits
... discus the quantum dot gate FET (QDGFET) that produces three states in its transfer characteristic: OFF, ON and a low current saturation state known as intermediate state ("i") because of the presence of quantum dots in the gate region. The complementary function shows the use of QDGFETs in a three- ...
... discus the quantum dot gate FET (QDGFET) that produces three states in its transfer characteristic: OFF, ON and a low current saturation state known as intermediate state ("i") because of the presence of quantum dots in the gate region. The complementary function shows the use of QDGFETs in a three- ...
THS1230 数据资料 dataSheet 下载
... Table 2 assumes that the delta in ADC reference voltages VREFT and VREFB is set to 1 V, i.e., VREFT – VREFB = 1 V. Note that VREFB and VREFT can be set externally, which will scale the numbers given in this table. The user-chosen operating configuration and reference voltages determine what input si ...
... Table 2 assumes that the delta in ADC reference voltages VREFT and VREFB is set to 1 V, i.e., VREFT – VREFB = 1 V. Note that VREFB and VREFT can be set externally, which will scale the numbers given in this table. The user-chosen operating configuration and reference voltages determine what input si ...
A 10Gb/s wide-band current-mode logic I/O interface for high
... The architecture of a differential current-mode logic buffer circuit in this work is shown in Fig. 6. It includes an active inductor form by PMOS transistors that act as active resistors connected to NMOS transistors load. The input impedance increases with the frequency and acts as the on-chip indu ...
... The architecture of a differential current-mode logic buffer circuit in this work is shown in Fig. 6. It includes an active inductor form by PMOS transistors that act as active resistors connected to NMOS transistors load. The input impedance increases with the frequency and acts as the on-chip indu ...
DS1302 数据手册DataSheet 在线下载
... This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pat ...
... This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pat ...
CDR`s circuit performance in sensing and recovering
... filter transfer function is identified as below from (5) to (9). Equation (5) shows a second order transfer function of RLC low pass filter. The equation (6) is the same as the equation (5) except that the denominator has been organized with a1 =LC and a2=RC so as to make it clear that the denominat ...
... filter transfer function is identified as below from (5) to (9). Equation (5) shows a second order transfer function of RLC low pass filter. The equation (6) is the same as the equation (5) except that the denominator has been organized with a1 =LC and a2=RC so as to make it clear that the denominat ...
MAX961–MAX964/ MAX997/MAX999 Single/Dual/Quad, Ultra
... because of noise or undesirable parasitic feedback. This can occur when the voltage on one input is close to or equal to the voltage on the other input. These devices have a small amount of internal hysteresis to counter parasitic effects and noise. The added hysteresis of the MAX961–MAX964/MAX997/ ...
... because of noise or undesirable parasitic feedback. This can occur when the voltage on one input is close to or equal to the voltage on the other input. These devices have a small amount of internal hysteresis to counter parasitic effects and noise. The added hysteresis of the MAX961–MAX964/MAX997/ ...
AD7401A 数据手册DataSheet下载
... The AD7401A1 is a second-order, sigma-delta (Σ-Δ) modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7401A operates from a 5 V power supply and accepts a differential input sign ...
... The AD7401A1 is a second-order, sigma-delta (Σ-Δ) modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7401A operates from a 5 V power supply and accepts a differential input sign ...
DS1302 - Maxim Integrated
... This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pat ...
... This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pat ...
PICASSO - Soundstream
... 3. Input Overload Indicators - Indicates the signal input level or input gain level is too high channels 1 & 2. 4. Input Level Selector Switch - Selectable input sensitivity range from 0.2-2 Volts RMS, or from 0.5-5 Volts RMS - channels 1 & 2. 5. Left Channel Balanced / Unbalanced Input Selector Swi ...
... 3. Input Overload Indicators - Indicates the signal input level or input gain level is too high channels 1 & 2. 4. Input Level Selector Switch - Selectable input sensitivity range from 0.2-2 Volts RMS, or from 0.5-5 Volts RMS - channels 1 & 2. 5. Left Channel Balanced / Unbalanced Input Selector Swi ...
DAC7811 数据资料 dataSheet 下载
... dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low, but before the first active clock edge, it will be ignored. If the SDO p ...
... dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low, but before the first active clock edge, it will be ignored. If the SDO p ...
Resistivity and Conductivity
... both transistors are turned on by logic 1 inputs. If either input is a logic 0 that transistor cannot conduct, so there is no current through either one. The output is then a logic 1. This is the behavior of a NAND gate. Of course, an inverter can also be included to provide an AND output at the sam ...
... both transistors are turned on by logic 1 inputs. If either input is a logic 0 that transistor cannot conduct, so there is no current through either one. The output is then a logic 1. This is the behavior of a NAND gate. Of course, an inverter can also be included to provide an AND output at the sam ...
ACTIONI/Q Q498 ® DC Powered DC Input Field Configurable
... grounded, the current output level that is being processed cannot be stopped. As an extreme example, if the output has been told to make a step change from 0V to 10V, the output could still be in the process of slewing to that value (which could take as long as 700mSec). When the Hold input is appli ...
... grounded, the current output level that is being processed cannot be stopped. As an extreme example, if the output has been told to make a step change from 0V to 10V, the output could still be in the process of slewing to that value (which could take as long as 700mSec). When the Hold input is appli ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.