Download nLIGHTEN Transmitter Module nL1201

S P E C I F I C A T I O N S
S H E E T
nLIGHTEN™ TRANSMITTER MODULE
nL1201-1.6 (12 CHANNEL 1.6 Gbps)
W.
L.
GORE
AND
A S S O C I AT E S ,
INC.
•
ELECTRONIC
PRODUCTS
DIVISION
Executive Summary
W. L. Gore & Associates, Inc. manufactures high-speed components for
use in telecom and data communications equipment. The nL1201-1.6
parallel optic module is a 12-channel transmitter used to convert twelve
differential electrical inputs to twelve optical outputs at 1.6 Gbps per
channel. When used with a nL1202-1.6 receiver, this device transfers
an aggregate bandwidth of 19.2 Gbps up to 300 meters using standard
FDDI grade 62.5 µm multimode ribbon fiber.
Features
• 1.6 Gbps data transmission
• 19.2 Gbps aggregate link bandwidth
• 12 optical output channels
• 850 nm VCSEL technology
• Low Voltage Differential Swing (LVDS) inputs
• Class 1M laser product to Amendment 2 of IEC60825-1
• Complies with CFR 1040.10 and 1040.11 except for deviations
pursuant to Laser Notice No. 50
• MPO Connector
• Channel BER 10–12 when used with nL1202-1.6 receiver
• Designed for use with standard FDDI grade 62.5/125 µm graded
index fiber
• Link distance up to 300 meters when used with nL1202-1.6 receiver
• Opto-electrically compatible per multi-source agreement
• Multi-source footprint design
Applications
• High-speed Telecom: Intra- and inter-system links for terabit switches,
routers, and access equipment.
• High-speed Data Communications: Rack to rack, board to board
and backplane applications.
W. L. Gore & Associates, Inc.
Figure 1
nLIGHTEN™ Transmitter Module
Bar Code
(Serial No.) (Part No.)
Pin
28
11.84
Pin
1
DE Interface
Laser Engrave Text as Shown
Pin
29
18.15 17.90
13.64
Pin
44
Pin
45
Pin
72
Note: Protective Plug
Included with
Module
10.20
Date of
Manufacture
57.05
Operating
Case Temperature
Reference Point
18.15
1.28
1.28
6
Optical
Axis
9.03
10
0.2
0.25
1.20
14.90
4.0
7.03
0.65 pitch
Transmitter Key
21.54
33.89
4xM2
2.52
Recommended PCB Layout
Detail A
2.775
Detail A
8X Annular Ring 3mm ID/4mm OD
on both sides of the board to be
attached to ground
7
4X
2.54+.03/–0
72X
1.8±.05
72X
0.35+.05/–0
15.6
14.9
18.7
2.575
15X
0.65=9.75
12.59
3.5
Ø 2.0
MPO
27X
0.65=17.55
1.64
33.89
22.35
Transmitter Performance Specifications
Table A
General
Symbol
Min
Vcc
3.135
Power Dissipation
Power Supply
3.3
Max
Symbol
Min
Pout
–10
Extinction Ratio
6
Center Wavelength
λ
Spectral Width (rms)
Units Notes
Electrical Parameters
Symbol
mW
Differential In
Amplitude
|VIH-VIL| 150
3.465
V
80
°C
5
Input Common Mode
0
Data Rate
Launch Power (ave)
Typical
1100 1500
Operating Case
Temperature
Optical Parameters
Table B
Typical
Max
1.6
Gbps
–4
7.3
830
6
Units Notes
dBm
1,2
dB
3
860
nm
∆λ
0.85
nm
Relative Intensity Noise
RIN
–117 dB/Hz
Output Risetime (20-80)
Tr
205
ps
3
Tf
205
ps
3
Total Jitter (pk-pk)
Tj
190
ps
4
150
ps
Notes:
1. The nLIGHTEN™ transmitter module has been certified as a Class
1M laser product according to Amendment 2 of IEC60825-1
published in January 2001 and complies with CFR 1040.10 and
1040.11 except for deviations pursuant to Laser Notice No. 50,
dated May 27, 2001.
2. Minimum average power is equivalent to 120 µW OMA (optical
modulation amplitude). OMA defined as the difference in optical
power between a logic 1 and a logic 0 as defined in the HiPPI6400 Optical PHY specification.
3. Measured with an unfiltered K28.7 pattern.
4. Measured as TP1 to TP2 (jitter transfer) as defined in IEEE 802.3z
Gigabit Ethernet Specification Section 38.5. Total jitter is equal to
the sum of the deterministic and random jitter. Deterministic jitter is
measured at the average level of a K28.5 data pattern. Random
jitter is measured at the average level of a K28.7 data pattern.
5. Power dissipation values assume device is operating in LVDS Mode.
6. Minimum ambient air to be 0 °C.
1.0
Typical
1.2
Input Overshoot
Input Impedance
90
100
Max
Unit Notes
400
mV
1
Vcc
V
2
20
%
110
Ω
Notes:
1. Into 100 Ω differential termination.
2. Common mode (logic threshold) relative to ground.
3. On-module termination: input-to-complementary input.
Output Falltime (20-80)
Channel-Channel Skew
Min
3
VIL
Figure 4 describes the timing sequence for data transmission from the
nLIGHTEN™ Tx module. WDRST is an internal clock with a nominal
period of 28 mS. This signal remains high for a nominal time of 13.8
µS. During this “high” period, the “watch dog” circuitry within the module
determines if any fault conditions exist (Vcc excursions, floating inputs). If
a fault condition is found, the WDOUT signal (Pin 6) remains low and
the offending channel(s) laser(s) remain off. If no fault condition is found,
the WDOUT signal (Pin 6) transitions high, and all channels function
normally. As illustrated in Figure 4, the WDRST signal is asynchronous
to any data input to the Tx module. The time from point t1 (data first
transmitted to the Tx module) to point t2 (Tx module transmitting valid
data) will be dependant on the cycle of WDRST. The maximum period
of the WDRST signal is 42 mS. (Please reference “Signal Description
Application Note” for more information.)
Time
Figure 4
Control Signal Timing Data
Figure 2
LVDS* Signal Levels (AC and DC Coupled)
mV
Single Ended
VIH
Vcm
|VID|
WDRST
|VID| = |VIH - VIL| (SPEC: 150 mV min, 400 mV max)
*See IEEE Standard for LVDS Signals
Figure 3
Transmitter Input Stage Schematic
Vcc
20k
IN
100
INB
20k
t2
t1
t2
t1
t2
t1
t2
Tx Module
Input Data
Vcm = (VIH + VIL) / 2
Note: In DC coupled configuration, Vcm must be between 1.0 V and
Vcc. In AC coupled configuration, internal pull-up resistors set Vcm to
Vcc.
t1
WDOUT
Tx Module
Output Data
Table C Transmitter Pin Assignments
Pin
Pin Name
Description
Logic Level
Notes
Pin
Pin Name
Description
Logic Level
1
Vcc
Power Supply Voltage
3.3 V DC
1
37
IN 7b
Input #7 Inverted
LVDS
2
NC
Not Connected
38
IN 7a
Input #7 Non-Inverted
LVDS
3
NC
Not Connected
39
GND
Ground
4
NC
Not Connected
40
GND
Ground
5
NC
Not Connected
41
IN 8b
Input #8 Inverted
LVDS
6
WDOUT
Watchdog Ouput
42
IN 8a
Input #8 Non-Inverted
LVDS
7
GND
Ground
43
GND
Ground
8
GND
Ground
44
GND
Ground
45
GND
Ground
9
LVCMOS
Output, “L”=Fault
2
NC
Not Connected
10
PNEN
PN Code Generator
“H” = enable
11
GND
Ground
12
GND
Ground
13
IN 1b
Input #1 Inverted
LVDS
14
IN 1a
Input #1 Non-Inverted
LVDS
15
GND
Ground
16
GND
Ground
17
IN 2b
Input #2 Inverted
LVDS
18
IN 2a
Input #2 Non-Inverted
LVDS
19
GND
Ground
20
GND
Ground
21
IN 3b
Input #3 Inverted
LVDS
22
IN 3a
Input #3 Non-Inverted
LVDS
58
GND
Ground
23
GND
Ground
59
IN 12b
Input #12 Inverted
LVDS
24
GND
Ground
60
IN 12a
Input #12 Non-Inverted
LVDS
25
NC
Not Connected
61
GND
Ground
26
IN 4b
Input #4 Inverted
LVDS
62
GND
Ground
27
IN 4a
Input #4 Non-Inverted
LVDS
63
NC
Not Connected
28
GND
Ground
64
WDRST
Watch Dog Reset
29
IN 5b
Input #5 Inverted
LVDS
65
GND
Ground
30
IN 5a
Input #5 Non-Inverted
LVDS
66
GND
Ground
31
GND
Ground
67
LINKEN
Link Enable
32
GND
Ground
68
NC
Not Connected
33
IN 6b
Input #6 Inverted
LVDS
69
NC
Not Connected
34
IN 6a
Input #6 Non-Inverted
LVDS
70
NC
Not Connected
35
GND
Ground
71
NC
Not Connected
36
GND
Ground
72
Vcc
Power Supply Voltage
Notes
LVCMOS input
Notes
1. A bypass capacitor of 10 µF Tantalum and a Π network of two .1µF
MLC to GND with a .5 to 1 µH inductor between the caps are
recommended.
2. LV CMOS output. No external pull-up required.
3. Previously LINKEN–. Now floating.
© Copyright 2001. W. L. Gore & Associates, Inc. All rights reserved.
46
IN 9b
Input #9 Inverted
LVDS
47
IN 9a
Input #9 Non-Inverted
LVDS
48
NC
Not Connected
49
GND
Ground
50
GND
Ground
51
IN 10b
Input #10 Inverted
LVDS
52
IN 10a
Input #10 Non-Inverted
LVDS
53
GND
Ground
54
GND
Ground
55
IN 11b
Input #11 Inverted
LVDS
56
IN 11a
Input #11 Non-Inverted
LVDS
57
GND
Ground
LV CMOS Input,
Leave OPEN
LV CMOS Input,
“H” = Enable
3
3.3 V DC
1