Download CDR`s circuit performance in sensing and recovering

IIUM Engineering Journal, Vol. x, No. x, 200x
THEORETICAL MODELING AND SIMULATION OF
PHASE–LOCKED LOOP (PLL) FOR CLOCK DATA
RECOVERY (CDR)
Z. M. ASHARI AND A.N.NORDIN
Electrical and Computer Engineering Department, Kulliyyah of Engineering, International
Islamic Universoty Malaysia (IIUM), Jalan Gombak, 53100 Kuala Lumpur, Malaysia.
[email protected]
ABSTRACT : Trasmitting and receiving process for large bandwidth data is highly
demanded with the rapid growth of communication technology. Clock data recovery or
known as CDR has become a crucial component for high speed performance to receive
gigahertz data. Due to this reason, this paper deals with the theoretical modeling and
simulation of phase-locked loop (PLL) of CDR. Many critical important features and
challenges that are influence CDR performance such as design approach, architectures,
simulator tools and jitter. This paper presents the effect of jitter in CDR circuit design
based on the PLL approach using Hardware Description Language, Verilog-AMS for
PCIe application.
KEY WORDS: Phase-locked loop (PLL) Jitter, Phase Detector, Low-pass filter, and
Voltage-controlled oscillator.
1. INTRODUCTION
The demand of high bandwidth data with high speed performance in communication
technology is increased such in computer industry. High speed transfer rate between
peripheral components, storage devices and network hubs is needed as the bandwidth
input/output (I/O) data getting larger. As a consequence, jitter, uncompensated clock skew,
and clock interconnect bandwidth are present. In fact, quality of the clock also difficult to
optimize with increased bandwidth demands and high speed transfer rate. Clock
architectures are normally used for synthesis, distribution and recovery of I/O clocks.
Various techniques are introduced with increasing data rates performance namely clock
multiplication, forwarded clock recovery, embedded clock recovery, per-pin deskew, jitter
filtering and duty-cycle error correction [1].
Clock data recovery circuit is frequently used in communication system especially
transceiver. Transceiver performance depends on the capability of a clock data recovery
circuit. Peripheral Component Interconnect Express or written as PCIe is one of the
transceiver families. It is performs two-ways communication. Transmitting and receiving
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process of PCIe has been implemented in the mobile, workstation, server, embedded
computing and communication platforms. PCIe have meets the requirements for high
performance features with the inventions of two different generations PCIe.
First generation of I/O interconnects with initial speed 2.5 Gbps known as PCIe 1.0.
The next generation, PCIe 2.0 is based on PCIe 1.0 principles, but it supports speeds of
5Gbps. Clock data recovery circuit has become one of the building blocks in PCIe
architecture. The ability of CDR to influence PCIe performance at Gigahertz data make it
critical to design. With transfer rate of 5 Gbps, PLL approached are preferably chosen in
[2] and [3].
Theoretical modeling and simulation of high performance of CDR based on the PLL
transfer functions is demonstrated in this work. Modeling of analog mixed-signal
architecture for dedicated CDR circuit using Verilog-AMS HDL is proposed. Six
important sections are presented in this paper. The system architecture of PLL is described
in Section2. Section 3 illustrates building blocks and transfer function of proposed CDR
circuit. Jitter in PLL, simulation and results, discussion, and conclusion are analyzed in
section 4, 5 and 6.
2. PROPOSED CDR ARCHITECTURE
A PD, a low-pass filter, a VCO, a resistor, and a feedback divider are building blocks of
the proposed PLL architecture. The PLL architecture basically consists of analog and
digital blocks as illustrated in Fig. 1. According to Fig. 1, only the phase detector is a
digital, the rest of the blocks are analog. This PLL compares the input signal at PD with
the output signal at the VCO. Each block was modeled accordingly and transfer function
for each block was derived.
Fig. 1:
Circuit design of proposed PLL architecture.
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Phase detector (PD)
Phase detector (PD) is the first block in PLL architecture. It is used to compare the
phases of the incoming data with the phase of the clock generated by the voltage
controlled oscillator (VCO) [4]. The performance of a CDR circuit is determined by the
phase detector. The best phase detector basically should accomplish three essential
functions which are data transition detection, phase difference detection and low spur
noise [5]. Characteristics concern is phase difference between the input phase and the
output phase as well as the phase difference between the input voltage and the output
voltage.
In locked condition, the phase difference between the output phase, out and the input
phase, in should be small and constant. It makes the output angular frequency, ωout equal
to angular frequency of the input, ωin. The voltage of the PD, VPD is sensed by PD based
on the phase difference of both inputs. The VPD is proportional to the phase error in the
PLL system. The value of VPD can be calculated according to the equation (1) below:
VPD  K PD out  in   K PD 
(1)
where KPD is a PD gain and  is a phase error between two inputs. The KPD also can be
determined based on the slope of VPD and . The width of the output pulses at PD varies
if the phase difference of the two inputs is also varied. In order to reduce the phase error in
a PLL system, KPD and KVCO must be large.
RLC Low-Pass Filter
The following block in the PLL system after a phase detector is a loop filter. The RLC
low pass filter with one pole and one zero is frequently used in designing CDR circuit
based on the PLL approach in [5, 6]. The transient response of the loop filter depends on
the magnitude of the pole and zero which is slightly important in designing stable lowpass filter. The number of poles and zeroes in low pass filter verify the type of PLL
system. Fig. 5 shows RLC low pass filter circuit. The circuit design and numerical values
of RLC low pass filter is verified according to the following equations (2) to (4).The
inductor’s impedance, XL, capacitor’s impedance, XC, and total impedance of the loop
filter circuit, Z can be determined as below.
Fig. 2:
Low-pass filter circuit.
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X L  j 2f L
(2)
XC 
1
j 2C
(3)
Z
 X L  X C 2  R 2
(4)
The function of low pass filter is to diminish jitter which is generated from the input of
PD. Jitter exists as the output of the VCO experiences pulses or ripples. The RLC low pass
filter transfer function is identified as below from (5) to (9). Equation (5) shows a second
order transfer function of RLC low pass filter. The equation (6) is the same as the equation
(5) except that the denominator has been organized with a1 =LC and a2=RC so as to make
it clear that the denominator is a quadratic equation. The actual factoring processes for the
gain is based on denominator in (6) with values of s are given by s1 and s2. The quadratic
equation is used to determine the value of s as illustrated in equation (7) and (8). The
resulting transfer function of G(s) =4.6X10-14 was obtained based on the R, L, C values
shown in Fig. 2.
G s  
1
LCs  RCs  1
(5)
G s  
1
a1s  a2 s  1
(6)
2
2
s1  
a1
2 a2

4a 
1  1  22 
a1 

(7)
s2  
a1
2a2

4a 
1  1  22 
a1 

(8)
G s  
1

s 
s
1  1  
 s1  s2 
(9)
VCO
Another part of PLL is a VCO. The major function of VCO is to control voltage input
and to create a frequency proportional to the control voltage. It is also known as frequency
– controlled device [7]. According to [8], the value of VVCO depends on the DC component
of Vcont which extracted from VPD. There are two unknown quantities which need to be
calculated for the VCO to function properly, namely phase error, err and Vcont (control
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voltage) Thus, the VCO and PD characteristics required to make it reliable are derived as
(10) to (13):
out  in  K vcoVcont
(10)
Vout 
err 
out  in
K vco
(11)
Vout out  in

K PD
K PD K vco
GVCO s  
(12)
KVCO
s
(13)
Based on (10), output frequency of the VCO, ωout is depends on ωin (input frequency
signal), KVCO (VCO gain) and Vcont. Vout in (11) is used to find the differences between
input and output frequency signal over the VCO gain. Consequently, err is obtained due
to (1) and (11). The transfer function of the VCO block is demonstrated in (13) which
consist of KVCO . Two important characteristics are recognized after the loop returns to
lock. All parameters such as phase difference, VPD, and VCO frequency remain constant
except for total input and output phases. Otherwise, Vcont from the output low pass filter
can be utilized in analyzing PLL system [8].
3. SIMULATIONS OF JITTER IN PLL
The existence of jitter is normally happens during transmission and receiving process.
This phenomenon is indirectly effects overall system performance in PLL. The
transmission signal or data will experience noise and distortion especially for large
bandwidth data. As a result, transfer rate and speed of a PLL system decreased. Small
changes in period during transmitting and receiving process are actually affects the excess
phase and the total phase of the waveform. In other words, excess phase and total phase
varies as the space in time of the waveform unstable.
In [8], jitter has been categorized into two which are fast jitter and slow jitter. Slow
jitter occurs whenever frequency of a signal varies slowly from one period to the other
whereas fast jitter due to changes in period.
Trend of jitter in PLL can be accumulated into two different parts such as at the PD
input or typically known as the input excess phase (in) and a random component (VCO)
at the VCO. Generally, jitter is generated in PD and finally produced at the VCO output.
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In fact, it also can be purposely injected at PD and VCO circuit to test ability of a system
in sensing distortion signal as demonstrated in Fig. 3 and Fig. 4. SMASH Dolphin
Integration software, Verilog-AMS tools have been used for all the simulation presented in
this section. All the results in based on effect of injected jitter in input PD and VCO.
Jitter at Input PD
CDR’s circuit performance in sensing and recovering distortion signal is tested. Fig. 3
shows that jitter is ideally added at the input of PD. The distortion signal of 50 MHz
become an input of PLL and finally passing trough to PD, loop filter, VCO and divider.
The resulting output 5 GHz waveform (out ) is not effected by the jitter at input  in > 0
as verified in Fig. 5.
Fig. 3:
Fig. 4:
Fig. 5:
Effect of PD jitter.
Input signal of 50 MHz with jitter.
Output waveform of proposed PLL 5 GHz (out ).
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Jitter at VCO
In this part, jitter is injected at the VCO block, ( VCO ) and no jitter at the input PD,
out = 0. Clean output signal is generated after passing trough PD, loop filter and VCO as
illustrated in Fig. 7 and Fig. 8. Distortion signal is obtained at Fig. 9 and Fig. 11 whenever
jitter is added, which means the proposed PLL 5 GHz and the VCO exhibit jitter at the
output. However, the output jitter at VCO still can be removed as obtained in Fig. 10 by
adding divider in PLL circuit design.
Fig. 6:
Fig. 7:
Effect of VCO jitter.
Input signal of 50 MHz without jitter.
Fig. 8:
Waveform signal of VCO.
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Fig. 9:
Waveform signal of VCO with jitter, (VCO ).
Fig. 10:
Feedback waveform of proposed PLL 50 MHz.
Fig. 11:
Output waveform of proposed PLL 5 GHz with jitter (out ).
4. DISCUSSION
In this section, simulation results from Fig. 4 to Fig. 5 and Fig. 7 to Fig. 11 for two
differences injected jitter were discussed. Jitter, (in ) is purposely injected at the input PD
to test CDR circuit performance as shown in Fig. 3. Based on the resulting waveform in
Fig. 5, the proposed PLL model can generate a clean high frequency output a hundred
times larger than the distortion input frequency of 50 MHz. The effective of proposed
CDR building blocks in sensing the presence of jitter also tested with additional jitter at
VCO, (VCO) as shown in Fig. 6. Fig. 9 and Fig. 11 were illustrated that output signal is
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distorted at the output of VCO and proposed PLL design. However, the feedback divider
is able to recover distortions signal generated from the VCO as proven in Fig. 10. This
means that the proposed PLL circuit is capable of handling GHz data and removing jitter
at input PD and VCO as illustrated in Fig. 5 and Fig. 10. Next, RLC low-pass filter is used
to ensure the CDR’s stability. It can generate a stable high frequency sinusoidal signal
based on the DC voltage output from the RLC. The divider block divides the output
frequency produced by the VCO by a factor of N in order to be equal to the input
frequency signal, 50 MHz.
5. CONCLUSION
A simple model of PLL architecture has been demonstrated and transfer function of
several important parts is verified. The proposed design composed of PD, RLC low–pass
filter, VCO, feedback divider and a resistor to stabilize the block system. High frequency
band 5 GHz is applied in this PLL model. Simple PLL system with less jitter has
successfully modeled by testing ability of a system in sensing distortion signal. Thus,
designing a CDR circuit with high speed and low jitter performance is a very challenging
task due to some specifications to be concerned.
ACKNOWLEDGEMENT
This work is funded by the Ministry of Science and Technology’s (MOSTI) Techno
Fund Grant TF0409D100
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