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A Fully Integrated BiCMOS PLL for 60 GHz
Wireless Applications
Wolfgang Winkler, Johannes Borngräber, Bernd Heinemann,
Frank Herzel
IHP, Frankfurt (Oder), Germany
An integrated PLL tunable from 54.5 to 57.8GHz manufactured
in a SiGe:C BiCMOS technology is presented. The PLL is aimed
at wireless transceivers in the unlicensed band from 57 to 64GHz
[1]. Existing 60GHz transceivers are based on compound semiconductors [2]. By contrast, silicon-based solutions will enable a
high integration level at low cost. The known 60GHz systems utilize free-running oscillators for frequency synthesis. These solutions are subject to frequency changes due to device parameter
variations with process and temperature. Our PLL solution
allows a simple stabilization of the frequency. In [3], a 45GHz
PLL manufactured in a SiGe bipolar technology is presented. It
uses a VCO running at half the output frequency in conjunction
with a frequency doubler. By contrast, the proposed PLL avoids a
frequency doubler and uses a fundamental LC oscillator resulting
in a higher output power at a given power consumption.
Furthermore, the BiCMOS implementation allows combining
fast bipolar circuitry with low-power CMOS blocks in order to
achieve a high integration level. The schematic of the fully integrated PLL is presented in Fig. 21.9.1. A VCO with a coarse and
a fine-tuning input is embedded in a PLL with two parallel loops
sharing the frequency divider and the phase-frequency detector
(PFD). This topology allows combining a relatively wide tuning
range with a low noise sensitivity [4]. The coarse tuning loop with
a tuning range of 3GHz has no resistor in the loop filter, but only
a large MIM capacitor to minimize the noise contribution. The
fine-tuning loop contains a standard loop filter for stability. The
fine-tuning range is as low as 600MHz, which minimizes the
noise contribution from the fine-tuning loop.
The PLL is fabricated in a SiGe:C BiCMOS technology with fT/fmax
= 200GHz/200GHz [5]. The chip micrograph of the PLL is presented in Fig. 21.9.2. The chip size is 1000 × 800µm2 including
pads and 700×560µm2 without pads. The VCO is based on a modified Colpitts principle in a symmetric configuration similar to
[6], and is followed by a cascade of ten static dividers. With the
symmetric signal the sensitivity to substrate noise is reduced and
the signal coupling to the symmetric ECL divider circuit [7] is
more effective. Figure 21.9.3 shows the measured coarse tuning
range, which amounts to 3GHz. Another 600MHz tuning range
results from the fine tuning. A VCO frequency around 55GHz will
result in an IF of about 5GHz in a 60GHz heterodyne receiver.
This will allow circuitry developed for 802.11a WLAN to be
reused in an integrated 60GHz WLAN transceiver. The measured
PLL lock range is from 54.5 to 57.8GHz. Figures 21.9.4 and 21.9.5
show the PLL output spectrum with different resolution. The
measurements are performed on wafer using the spectrum analyzer FSEM 30 in conjunction with the harmonic diode mixer FSZ75 for frequency extension to the V-band. To prevent mixer overload, a 20dB wave-guide attenuator is inserted. The reference
spurs are 50dB below the carrier. The circuit operates from a 3V
supply except for the first divide-by-two stage which needs a 4.3V
supply. A signal generator provides a sine-wave reference signal
from 53.2 to 56.5MHz with 100mV amplitude. The total power
consumption amounts to 650mW.
An important issue is the optimization of the loop bandwidth.
The high PLL output frequency results in a large PLL division
factor if a commercial crystal oscillator is used to drive the PLL.
This enhances the jitter contributions of the input signal and the
charge pump, which are low-pass filtered in a PLL making a narrow-band PLL desirable. However, due to the absence of highquality passives in an integrated PLL, the VCO phase noise,
which is high-pass filtered in the PLL, will significantly degrade
the PLL jitter performance. As shown in [8], the corresponding
rms phase error contribution (in radians) can be deduced from
the single-sideband phase noise SSSB [1/Hz] of the free-running
VCO measured at the offset ∆f from the carrier, and the loop
bandwidth fL [Hz] according to
σ φPLL = ∆f
π ⋅ S SSB
Figure 21.9.6 shows the RMS phase error as a function of fL for
two typical VCO phase noise values. Obviously, a relatively large
loop bandwidth will be required for an acceptable phase error,
resulting in a subtle trade-off with the other noise contributions
in the PLL. In conclusion, the PLL bandwidth of 200kHz visible
in Fig. 21.9.5 should be significantly increased in a redesign.
The authors acknowledge the IHP technology team for chip fabrication.
This work was partly funded by the German Federal Ministry of Education
and Research (BMBF) under the project acronym WIGWAM.
[1] W. Winkler et al., “60 GHz Transceiver Circuits in SiGe:C BiCMOS
Technology,” ESSCIRC, pp. 83-86, Sept., 2004.
[2] Y. Shoji, K. Hamaguchi, and H. Ogawa, “Millimeter-Wave Remote SelfHeterodyne System for Extremely Stable and Low-Cost Broad-Band
Signal Transmission,” IEEE Trans. on Microwave Theory and Techniques,
vol. 50, pp. 1458-1467, June, 2002.
[3] G. Ritzberger, J. Böck, and A. Scholtz, “45GHz Highly Integrated
Phase-Locked Loop Frequency Synthesizer in SiGe Bipolar Technology,”
IEEE MTT-S Intl. Microwave Symp., pp. 831-834, June, 2002.
[4] F. Herzel, G. Fischer, and H. Gustat, “An Integrated CMOS RF
Synthesizer for 802.11a Wireless LAN,” IEEE J. Solid-State Circuits, vol.
38, pp. 1767-1770, Oct., 2003.
[5] B. Heinemann et al., “Novel Collector Design for High-Speed SiGe:C
HBTs,’’ IEDM, pp. 775-778, Dec., 2002.
[6] W. Winkler, J. Borngräber, B. Heinemann, and P. Weger, “60GHz and
76GHz Oscillators in 0.25µm SiGe:C BiCMOS,’’ ISSCC Dig. Tech. Papers,
pp. 454-455, Feb., 2003.
[7] W. Winkler et al., “High-performance and Low-Voltage Divider Circuits
Fabricated in SiGe:C HBT Technology,” ESSCIRC, pp. 827-830, Sept.,
[8] F. Herzel, W. Winkler, and J. Borngräber, “An Integrated 10 GHz
Quadrature LC-VCO in SiGe:C BiCMOS Technology for Low-Jitter
Applications,” IEEE CICC, pp. 293-296, Sept., 2003.
• 2005 IEEE International Solid-State Circuits Conference
0-7803-8904-2/05/$20.00 ©2005 IEEE.
ISSCC 2005 / February 9, 2005 / Salon 7 / 12:00 PM
Figure 21.9.1: Circuit schematic of the PLL.
Figure 21.9.2: Chip micrograph of the fully integrated PLL.
Figure 21.9.3: VCO output frequency as a function of coarse tuning voltage.
Figure 21.9.4: Output spectrum of PLL including 20dB external attenuation.
Figure 21.9.5: High-resolution output spectrum around the carrier
including 20dB external attenuation.
Figure 21.9.6: Plot of rms phase error due to VCO noise versus loop
bandwidth fL.