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José Pedro Cardoso
WP5
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WORK PACKAGE LDR
RESEARCHER
Radiation-hard ASIC building blocks for
detector data readout
ACEOLE MID TERM REVIEW CERN 3RD AUGUST 2010
COORDINATOR
Work Package 2
Personal Data
Name: José Pedro Cardoso
Nationality: Portuguese
Age: 36
Education : MSc. in Electrical and Computer Engineering
BSc. In Electronics and Telecommunications Engineering
Joined ACEOLE’s Program: 1st of June 2009
06/07/2010
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Accelerator Concepts
Training and Education
Project
Timeline
References
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The LHC
Source:[1]
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This Project
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Accelerator Concepts
Training and Education
Project
Timeline
References
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Education - PhD in Electrical and Computer Engineering
Title: Design of Low-Noise and Radiation Tolerant Readout Systems
1st semester (2009/2010)
 Microelectronic and Micro-electro-Mechanical Technologies
 Test and Design for Testability
 Digital Communication Systems
 Seminars
Projects:
 Design of a low-phase noise VCXO running at 80 MHz
 Design of a jitter measurement circuit, based on a new Vernier Delay Line
 Mem’s Based Oscillator
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Training
 On- job Training
 Phase Locked Loops
 Noise theory
 Cadence and MatLab
 Courses
 2 day course – “Leaders in Science”

Team work

Self-Confidence

Establish better personal and work connections between ACEOLEs.
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Accelerator Concepts
Training and Education
Project
Timeline
References
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Proposed Solution
 Circuit is divided as follows:




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PLL, BIST, Control and Fuse Banks.
PLL is capable of Lock Detection
and Automatic Oscillation
Amplitude Control
Built-in Self Test is capable of:
 Calibration (on-line and off-line)
 Frequency Offset Measurement
 Jitter Measurement
Control block is able of controlling
every action on the circuit and
interact with the user
Fuse bank acts as a PROM/RAM
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Phase Locked Loop
v/2
θ1
PFD
LF
VCO
θ2
θ2'
:N
θ1
PFD
LF
VCO
θ2
θ2'
:N
Phase Locked Loop (PLL)
Stand-alone operation
 Measures the difference input phase
• The circuit should be low noise and
of two signals
 Based on, mainly, in the following
blocks: Phase Detector, Loop Filter,
Voltage-Controlled Oscillator
 Frequency Divider – N-Integer PLL
with a dividing factor of 2
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insensitive to Process-VoltageTemperature (PVT).
• A voltage is applied to the VCXO in
order to generate the central frequency
• The output frequency will be 80 MHZ
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Jitter Measurement Circuit
 Vernier Delay Line: is based on the
delay line method. Time resolution is
determined by a logic buffer delay.
 Two delay buffer chains are used: buffer’s
Source:[2]
delay in the upper chain is slightly higher than
buffer’s delay in the lower delay chain, thus
sub-gate timings can be achieved.
 Drawbacks: VDL has N stages and 2N delays,
it makes this structure quite dependent on the
technology used, resolution one gate delay
and is area inefficient.
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Source:[2]
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Jitter Measurement Circuit
Modified Vernier Delay Line features:
 one counter instead of N counters
 in order to get the CDF, the
 simulation must be done N times.
Source:[2]
Advantages:
 Avoids a large waist of silicon area since only one counter is used.
Disadvantages
 fabrication’s process dependent, because gate delays are PVT sensitive.
 Large measurement uncertainty
Solution
 Replace all the delays by a single delay in each path, the circuit will be
almost independent of the technology.
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Jitter Measurement Circuit
Component-Invariant VDL [2]
 Uses inverters to cause the delay
between data and clock, and then its
output is fed back to the input.
Source:[2]
 The oscillators will run with a period of 2τs or 2τf.
 Each inverter will delay the leading edge of the data signal in respect
to clock signal by an amount of 2Δτ seconds. To measure accurately
timing the circuit should be able to detect rising edges of data/clock.
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Other Blocks (not developed yet)
 Calibration
 PLL mode - the auto calibration feature allows centring of the VCXO tuning
range relating to the reference clock frequency.
 Oscillator mode - the auto calibration logic can be used to quickly choose the
VCXO parameters that have to be programmed in the Fuse-Bank to tune the
oscillation frequency.
 Frequency Offset Measurement
 Measures the offset between the central frequency and a reference
 Fuse Bank
 Fuses the default configuration of the PLL, after calibration.
 Uses a dynamic memory to operate in modes demanded by the user
 Control Interface
 Controls all the circuit operation and interfaces with the user with a 8-bit bus.
 AOAC
 The amount of power must be chosen according to decrease phase-noise, and
not excite other resonant modes of the crystal, rather than the sheering of the
crystal.
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Accelerator Concepts
Training and Education
Project
Timeline
References
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Timeline
May 2010 - January 2011
 Design of a Phase Locked Loop with Built-In and Self test capabilities.
 The design should focus on a very low phase-noise circuit.
 Tape-out of the circuit
Feb 2011 - Mar 2011
 Design and setup of the test session (pcb design, tester software, radiation
lab setup)
 Test of the circuit
Apr 2011 - July 2011
 Doctoral Programme Second Semester.
 Write an article to target conferences
Sep 2011 - Jun 2012
 Development of a 10 GHz VCO
 Attend to targeted conferences
Jun 2012 - Sep 2012
 Dissertation’s writing.
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References
[1] - https://espace.cern.ch/GBT-Project/default.aspx
[2] - Chan, A. & Roberts, G. (2002), 'A deep sub-micron timing
measurement circuit using a single-stage Vernier delay line''Custom
integrated circuits conference', 77--80.
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Thank you for your attention
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Backup Slides
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Functional Diagram
PLL
Generate
Reference Clock
BIST
Recover the
Input Signal
Test and
calibrate the
Circuit
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Adjust the
circuit’s
parameters
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The Problem
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Main Project
GBTX
 The GBTX is a radiation tolerant chip that can be used to implement
bidirectional multipurpose optical links for high-energy physics
experiments. The target applications are: data readout, trigger, timing,
fast/slow control and monitoring links [1].
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PLL specifications
 Crystal frequency = 80.1572 MHz
 Locking range = 40.0786 MHz ± 8 kHz
 Output Jitter < 7 ps
 130 nm CMOS Technology
 One frequency multiplication mode: × 2
 Power voltage: 1.5 V
 10 GHz VCO for High-Speed Transceiver
 Very low-phase noise characteristics
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Stand-Alone VCXO
Stand-alone operation
 Only VXCO is working
 The circuit should
 low noise
v/2
θ1
PFD
LF
VCO
θ2
θ2'
:N
 insensitive to Process-Voltage-
Temperature (PVT).
 A voltage is applied to the
VCXO in order to generate the
central frequency
 The output frequency will be 80
MHZ
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Jitter Measurement Circuit
 After each flip-flop either data
leads the clock signal or lags the
clock signal.
 When the data lags the clock the
flip-flop latches to a logic level
Source:[2]
‘0’, thus counter will not count.
 Disadvantage: resolution
depends on τ, and finally on
technology. This circuit can only
measure timing till a gate delay.
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Source:[2]
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