Chap13
... partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction. ...
... partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction. ...
AD7888 数据手册DataSheet下载
... the AD7888 and also frames the serial data transfer. Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888. Alternatively, the internal reference can be disabled and an external reference applied to this input. The voltage range for the external refere ...
... the AD7888 and also frames the serial data transfer. Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888. Alternatively, the internal reference can be disabled and an external reference applied to this input. The voltage range for the external refere ...
FMS6364A Four-Channel Standard
... TVs, and DVD players are at +70ºC; consideration must be given to providing an adequate heat sink for the device package for maximum heat dissipation. When designing a system board, determine how much power each device dissipates. Ensure that devices of high power are not placed in the same location ...
... TVs, and DVD players are at +70ºC; consideration must be given to providing an adequate heat sink for the device package for maximum heat dissipation. When designing a system board, determine how much power each device dissipates. Ensure that devices of high power are not placed in the same location ...
Quadruple Differential Line Driver (Rev. G)
... The AM26LS31 is a quadruple complementary-output line driver designed to meet the requirements of ANSI TIA/EIA-422-B and ITU (formerly CCITT) Recommendation V.11. The 3-state outputs have high-current capability for driving balanced lines such as twisted-pair or parallel-wire transmission lines, and ...
... The AM26LS31 is a quadruple complementary-output line driver designed to meet the requirements of ANSI TIA/EIA-422-B and ITU (formerly CCITT) Recommendation V.11. The 3-state outputs have high-current capability for driving balanced lines such as twisted-pair or parallel-wire transmission lines, and ...
MAX5544 Low-Cost, +5V, Serial-Input, Voltage-Output, 14-Bit DAC General Description
... than 1LSB differential linearity error. Serial-data transfer minimizes the number of package pins required. The MAX5544 is composed of two matched DAC sections, with a 12-bit inverted R-2R DAC forming the 12LSBs and the 4MSBs derived from 15 identically matched resistors. This architecture allows th ...
... than 1LSB differential linearity error. Serial-data transfer minimizes the number of package pins required. The MAX5544 is composed of two matched DAC sections, with a 12-bit inverted R-2R DAC forming the 12LSBs and the 4MSBs derived from 15 identically matched resistors. This architecture allows th ...
Digital Outputs (7
... Each one of the seven LEDs in the display is given a positional segment which is controlled by one pin. These LED pins are labeled a, b, c, d, e, f, and g representing each individual LED. The other LED pins are connected together and wired to form a common pin. By forward biasing the appropriate pi ...
... Each one of the seven LEDs in the display is given a positional segment which is controlled by one pin. These LED pins are labeled a, b, c, d, e, f, and g representing each individual LED. The other LED pins are connected together and wired to form a common pin. By forward biasing the appropriate pi ...
AD7667 数据手册DataSheet下载
... When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that ...
... When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that ...
UC2834 数据资料 dataSheet 下载
... The crowbar output on the UC1834 is activated following a sustained over-voltage condition. The crowbar output remains high as long as the fault condition persists, or, as long as the over-voltage latch is set. The latch is set with an over-voltage fault if the voltage at Pin 15 is above the latch r ...
... The crowbar output on the UC1834 is activated following a sustained over-voltage condition. The crowbar output remains high as long as the fault condition persists, or, as long as the over-voltage latch is set. The latch is set with an over-voltage fault if the voltage at Pin 15 is above the latch r ...
4100 ELECTRIC STRIKE
... completely closed position in order to avoid the lock latch from applying pressure against the releasing latch portion of the electric strike. 3. Electrical wire connections must be completed and ready to be terminated inside the frame. 4. Confirm that the power line in the frame is the correct volt ...
... completely closed position in order to avoid the lock latch from applying pressure against the releasing latch portion of the electric strike. 3. Electrical wire connections must be completed and ready to be terminated inside the frame. 4. Confirm that the power line in the frame is the correct volt ...
USB1T11A — Universal Serial Bus Transceiver U S B
... The USB1T11A is a one-chip, generic USB transceiver. It is designed to allow 5.0V or 3.3V programmable and standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of transmitting and receiving serial data at both full-speed (12Mbit/s) and low-speed (1.5Mbit/s) ...
... The USB1T11A is a one-chip, generic USB transceiver. It is designed to allow 5.0V or 3.3V programmable and standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of transmitting and receiving serial data at both full-speed (12Mbit/s) and low-speed (1.5Mbit/s) ...
Abstract: This paper introduces a generalized method for simulating
... Fig.2 Block Diagram of Operational Amplifier ...
... Fig.2 Block Diagram of Operational Amplifier ...
Nov 2000 Infinite Sample-and-Hold Outperforms Many Legacy Sample-and-Hold Amplifiers
... several LSB, the filtering effects following the DAC and the use of a higher resolution ADC for resampling can reveal details below the quantization floor of the original ADC and DAC. The integral linearity is limited by the infinite sample-and-hold, but resolution can be greater. If a recurring wav ...
... several LSB, the filtering effects following the DAC and the use of a higher resolution ADC for resampling can reveal details below the quantization floor of the original ADC and DAC. The integral linearity is limited by the infinite sample-and-hold, but resolution can be greater. If a recurring wav ...
TESND300 - DC/DC Converters with wide input voltage range
... 1 - «TESND» Series 2 - Output power in the standard version, W ...
... 1 - «TESND» Series 2 - Output power in the standard version, W ...
by Tony van Roon © by Tony van Roon The 555 timer
... double triggering due to this effect. The voltage range that can safely be applied to the trigger pin is between V+ and ground. A dc current, termed the trigger current, must also flow from this terminal into the external circuit. This current is typically 500nA (nano-amp) and will define the upper ...
... double triggering due to this effect. The voltage range that can safely be applied to the trigger pin is between V+ and ground. A dc current, termed the trigger current, must also flow from this terminal into the external circuit. This current is typically 500nA (nano-amp) and will define the upper ...
AD723 数据手册DataSheet下载
... reconstructing the luma signal. The 8FSC oversampling of this delay line limits the amount of jitter in the reconstructed sync output. The clocks driving the delay line are reset once per video line during the burst flag. The output of the luma path will remain unchanged during this period and will ...
... reconstructing the luma signal. The 8FSC oversampling of this delay line limits the amount of jitter in the reconstructed sync output. The clocks driving the delay line are reset once per video line during the burst flag. The output of the luma path will remain unchanged during this period and will ...
Control of G4JNT AD9850 Direct Digital Synthesizer module
... There is one wire link that needs to be installed on the board. This is the input to the internal comparator, Pin 16, on the AD9850 that is used to generate a square wave output from the filtered sine wave. If this function is wanted, connect a thin insulated wire from the pad adjacent to pin 16 to ...
... There is one wire link that needs to be installed on the board. This is the input to the internal comparator, Pin 16, on the AD9850 that is used to generate a square wave output from the filtered sine wave. If this function is wanted, connect a thin insulated wire from the pad adjacent to pin 16 to ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.