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DATA  SHEET UDA1334ATS Low power audio DAC with PLL
DATA SHEET UDA1334ATS Low power audio DAC with PLL

... high signal-to-noise performance and low clock jitter sensitivity is achieved. No post filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. ...
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The Q TEST 6000 is an extremely versatile instrument for testing
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... The VSP3010 is a complete, three-channel image signal processor for Charge Coupled Device (CCD) or Contact Image Sensor (CIS) systems. Each channel contains sensor signal sampling, Black Level adjustment and a programmable gain amplifier. The three inputs are multiplexed into a high speed, 12-bit an ...
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On-chip phase noise measurement, design study in 65 nm CMOS technology
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an358 optimizing low-power operation of the c8051f9xx
an358 optimizing low-power operation of the c8051f9xx

... The C8051F9xx family of MCUs support five power modes: Normal, Idle, Stop, Suspend and Sleep. A summary of the power modes can be found in Table 1. Detailed descriptions of each mode can be found in the Power Management chapter of the device data sheet. Normal and Idle modes are classified as Active ...
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AN1983 - SP-Elektroniikka

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... CMOS Input Control for Output 1 to Output 0. (0: LVDS, 1: CMOS.) CMOS Input Control for Output 5 to Output 2. (0: LVDS, 1: CMOS.) CMOS Input for Sleep Mode. (0: normal operation, 1: sleep.) Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B. True Side of Differential LVD ...
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... A scanning display controller circuit can be used to show a four-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession, at an update rate that is faster than the human eye can detect. Each digit is i ...
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mt8870,dtmf decoder.pdf

... registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considere ...
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... In Figure 8 the voltage drop across the input capacitor (taking into account the S/H circuit simplifications and all component tolerances) is big but does not cause any error in the digital output of the ADC. The digital result for the second channel measured by FreeMASTER is 4087. A common mistake ...
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Time-to-digital converter



In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.
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