Introduction
... two wires both “1” - make another be “1” (AND) at least one of two wires “1” - make another be “1” (OR) a wire “1” - then make another be “0” (NOT) Memory devices (store) ...
... two wires both “1” - make another be “1” (AND) at least one of two wires “1” - make another be “1” (OR) a wire “1” - then make another be “0” (NOT) Memory devices (store) ...
ADS7843 数据资料 dataSheet 下载
... The ADS7843 is a 12-bit sampling Analog-to-Digital Converter (ADC) with a synchronous serial interface and low onresistance switches for driving touch screens. Typical power dissipation is 750µW at a 125kHz throughput rate and a +2.7V supply. The reference voltage (VREF) can be varied between 1V and ...
... The ADS7843 is a 12-bit sampling Analog-to-Digital Converter (ADC) with a synchronous serial interface and low onresistance switches for driving touch screens. Typical power dissipation is 750µW at a 125kHz throughput rate and a +2.7V supply. The reference voltage (VREF) can be varied between 1V and ...
VSP2590 数据资料 dataSheet 下载
... Register update timing is synchronized with the falling edge of UPDATE_REG. Continuous Writing Continuous write mode is used when transmitting a large set of data. Receiving data initiates at the falling edge of SLOAD and continues while SLOAD is low. It is only necessary to transmit the starting ad ...
... Register update timing is synchronized with the falling edge of UPDATE_REG. Continuous Writing Continuous write mode is used when transmitting a large set of data. Receiving data initiates at the falling edge of SLOAD and continues while SLOAD is low. It is only necessary to transmit the starting ad ...
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)
... for positive and negative going input signals. The driving force behind the rapid growth of the VLSI technology has been the constant reduction of the feature size of VLSI devices. The feature size decrease from about 2mm in 1985 to 0.35- 0.5mm today (1996). Such continual miniaturization of VLSI de ...
... for positive and negative going input signals. The driving force behind the rapid growth of the VLSI technology has been the constant reduction of the feature size of VLSI devices. The feature size decrease from about 2mm in 1985 to 0.35- 0.5mm today (1996). Such continual miniaturization of VLSI de ...
Datasheet - Intersil
... of the output duty cycle as a function of the voltage at terminal 9 are shown in Figure 7. To synchronize two or more CAl524’s, one must be designated as master, with RT CT set for the correct period. Each of the remaining units (slaves) must have a CT of 1/2 the value used in the master and approxi ...
... of the output duty cycle as a function of the voltage at terminal 9 are shown in Figure 7. To synchronize two or more CAl524’s, one must be designated as master, with RT CT set for the correct period. Each of the remaining units (slaves) must have a CT of 1/2 the value used in the master and approxi ...
MAX1198 Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC General Description
... An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. The MAX1198 features p ...
... An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. The MAX1198 features p ...
差分放大器系列AD8324 数据手册DataSheet 下载
... Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch ( ...
... Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch ( ...
Using Clock Jitter Analysis to Reduce BER in Serial Data Applications
... is multiplied up in the transmitter which uses the result to define the timing of logic transitions in the serial data stream. The character of the reference clock is included in the data transmitted. At the receiver, two different things can happen. If the reference clock is not distributed, then t ...
... is multiplied up in the transmitter which uses the result to define the timing of logic transitions in the serial data stream. The character of the reference clock is included in the data transmitted. At the receiver, two different things can happen. If the reference clock is not distributed, then t ...
CoolRunner-II Automotive CPLD Product Family
... traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The Function Blocks use a Programmable Logic Array (PLA) configuration which allows all product terms to be routed and shared amon ...
... traditional CPLD architecture combining macrocells into Function Blocks (FBs) interconnected with a global routing matrix, the Xilinx Advanced Interconnect Matrix (AIM). The Function Blocks use a Programmable Logic Array (PLA) configuration which allows all product terms to be routed and shared amon ...
Problem 1 – Inverter Sizing
... voltage in 90nm? Assuming 80mV/dec subthreshold slope, what would be the leakage power of the new processor? ...
... voltage in 90nm? Assuming 80mV/dec subthreshold slope, what would be the leakage power of the new processor? ...
lect23-io
... Example A 4-layer PCB contains power and ground planes on the inner layers and signals on the outer layers. The board uses 1 oz copper (1.4 mils thick) and the FR4 dielectric is 8.7 mils thick. How wide should the traces be to achieve 50 characteristic ...
... Example A 4-layer PCB contains power and ground planes on the inner layers and signals on the outer layers. The board uses 1 oz copper (1.4 mils thick) and the FR4 dielectric is 8.7 mils thick. How wide should the traces be to achieve 50 characteristic ...
MAX1875/MAX1876 Dual 180° Out-of-Phase PWM Step- Down Controllers with POR General Description
... ranging from 4.75V to 23V. Each output is adjustable from sub-1V to 18V and supports loads of 10A or higher. Input voltage ripple and total RMS input ripple current are reduced by synchronized 180° out-of-phase operation. The switching frequency is adjustable from 100kHz to 600kHz with an external r ...
... ranging from 4.75V to 23V. Each output is adjustable from sub-1V to 18V and supports loads of 10A or higher. Input voltage ripple and total RMS input ripple current are reduced by synchronized 180° out-of-phase operation. The switching frequency is adjustable from 100kHz to 600kHz with an external r ...
AD7810 数据手册DataSheet下载
... As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. ...
... As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. ...
Monolithic Active Pixel Detectors
... •low noise due to small gate capacitance (few fF) – theoretically few e - few 10 e •signal processing (1st and 2nd stage amplification) in each individual pixel is possible -> good S/N at high speed •homogeneity of charge collection >97% •pixel sizes of order (25x25 m2) – could be limited by integr ...
... •low noise due to small gate capacitance (few fF) – theoretically few e - few 10 e •signal processing (1st and 2nd stage amplification) in each individual pixel is possible -> good S/N at high speed •homogeneity of charge collection >97% •pixel sizes of order (25x25 m2) – could be limited by integr ...
LTC6909 - 1 to 8 Output, Multiphase Silicon
... minor frequency inaccuracies due to supply bounce at high frequencies. When any output pin is not in use, it is in a floating, high impedance state. The outputs are also held in a high impedance state during start-up. After the ...
... minor frequency inaccuracies due to supply bounce at high frequencies. When any output pin is not in use, it is in a floating, high impedance state. The outputs are also held in a high impedance state during start-up. After the ...
ADuM1100 数据手册DataSheet下载
... Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM1100 operates with a voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compati ...
... Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM1100 operates with a voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compati ...
ADS1252 数据资料 dataSheet 下载
... rate, scales directly with the system CLK frequency, this allows the data output rate to be changed over a very wide range (five orders of magnitude) by changing the system CLK frequency. However, it is important to note that the –3dB point of the filter is 0.216 times the data output rate, so the d ...
... rate, scales directly with the system CLK frequency, this allows the data output rate to be changed over a very wide range (five orders of magnitude) by changing the system CLK frequency. However, it is important to note that the –3dB point of the filter is 0.216 times the data output rate, so the d ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.