Digilent Pmod™ Interface Specification
... Pmod connections are made using standard 100mil spaced, 25mil square, pin-header style connectors. The peripheral module board will have a male connector. This will typically be a right angle connector, at the board edge, for direct connection to a host board, This can be a straight male connector i ...
... Pmod connections are made using standard 100mil spaced, 25mil square, pin-header style connectors. The peripheral module board will have a male connector. This will typically be a right angle connector, at the board edge, for direct connection to a host board, This can be a straight male connector i ...
AT91SAM7SE256 数据手册DataSheet 下载
... The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM7SE Series syst ...
... The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM7SE Series syst ...
CC2400DK User Manual
... The MCU is also connected to four LEDs, a joystick and an extra button for user interface purposes. The different examples use these peripherals differently. An analogue temperature sensor, a potentiometer and 32 kB of external RAM are also included. An ISP and a JTAG ICE connector are provided for ...
... The MCU is also connected to four LEDs, a joystick and an extra button for user interface purposes. The different examples use these peripherals differently. An analogue temperature sensor, a potentiometer and 32 kB of external RAM are also included. An ISP and a JTAG ICE connector are provided for ...
Mid Semester Presentation - High Speed Digital Systems Lab
... representation of an analog signal at an instant in time. In practice, analog signals continuously vary over time and an ADC takes periodic “samples” of the signal at a predefined rate. These samples are transferred to a computer over a computer bus where the original signal is reconstructed from th ...
... representation of an analog signal at an instant in time. In practice, analog signals continuously vary over time and an ADC takes periodic “samples” of the signal at a predefined rate. These samples are transferred to a computer over a computer bus where the original signal is reconstructed from th ...
MOD-IO - Olimex
... The part of the example software that was written by Olimex is released under GPL. If there are parts of the software belonging to other developers or companies they maintain their respective rights of the code. It is possible that the pictures in this manual differ from the latest revision of the b ...
... The part of the example software that was written by Olimex is released under GPL. If there are parts of the software belonging to other developers or companies they maintain their respective rights of the code. It is possible that the pictures in this manual differ from the latest revision of the b ...
CoolRunner-II Automotive CPLD Product Family
... combinatorial or registered, with the storage element operating selectably as a D or T flip-flop, or transparent latch. ...
... combinatorial or registered, with the storage element operating selectably as a D or T flip-flop, or transparent latch. ...
Methods for Memory Testing
... The hasic rationale of testing is to check whether the device under lest (OUT) including chips, printed circuil boards (PCB), and system can produce expected results when known inputs or "input stimuli" arc applied. In general, a simple lest program will produce results like "pass" or "fail," while ...
... The hasic rationale of testing is to check whether the device under lest (OUT) including chips, printed circuil boards (PCB), and system can produce expected results when known inputs or "input stimuli" arc applied. In general, a simple lest program will produce results like "pass" or "fail," while ...
Evaluates: SPI and SMBus/I Maxim MINIQUSB User Guide General Description Features
... companion EV kit board. Attainable throughput is limited by your PC and its software. The SMBus/I2C bus runs in bursts at rated speed, but there is some variable dead time between transfers, due to communications overhead. Properly written PC software can minimize this dead time but cannot completel ...
... companion EV kit board. Attainable throughput is limited by your PC and its software. The SMBus/I2C bus runs in bursts at rated speed, but there is some variable dead time between transfers, due to communications overhead. Properly written PC software can minimize this dead time but cannot completel ...
Watchdog Timer
... – The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 225 for details. ...
... – The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-scan” on page 225 for details. ...
Reference Manual
... has been successfully configured. Before starting the programming sequence, Adept ensures that any selected configuration file contains the correct FPGA ID code – this prevents incorrect .bit files from being sent to the FPGA. In addition to the navigation bar and browse and program buttons, the Con ...
... has been successfully configured. Before starting the programming sequence, Adept ensures that any selected configuration file contains the correct FPGA ID code – this prevents incorrect .bit files from being sent to the FPGA. In addition to the navigation bar and browse and program buttons, the Con ...
Virtex-5 LX FPGA Prototype Platform www.BDTIC.com/XILINX User Guide
... REG|JACK. Placement of jumpers on these headers enables delivery of all power from the onboard regulators. Removing all jumpers allows the user to provide power from the three power supply jacks marked VCCINT (J33), VCCO (J31), and VCCAUX (J30). Note: If using an external bench top power supply, 5V ...
... REG|JACK. Placement of jumpers on these headers enables delivery of all power from the onboard regulators. Removing all jumpers allows the user to provide power from the three power supply jacks marked VCCINT (J33), VCCO (J31), and VCCAUX (J30). Note: If using an external bench top power supply, 5V ...
MAXQ615 16-Bit MAXQ Microcontroller with Hardware Multiplier General Description
... Note 3: The power-fail reset and POR detectors operate in tandem so one or both of these signals is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is achieved. Note 4: Measured on the VDD pin and the part not in reset. All inputs ...
... Note 3: The power-fail reset and POR detectors operate in tandem so one or both of these signals is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is achieved. Note 4: Measured on the VDD pin and the part not in reset. All inputs ...
Imote2 Hardware Reference Manual
... recharge the batteries. The battery board should drive the nCHARGE_EN pin low to connect the USB input to the PMIC charger pin, hence allowing to recharge the battery using USB. The PMIC supports single cell Li-Ion at 4.1 and 4.2 V, in addition to a Li-Polymer pack. See the figure below for more det ...
... recharge the batteries. The battery board should drive the nCHARGE_EN pin low to connect the USB input to the PMIC charger pin, hence allowing to recharge the battery using USB. The PMIC supports single cell Li-Ion at 4.1 and 4.2 V, in addition to a Li-Polymer pack. See the figure below for more det ...
AT91SAM7X512
... The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on the 32-bit ARM® RISC processor. It features 512/256/128 Kbytes of high-speed Flash and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, and a CAN controller. A complete set of syste ...
... The Atmel SAM7X512/256/128 is a highly-integrated Flash microcontroller based on the 32-bit ARM® RISC processor. It features 512/256/128 Kbytes of high-speed Flash and 128/64/32 Kbytes of SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, and a CAN controller. A complete set of syste ...
Datasheet
... The PES32H8G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES32H8G2 can operate either as a store and forward or cut-through switch. ...
... The PES32H8G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES32H8G2 can operate either as a store and forward or cut-through switch. ...
LPC1768 Short Slides ece362_lpc1768
... consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. If a peripheral control bit is 1, ...
... consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. If a peripheral control bit is 1, ...
Reference Manual
... The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs). Bi ...
... The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs). Bi ...
ML405 User Guide
... 2. Use of DCI disables user control of the DDR_CS_N and DDR_CKE signals. 3. This disables the use of two I/O pins on the expansion connector J5 (pin 38 and 40). ...
... 2. Use of DCI disables user control of the DDR_CS_N and DDR_CKE signals. 3. This disables the use of two I/O pins on the expansion connector J5 (pin 38 and 40). ...
AT91SAM9G20 Summary - Technologic Systems
... The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The AT91SAM9G20 is architectured on a 6-layer matrix ...
... The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The AT91SAM9G20 is architectured on a 6-layer matrix ...
AT91SAM9G20 英文数据手册DataSheet 下载
... The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The AT91SAM9G20 is architectured on a 6-layer matrix ...
... The AT91SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The AT91SAM9G20 is architectured on a 6-layer matrix ...
Presentation by Ahmed Al-wattar (March 3rd 2010)
... Why disable pull-up resistors during configuration? ◦ In hot-swap or hot-insertion applications, the pull-up resistors provide a potential current path to the I/O power rail ◦ Turning off the pull-up resistors disables this potential path ◦ However, external pull-up or pull-down resistors are then r ...
... Why disable pull-up resistors during configuration? ◦ In hot-swap or hot-insertion applications, the pull-up resistors provide a potential current path to the I/O power rail ◦ Turning off the pull-up resistors disables this potential path ◦ However, external pull-up or pull-down resistors are then r ...
UG184: EFR32 Flex Gecko 2400/434 MHz Wireless
... mode is set to "Debug IN", this connector allows an external debug emulator to be used with the radio board EFR32. When set to "Debug OUT", this connector allows the kit to be used as a debugger towards an external target. When set to "Debug MCU" (default), this connector is isolated from the debug ...
... mode is set to "Debug IN", this connector allows an external debug emulator to be used with the radio board EFR32. When set to "Debug OUT", this connector allows the kit to be used as a debugger towards an external target. When set to "Debug MCU" (default), this connector is isolated from the debug ...
9.3 System Overview
... Temperature either in Readout and Trigger electronics or outside chamber minicrate is measured using dedicated chips (DS1820 from Dallas Semiconductor) with single wire interface. For external temperature measurements a large number of chips can be connected to the Control Board temperature connecto ...
... Temperature either in Readout and Trigger electronics or outside chamber minicrate is measured using dedicated chips (DS1820 from Dallas Semiconductor) with single wire interface. For external temperature measurements a large number of chips can be connected to the Control Board temperature connecto ...
Atmel AVR042: AVR Hardware Design Considerations 8-bit Atmel
... devices will all respond to the ISP instructions if special design considerations are not made. If it is desired to have only one ISP interface on the target board, the ISP programming can be designed so that only one of the AVR devices is provided with a SPI clock at a time. All other SPI lines can ...
... devices will all respond to the ISP instructions if special design considerations are not made. If it is desired to have only one ISP interface on the target board, the ISP programming can be designed so that only one of the AVR devices is provided with a SPI clock at a time. All other SPI lines can ...