Download J-FET (Junction Field Effect Transistor)

Types of Field-Effect Transistors
MOSFET (Metal-Oxide Semiconductor Field-Effect
Transistor)
Primary component in high-density VLSI chips such as
memories and microprocessors
JFET (Junction Field-Effect Transistor)
Finds application especially in analog and RF circuit design
J-FET (Junction Field Effect Transistor)
Introduction
The field-effect transistor (FET) controls
the current between two points but does
so differently than the bipolar
transistor. The FET operates by the
effects of an electric field on the flow of
electrons through a single type of
semiconductor material. This is why the
FET is sometimes called a unipolar
transistor.
J-FET (Junction Field Effect Transistor)
Introduction…cont
Current moves within the FET in a channel, from
the source (S) connection to the drain (D)
connection. A gate (G) terminal generates an
electric field that controls the current .
The channel is made of either N-type or P-type
semiconductor material; an FET is specified as
either an N-channel or P-channel device
Majority carriers flow from source to drain.
In N-channel devices, electrons flow so the drain
potential must be higher than that of the Source
(VDS > O)- In P-channel devices, the flow of
holes requires that VDS < 0
JFET Construction
A schematic representation of an n
channel JFET is shown in Figure 118.
An n-type channel is formed between
two p-type layers which are connected
to the gate. Majority carrier electrons
flow from the source and exit the drain,
forming the drain current. The pn
junction is reverse biased during
normal operation, and this widens the
depletion layers which extend into the n
channel only (since the doping of the p
regions is much larger than that of the
n channel). As the depletion layers
widen, the channel narrows, restricting
current flow.
J-FET (Junction Field Effect Transistor)
Introduction…contd.
The behavior of a JFET can be
described in terms of a set of
Characteristic Curves shown here. In
the region shown with a green
background the drain-source voltage is
small and the channel behaves like a
fairly ordinary conductor. In this region
the current varies roughly in proportion
to the drain-source voltage as if the
JFET obeys Ohm's law. However, as
we increase the drain-source voltage
and move into the region with a light
background we increase the drainchannel voltage so much that we start
to ‘squeeze down’ the channel.
Gate Voltage control S-D currents
J-FET (Junction Field Effect Transistor)
Hence a large increase in drain-source:



‘pulls
harder’, trying to drag the electrons
more quickly from source to drain.
‘squeezes down’ the channel making it harder
for the electrons to get through.
These effects tend to cancel out, leaving the
current the same at all high drain-source
voltage.
The MOS Transistor
Polysilicon
Aluminum
The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND - electrons
are the majority carriers
Gate oxide
Polysilicon
W
Gate
Source
Drain
n+
n+
L
p substrate
Field-Oxide
(SiO2)
p+ stopper
Bulk (Body)
p areas have been doped with acceptor
ions (boron) of concentration NA - holes
are the majority carriers
MOS Capacitor Structure



First electrode - Gate :
Consists of low-resistivity
material such as highly-doped
polycrystalline silicon,
aluminum or tungsten
Second electrode Substrate or Body: n- or ptype semiconductor
Dielectric - Silicon dioxide:
stable high-quality electrical
insulator between gate and
substrate.
Substrate Conditions for Different
Biases
Accumulation
VG << VTN
Depletion
VG < VTN
Inversion
VG > VTN
Low-frequency C-V Characteristics for MOS Capacitor
on P-type Substrate



MOS capacitance is nonlinear function of voltage.
Total capacitance in any
region dictated by the
separation between
capacitor plates.
Total capacitance modeled
as series combination of
fixed oxide capacitance
and voltage-dependent
depletion layer
capacitance.
NMOS Transistor: Structure




4 device terminals:
Gate(G), Drain(D),
Source(S) and Body(B).
Source and drain regions
form pn junctions with
substrate.
vSB, vDS and vGS always
positive during normal
operation.
vSB must always reverse
bias the pn junctions
The Threshold Voltage
VT = VT0 + (|-2F + VSB| - |-2F|)
where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
– Difference in work-function between gate and substrate
material, oxide thickness, Fermi voltage, charge of impurities
trapped at the surface, dosage of implanted ions, etc.
VSB is the source-bulk voltage
F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is
the thermal voltage; NA is the acceptor ion concentration; ni 
1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure
silicon)
 = (2qsiNA)/Cox is the body-effect coefficient (impact of changes in
VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox
is the gate oxide capacitance with ox=3.5x10-11F/m)
The Body Effect
0.9
0.85
VSB is the substrate
bias voltage (normally
positive for n-channel
devices with the body
tied to ground)
l
0.8
0.75
0.7
0.65
0.6
0.55
A negative bias
causes VT to increase
from 0.45V to 0.85V
l
0.5
0.45
0.4
-2.5
-2
-1.5
VBS (V)
-1
-0.5
0
NMOS Transistor: Triode Region Characteristics
Concept of Asymmetric Channel
• It is to be noted that the VDS measured relative to the source
increases from 0 to VDS as we travel along the channel from
source to drain. This is because the voltage between the gate
and points along the channel decreases from VGS at the source
end to VGS-VDS.
• When VDS is increased to the value that reduces the voltage
between the gate and channel at the drain end to Vt that is ,
•
VGS-VDS=Vt
or
VDS= VGS-Vt or VDS(sat) ≥ VGS-Vt
Transistor in Saturation Mode
Assuming VGS > VT
VGS
S
VDS
G
D
n+
VDS > VGS - VT
- V -V +
GS
T
ID
n+
Pinch-off
B
The current remains constant (saturates).
NMOS Transistor: Saturation Region
iD 
vDSAT vGS VTN
'
Kn W
2 L
v VTN 

 GS
2
for vDS  vGS VTN
is called the saturation or pinch-off voltage
Channel-Length Modulation


As vDS increases above
vDSAT, the length of the
depleted channel beyond
pinch-off point, DL,
increases and actual L
decreases.
iD increases slightly with
vDS instead of being
constant.
channel length modulation
parameter
'
K n W 
2

v V 
 1 v
iD 

 GS
TN  
DS 
2 L
(pCox)
Enhancement-Mode PMOS Transistors:
Structure





p-type source and drain regions in
n-type substrate.
vGS < 0 required to create p-type
inversion layer in channel region
For current flow, vGS < vTP
To maintain reverse bias on
source-substrate and drainsubstrate junctions, vSB < 0 and
vDB < 0
Positive bulk-source potential
causes VTP to become more
negative
Depletion-Mode MOSFETS



NMOS transistors with VTN 0
Ion implantation process is used to form a built-in
n-type channel in the device to connect source
and drain by a resistive channel
Non-zero drain current for vGS = 0; negative vGS
required to turn device off.
Problem-solving Technique :MOSFET
DC Analysis
STep1: Requires knowing the bias
condition of the transistor such as
cutoff or saturation or nonsaturation.

Step2: If the bias condition is not
obvious, one must guess the bias
condition before analyzing the circuit.

Step3 How can we Guess?
(i) Assume that the transistor is biased in
the saturation region, which implies
that:
VGS>VTN,
ID>0,
and VDS≥VDS(sat)
If all the above conditions are satisfied,
analyze the circuit using the saturation
current voltage relations.
(ii)
If VGS<VTN, then transistor is probably
in cutoff mode.
(iii)
If VDS<VDS(sat), the transistor is
likely biased in nonsaturation region,
analyze the circuit using nonsaturation
current voltage relations.

MOSFET Circuit Symbols




(g) and (i) are the
most commonly used
symbols in VLSI logic
design.
MOS devices are
symmetric.
In NMOS, n+ region at
higher voltage is the
drain.
In PMOS p+ region at
lower voltage is the
drain
Summary of the MOSFET
Current-Voltage relationship
Table 5.1