Download Pins were added to the layout of the cell so that an LVS test could be

Pins were added to the layout of the cell so that an LVS test could be performed to verify the circuit.
This can be seen in Figure 1.
Figure 1 Layout of the unknown cell.
The first schematic derived from the layout can be seen in Figure 2. The topology of all of the transistors
was arranged to match that of the layout, which simplified the reverse engineering process.
Figure 2 First schematic derivation of the unknown circuit
In order to verify that the derived circuit matched the original one, an LVS test was performed on the
extracted cell and the newly created schematic. The results of the test, showing that the circuits match,
can be seen in Figure 3.
Figure 3 LVS log showing that the derived and the original circuits match
To simplify the circuit, another version schematic was created. This can be seen in Figure 4. It was
verified by another LVS check, whose log can be seen Figure 5. This new schematic clearly shows that
the circuit is a D-type flip flop implemented using a master-slave architecture. The constituent latches
are implemented using tri-state buffer, whose output can be set to invert the input, or to allow the
output to float.
For instance, in the first latch, if clk is low, the first tri-state buffer is set to invert, and the second buffer
is set to high impedance. The output of the latch (latchD) is thus the same as the input. When clk
switches to high, the state of the buffers is switched, and the output of the latch is thus its old value.
The second latch operates similarly, but remembers when the clock is low, and is transparent when it is
high. By combining these two latches, it can be seen that this is a rising edge flip-flop, since the input
value first makes it to the output value when the first latch holds the old value and the second latch is
transparent.
Figure 4 Second version of the derived schematic
Figure 5 LVS log showing that the second schematic matches the original design
The schematic was redrawn again using circuit symbols. This can be seen in Figure 6. Each of the tristate buffers has an enable input, which turns the buffer to invert only when the enable input is high.
An LVS test was not conducted, as it was known that the circuit would fail. This is due to the fact that
the tri-state buffers each have an internal signal to generate the inverted enable signal, whereas in the
original circuit, only one inverter is used to generate the inverted enable signal, as it is shared among all
of the buffers.
Figure 6 Circuit redrawn using symbols
The gate simulation was run, with the results viewable in Figure 7.
Figure 7 DC transient simulation of the gates
The formula that indicated a four-fold increase in size from NAND to NOR was derived for the case when
all 3 gates have a switching threshold (with all inputs changed simultaneously) of exactly 0.5*VDD.
Clearly, from Figure 7, it can be seen that this is not the case, as the NOR gate has a threshold of about
1.0 V, while the inverter has a threshold of about 1.4 V and the NAND gate has a threshold of about
1.8 V. Neither of these is 0.5*VDD (1.65 V), although the inverter and the NAND gate are close. As a
result, the expected sizes of between the NAND and NOR gates will be smaller than 4, although the
NAND gate should still be smaller (or the same size) as the NOR gate.
The layouts of all 3 gates can be seen in Figure 8. As can be seen, the inverter uses the smallest area
(since it has the fewest transistors), while the NAND and the NOR gates are both the same size. All of
the gates use PMOS and NMOS transistors that are the same size (L=0.35 um for both NMOS and PMOS,
W=2.4 um for NMOS and W=3.8 um for PMOS). This explains the results seen in Figure 7, as the
switching point of the NOR gate is very low. In order to balance the NOR gate better, larger PMOS
transistors would be needed, but this would increase the gate’s input capacitance and the gate’s power
consumption. The transistor sizes also explains why the NAND gate has a higher threshold voltage than
the inverter- since the transistors are all the same size, in the simultaneous switching case, the NAND
gate has twice the pull-up strength, since bother PMOS transistors are active, while the inverter has only
1 PMOS transistor pulling up.
Figure 8 Layouts of the compared gates
Referring to your simulation of the INV, NAND and NOR gates, comment on the switching points
realized by these gates. How does the switching point of each gate affect the noise margin of each
gate?
As discussed earlier, the switching voltages are 1.0 V for the NOR gate, 1.4 V for the inverter, and 1.8 V
for the NAND gate. The noise margin reflects amount of additive noise or interference the input signal
can have while keeping the output constant.
Typically, the best noise margin is usually 0.5*VDD, which allocates have of the supply voltage to each
logic value. This is why the threshold voltage is usually set the 0.5*VDD. The reason why this is
considered ideal is because the noise and interference tends to be uncorrelated with the input signal, so
the additive noise/interference has the same statistics, regardless of the current input value. Thus,
dividing the voltage evenly between both logic values will maximize the smallest noise margin any single
logic value has.
From this discussion and the values of the threshold voltages, it can be seen that the inverter and the
NAND gate both have fairly ideal switching thresholds with large noise margins, while the NOR gate is
fairly unbalanced and has a small noise margin for logic 0 values. However, these threshold values were
derived for the case where both input change simultaneously, a case which is quite rare when
considering noise, since additive noise will likely be uncorrelated from input to input, so the chance of a
large noise spike causing both inputs to change simultaneously is unlikely. Interference (such as crosstalk from a nearby wire) is much more likely to cause simultaneous switching since the amount added to
both inputs will be highly correlated. However, it is again unlikely to add equal amounts of interference
to both inputs, so the simultaneous switching case will cover only a small fraction of the possible
scenarios. For a more complete discussion, one will need to look at the cases where thresholds where 1
input is held constant, as well as cases where 1 input is held at an intermediate value (eg. 1.3 or 2.6 V).
This requires many simulations to be done and will yield very complicated results, and so is not very
practical.
Using the extracted cellviews, obtain the sizes of the pfets and nfets in each gate (INV, NOR, NAND)
and calculate the expected switching points. You may have to derive the switching points yourself (or
find a good textbook with the derivation - your choice). Compared the calculated switching points to
the simulated switching points. Give reasons for any differences.
To derive calculated values of the switching points, several parameters of the transistors are needed,
such as the threshold values, or the mobility constants. Thus, other simulations were run to obtain
these values.
An Id vs Vgs plot was created and can be seen in Figure 9 for the NFET.
Figure 9 Plot of Id vs Vgs with NMOS transistor with W=2.4 um and L = 0.35 um
Figure 10Plot of Id vs Vsg with PMOS transistor with W=3.4 um and L = 0.35 um