Download Simulation and Layout of CMOS Analog Circuits

Simulation and Layout of CMOS Analog
Circuits
Valentino Liberali
Università degli Studi di Pavia
Dipartimento di Elettronica
Via Ferrata 1, 27100 Pavia, Italy
Phone: +39-0382-505226; Fax: +39-0382-505677
e-mail: [email protected]
Contents:
Computer Simulation of ICs
MOS Modelling
CMOS Layout
EUROPRACTICE Training Course on
Analog CMOS Design with Low-Voltage Issues
Computer simulation of ICs
Verification of a CMOS IC design is practically unfeasible with a
bread-board:
Large number of active devices
Performance depends on optimum sizing
Discrete components have large parasitics
Computer simulation is used
to verify the design before prototyping
to optimize the design parameters
to estimate worst case performance
IC simulation tools:
SPICE (University of California at Berkeley)
ASTAP (IBM)
Spectre (Cadence Design Systems)
COMPUTER SIMULATION OF ICS
1
Circuit elements
Circuit simulation is applied to a circuit described in the structural
domain (i.e. schematic or netlist ).
Circuit elements (SPICE):
R Resistor
C Capacitor
L Inductor
K Mutual inductance
T Transmission line
V Voltage source
I Current source
E Voltage-controlled voltage source
F Current-controlled current source
G Voltage-controlled current source
H Current-controlled voltage source
D Junction diode
Q Bipolar junction transistor (BJT)
J Junction field-effect transistor (JFET)
M MOS field-effect transistor (MOSFET)
COMPUTER SIMULATION OF ICS
2
Circuit analysis
The simulator extracts parameters in the behavioural domain
(e.g. power consumption, frequency response, etc.)
Types of analysis (SPICE):
.OP
.DC
.AC
.TRAN
.TF
.FOUR
.DISTO
.NOISE
Operating point
DC transfer curve (input/output characteristic)
Frequency analysis
Transient (time-domain) analysis
Transfer function
Fourier analysis
Harmonic distortion
Noise analysis
COMPUTER SIMULATION OF ICS
3
Circuit solution
Any electrical circuit satisfies the Kirchhoff’s Laws:
Kirchhoff’s Current Law (KCL): At any time, the sum of currents flowing out of a node is zero.
Kirchhoff’s Voltage Law (KVL): At any time, the sum of branch
voltages around a loop is zero.
The solution of the circuit is obtained by solving a set of equations (KCL and KVL).
However,
in semiconductor devices, relationships between currents and
voltages are not linear
storage elements (capacitors and inductors) introduce derivatives
An example: KCL
i(v(t)) +
d
q(v(t) + u(t) = 0
dt
(1)
where
i(v(t)): currents in (non-linear) resistive branches
q(v(t): currents in (non-linear) capacitive branches
u(t): current sources (stimuli)
d
dt
COMPUTER SIMULATION OF ICS
4
Numerical constraints in circuit simulation
Numerical solution is obtained through an iterative algorithm.
Convergence criteria are used to stop iterations
Discrete-time differences replace derivatives
DC Analysis:
i(v(t)) +
d
q(v(t) + u(t) = 0
dt
(2)
becomes
i(v ) + u
DC
DC
=0
(3)
The solution is the Operating Point of the circuit, calculated with
the Newton-Raphson algorithm.
COMPUTER SIMULATION OF ICS
5
The Newton-Raphson algorithm
f(v)
v (2)
f(v (0) )
v (1)
v
v (0)
f(v (1) )
v*
Equation in the form: f (v ) = 0
v: exact solution
initial “guess”: v (0)
begin loop
(k )
linearization around v ( ): J (v ( )) = ( )
J is the Jacobian matrix (vector derivative on an N-dimensional
vector)
k
k
@f v
@v
updating rule: v ( +1)
k
= v( ) , J ,1(v( )) f (v( ))
k
k
k
converged ? exit : continue loop
COMPUTER SIMULATION OF ICS
6
Convergence criteria
“Residue” criterion
The KCL must be satisfied with a given accuracy:
fn (v (k) ) <
"
(4)
f
with
" = reltol f max + abstol
f
n;
(5)
where f max = absolute value of largest current entering node n.
Default values: reltol = 0.001; abstol = 1 pA
n;
“Update” criterion
The difference between the last two iteration must be small:
(k)
v
,
v(k,1)
<"
x
(6)
with
" = reltol v max + vntol
x
n;
(7)
,
where v max = max v ( ) ; v ( ,1) maximum absolute value of
node voltage in the last two iterations.
Default value: vntol = 1 V
k
k
n;
Both criteria must be satisfied to achieve convergence.
COMPUTER SIMULATION OF ICS
7
Convergence of the Newton-Raphson algorithm
The Newtow-Raphson algorithm converges if:
f is continuosly differentiable (to calculate J ,1(v( )))
the solution is isolated (i.e. for each branch, V-I characteristics
k
are not horizontal nor vertical)
the initial guess v (0) is sufficiently close to the solution
Convergence cannot be guaranteed in all situations.
If a circuit has more than one solution, the Newton-Rapson algorithm converges to the “nearest” one, and the solution found
depends on the initial guess (by default, I = 0 in all braches).
The simulator does not distinguish between stable and unstable
solutions.
COMPUTER SIMULATION OF ICS
8
MOS modelling
In circuit simulation, device models are important for accuracy
and computation time.
To avoid convergence problems:
model equations must be continuously differentiable
the slope of V-I characteristic must differ form 0 and 1 (uniqueness of the solution)
Classical MOS models (levels 1, 2 and 3) very similar to models used in hand-made calculations
Proprietary models (from silicon foundries)
Recent models (EKV) developed to improve simulation time
and accuracy
MOS MODELLING
9
Layout
The layout is the representation of a circuit in the physical domain.
The layout must contain all the information required to generate
the masks for circuit fabrication.
The actual mask geometry is obtained from the layout by means
of logical and geometrical operations (logical “and”, logical “or”,
size increment or reduction, etc.).
The layout contains the circuit elements and the interconnections.
In general, interconnections (and poor layout design) introduce
parasitic elements which can degrade circuit performance:
parasitic resistances due to interconnecting elements (lines
and contacts)
parasitic capacitances due to parallel lines and/or line crossing
component mismatching due to non identical design of elements
These parasitics elements must be carefully controlled and evaluated for critical designs.
LAYOUT
10
General layout guidelines
Use poly connections only for signal, never for current (the
offset is RI : with 4 squares R 150 , if I = 100 mA, then
V = 15 mV!)
os
Minimize line lengths, expecially for lines connecting high impedance nodes (if they are not the dominant pole node)
Use matched structures.
If necessary common centroid ar-
rangement
Respect symmetries (even with respect power devices)
Only straight-line transistors
Separate (or shield) the input from the output line, to avoid
feedback
Shielding of high impedance nodes to avoid noise injection
from the power supply and the substrate
Regular shape
Use a layout oriented design
LAYOUT
11
,,,
,,,,,
,,,,,
,,,
,,
,,
Stacked layout
Single MOS transistor:
W
Source
L
Drain
d
C = C = C W (d + 2x )
sb
db
jb
(8)
j
W
Drain
Source
W/2
W/3
Drain
Drain
Source
Source
Drain
Drain
A
B
Structure A:
1
2
W
C = C =C
sb
db
C =C =C
sb
db
(d + 2x )
(9)
2
W (d + 2x )
3
(10)
jb
Structure B:
LAYOUT
Source
jb
2
j
j
12
Capacitances are further reduced if the diffusion area is shared
between different transistors
Key point: use of equal width transistors (or part of transistors)
Transistors with arbitrary width are not allowed (but are they
really necessary?)
Placement and routing
If we divide a transistor in an odd number of parallel transistors
the resulting stack has the source on one side and the drain
on the other side
,,
,,
,, ,,
If we divide a transistor in an even number of parts the resulting stack has source or drain on the two sides
Drain
Drain
Source
Source
Drain
Drain
Source
Source
Drain
Placement of
transistors divided into stack in order to join
stacks.
LAYOUT
13
1
,,,,,
,,,,,
100
200
2
1
2
1
3
3
1
200
4
3
1
100
5
4
1
4
1
5
1
,,,,,,
,,,,,,
,,,,,,
Rounting into stacks: use “comb” or “serpentine” connections
LAYOUT
14
Example: fully differential folded cascode
Features: symmetry, common centroid input pair, minimum line
length.
2
2
M10
V
M9
B1
_
+
M1
V B2
M2
4
4
M3
_
M4
2
2
Out
+
Out
V B3
M6
M5
2
2
V B4
V
M13
6
B5
2
1
1
M11
LAYOUT
M8
2
M7
M12
9
3
3
9
10
4
4
10
1
1
2
2
1
1
2
2
11
13
13
13
13
13
13
12
7
5
5
7
8
6
6
8
15
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
,,,,,
V DD
V
B1
V
B2
V
+
V
V
B4
V
B5
V
B3
V
SS
LAYOUT
16