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ECE 477 Final Report  Spring 2012
Team 2  Awesillo-Scope
Team Members:
#1: __Bo Yuan __________________
Signature: ____________________ Date: _________
#2: __Yimin Xiao________________
Signature: ____________________ Date: _________
#3: __Yang Yang________________
Signature: ____________________ Date: _________
#4: __Jintao Zhang______________
Signature: ____________________ Date: _________
CRITERION
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ECE 477 Final Report
Spring 2012
Table of Contents
1.0 Project Overview and Block Diagram ................................................................................. 2
2.0 Team Success Criteria and Fulfillment ................................................................................ 3
2.1 An ability to sample analog voltage signal range from -12V to 12V via BNC cable ...... 3
2.2 An ability to reconstruct and display the sampled signal on VGA display...................... 3
2.3 An ability to create user interface and realize basic signal measurements, such as
frequency and peak-to-peak voltage ........................................................................................... 3
2.4 An ability to store/load the sampled signal to/from external memory ............................. 3
2.5 An ability to replay a stored signal .................................................................................. 3
3.0 Constraint Analysis and Component Selection.................................................................... 4
3.1 Design Constraint Analysis .............................................................................................. 4
3.1.1 Computation Requirements ...................................................................................... 4
3.1.2 Interface Requirements ............................................................................................. 4
3.1.3 On-Chip Peripheral Requirements ............................................................................ 5
3.1.4 Off-Chip Peripheral Requirements ........................................................................... 6
3.1.5 Power Constraints ..................................................................................................... 6
3.1.6 Packaging Constraints ............................................................................................... 6
3.1.7 Cost Constraints ........................................................................................................ 7
3.2 Component Selection Rationale ....................................................................................... 7
4.0 Patent Liability Analysis ...................................................................................................... 9
4.1 Patent and Product Search ................................................................................................ 9
4.1.1 Self Adjusting Oscilloscope (Patent No. 4743844) [1] ............................................ 9
4.1.2 Method and system for secure digital triggering for an oscilloscope (Patent No.
7860674) [2]............................................................................................................................ 9
4.1.3 Oscilloscope system for acquiring, processing, and displaying information (Patent
No. 4225940) [3]................................................................................................................... 10
4.2 Analysis of Patent Liability ............................................................................................ 10
4.2.1 Self Adjusting Oscilloscope .................................................................................... 10
4.2.2 Method and system for secure digital triggering for an oscilloscope ..................... 11
4.2.3 Oscilloscope system for acquiring, processing, and displaying information.......... 12
4.3 Actions ........................................................................................................................... 12
5.0 Reliability and Safety Analysis .......................................................................................... 13
5.1 Reliability Analysis ........................................................................................................ 13
5.2 Failure Mode, Effects, and Criticality Analysis (FMECA) ........................................... 17
6.0 Ethical and Environmental Impact Analysis...................................................................... 18
6.1 Environmental Impact Analysis ..................................................................................... 18
6.2 Ethical Challenges .......................................................................................................... 19
7.0 Packaging Design Considerations...................................................................................... 21
7.1 Project Packaging Specifications ................................................................................... 21
7.2 PCB Footprint Layout .................................................................................................... 21
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8.0 Schematic Design Considerations...................................................................................... 22
8.1 Theory of Operation ....................................................................................................... 22
8.2 Hardware Design Narrative ............................................................................................ 23
9.0 PCB Layout Design Considerations .................................................................................. 25
9.1 General ........................................................................................................................... 25
9.1.1 Different power supplies and ground plane: ........................................................... 25
9.1.2 A/D isolation and related power routing:................................................................ 25
9.1.3 High sensitivity components and channels ............................................................. 26
9.1.4 High-speed connection between MCU and FPGA ................................................. 26
9.2 PCB Layout Design Considerations - Microcontroller .................................................. 27
9.3 PCB Layout Design Considerations - Power Supply ..................................................... 27
10.0 Software Design Considerations ........................................................................................ 29
10.1
Software Design ......................................................................................................... 29
10.1.1 Data Storage/ Memory Allocation .......................................................................... 29
10.1.2 Function Implementation ........................................................................................ 30
10.2
Software Narrative ...................................................................................................... 32
10.2.1 MCU Code, Interrupts ............................................................................................ 33
10.2.2 MCU Code, Main.................................................................................................... 34
10.2.3 FPGA Logic ............................................................................................................ 36
11.0 Version 2 Changes ............................................................................................................. 37
11.1
Revise PCB ................................................................................................................. 37
11.2
Integrate power module onto the PCB ....................................................................... 37
11.3
Eliminate FPGA development board .......................................................................... 37
11.4
Improvement in enclosure manufacturing .................................................................. 38
12.0 Summary and Conclusions ................................................................................................ 39
13.0 References .......................................................................................................................... 40
Appendix A: Individual Contributions ..................................................................................... A-1
A.1 Contributions of Bo Yuan: ........................................................................................... A-1
A.2 Contributions of Yimin Xiao: ...................................................................................... A-3
A.3 Contributions of Yang Yang: ....................................................................................... A-5
A.4 Contributions of Jintao Zhang: ..................................................................................... A-7
Appendix B: Packaging ............................................................................................................ B-1
Appendix C: Schematic ............................................................................................................ C-1
Appendix D: PCB Layout Top and Bottom Copper ................................................................ D-1
Appendix E: Parts List Spreadsheet ..........................................................................................E-1
Appendix F: FMECA Worksheet .............................................................................................. F-2
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Abstract
The project we propose is a digital oscilloscope with playback function that
provides almost any function of a typical oscilloscope, such as digital sampling, signal
processing, auto-scale setting, cursor setting, reconstruction and visualization of signals.
Additional features such as recording and replicating signals as a function generator,
interacting with PC via USB and GUI display of signals will also be included.
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1.0 Project Overview and Block Diagram
This Awesillo-Scope will have the function of an ordinary oscilloscope. It will take
two analog voltage inputs and display the voltage versus time graph on a VGA channel.
The inputs are expected to be periodic. The graph will be triggered on a rising or falling
edge. Trigger voltage level will be adjustable by user. Scales of both axis (time/voltage)
are adjustable. The user interface will be consisting push buttons and rotary pulse
generators (RPG). A list of measurement values will be available, such as frequency,
period, max voltage, peak to peak voltage, average voltage, RMS voltage, etc. A cursor
function will be available. In addition, Awesillo-Scope will also implement a waveform
recorder. The scope can record, lock, and play an input waveform on an output panel.
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2.0 Team Success Criteria and Fulfillment
2.1
An ability to sample analog voltage signal range from -12V to 12V
via BNC cable
2.2
An ability to reconstruct and display the sampled signal on VGA
display
2.3
An ability to create user interface and realize basic signal
measurements, such as frequency and peak-to-peak voltage
2.4
An ability to store/load the sampled signal to/from external
memory
2.5
An ability to replay a stored signal
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3.0 Constraint Analysis and Component Selection
3.1
Design Constraint Analysis
The major design constraints will be induced by the two major controller
components utilized in data sampling/processing as well as displaying to a VGA
port. An ARM Cortex-M4 microcontroller will be used to sample/process data, and
a FPGA to generate the VGA display signal.
3.1.1 Computation Requirements
One of the project’s major constraints will be sampling rate
limitation. For the main purpose of this project – proof of concept,
sampling rate was chosen at 500 kHz maximum. In this time
frame, about 100 clock-cycle of computation per sampling period
is desired. The microcontroller should also be capable to perform
FFT, inverse FFT, sorting, filtering respecting to 480 of 12-bit
data points.
3.1.2 Interface Requirements
For the microcontroller in this project, two ATD converter
channels with 500 kHz sampling frequency and 12-bit resolution
are needed.
For the FPGA component, a development board with
VGA output is desired. The frequency is not the major
consideration, since FPGA frequency will be much higher than
that of microcontroller and VGA output protocol. One way to
simplify the design is to choose FPGA with voltage level that is
compatible with the microcontroller selection. In such a way the
bus can be connected directly between microcontroller and FPGA
without a level shifter.
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The microcontroller will be interfacing with an
external USB flash drive. The microcontroller should be able to
connect to, verify, write, and read from the external flash drive.
3.1.3 On-Chip Peripheral Requirements
For input sampling requirement, the microcontroller needs
to have at least 2 ATD channels with the capability of multisample processing. Since the design input voltage is in the range
of -25V to 25V, a 12 bit resolution would be a proper balance
between accuracy and speed.
For output (signal reconstruction) purpose, the
microcontroller needs to have a PWM output, or preferably a
DTA channel to achieve high performance when rebuilding the
digital signal.
To enable the communication between microcontroller
and display unit (FPGA), an I2C or SPI interface will be needed.
At least 10 GPIOs must be included for the interaction of user
interface. For instance, 3 GPIOs are needed for each Rotary Pulse
Generator (RPG) to perform rotation and pushbutton function,
four additional GPIOs will be required for the rest of the
pushbuttons.
The FPGA should have an implemented VGA output, a
similar system clock and a common voltage level with the MCU,
low cost PCI/SPI, and an on-chip RAM for buffering the video
output data.
The strongest candidates of microcontroller are
STM32F407VGT6 from STMicroelectronics and LM4F232E5QC
from Texas Instrument. For the FPGA component, Altera Cyclone
II EP2C35 and Spartan-3E FPGA will be two major candidate
selections.
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3.1.4 Off-Chip Peripheral Requirements
4 pushbuttons and 2 RPGs are needed for completing
functions of user interface. As for regulating the analog input
before ADC, an input voltage attenuator with flexible ratio will be
included. Also, a buffer and a signal filter should be accompanied
with the attenuator. For failsafe protection, isolation circuits and
Zener Diodes will be implemented.
For replicating the signals, an output voltage amplifier
circuitry will be needed to playback the signal in its original
amplitude. For visual output, a VGA interface controlled by
FPGA will be used as the display unit.
3.1.5 Power Constraints
This design utilizes general 110V, 60 Hz AC power and a
voltage regulator adjusts the on chip voltage to 3.3 V. Potentially
+/- 15V for operational amplifier to handle +/- input voltage is
also required. Due to the estimated size and microcontroller
operating frequency specification, heat dissipation is not
necessary. However, for safety consideration a chassis fan will be
added to ensure the components are kept in normal room
temperature constantly.
3.1.6 Packaging Constraints
The whole device should fit in a reasonably small and light
box (hand deployable size and weight) without visual display
screen (adaptable to any external VGA screen). The estimated
product size is 300mm * 250mm * 200mm or smaller. The user
interface should be easy enough for students in Electrical
Engineering to operate.
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3.1.7 Cost Constraints
The major components (MCU and FPGA) are chosen
to be STM32F407VGT6 and Spartan-3E (XC3S500E-4FG320C)
with costs at around $15 and $40, respectively. The prices for
other component are also included in Appendix B. One thing
worth mentioning is two of the team members have left over
STM32F407VGT6 samples along with a STM32F4-Discovery
development board from previous project.
The price of parts on user interface varies extremely
between brands and products. A silver plated BNC connector can
cost more than 60 dollars. A RPG varies from 5 dollars to 40
dollars. Due to the limitation of budgeting and the purpose of this
project, cost will be a major consideration on choosing
components.
3.2
Component Selection Rationale
For FPGA board selection consideration, since the main function of FPGA is
to communicate with MCU and generate VGA display output, the main features
being considered are data transmission and VGA interface. The two choices are
Cyclone Altera II and Xilinx Spartan XC3S400. Both FPGA versions are not very
up-to-date since the newer versions utilize lower supply voltage levels (2.5 V).
Instead, utilizing the older version FPGAs can avoid digital voltage conversion.
Thus the digital signal from MCU will be successfully transmitted to FPGA
without any logic level shifter. The clock frequency is required to be around 200M
Hz in order to react to the input control signal fast enough. Xilinx Spartan
XC3S400 was chosen over Cyclone Altera II because it meets all the required
features and the cost is reasonably low.
In terms of the MCU, there are also two choices, STM32F407VGT6 from
STMicroelectronics and LM4F232E5QC from Texas Instrument. The MCU is
mainly used for ATD conversion with targeted sampling rate up to 500K Hz while
achieving maximum accuracy. The STM32F407VGT6 has up to 2.4 MHz
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sampling rate whereas LM4F232E5QC has at most 1 MHz which is one reason of
choosing STM32F407VGT6 over LM4F233E5QC. Another reason is that
STM32F407VGT6 has larger on-chip RAM size than LM4F232E5QC. Since an
order of 1,000 samples of data is desired at one instant, as well as processing them
simultaneously, larger on-chip memory will provide more space and flexibility to
store temporary data.
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4.0 Patent Liability Analysis
4.1
Patent and Product Search
4.1.1 Self Adjusting Oscilloscope (Patent No. 4743844) [1]
Filing date: December 19, 1986
Abstract: This is a digital oscilloscope with adjustable gain and
offset for producing an output signal in response to an input
signal. It also has a triggering system for producing a trigger
status signal when the output signal reaches an adjustable trigger
level, and a digitizer for generating a waveform data sequence
representing magnitudes of samples of the output signal.
Key Claims:
1 – Periodically sampling the amplifier output and generating a
waveform data sequence representing magnitudes of successive
samples.
2 – Controls to adjust gain and offset of amplifier and adjust
trigger levels.
3 – Producing trigger status signal when the amplifier output
signal reaches an adjustable trigger.
4 – Producing a waveform display on a screen according to the
waveform data sequence produced by the digitizer and
automatically adjust the sampling rate of the digitizer
4.1.2 Method and system for secure digital triggering for an
oscilloscope (Patent No. 7860674) [2]
Filing date: April 24, 2006
Abstract: This is an approach for digital triggering one or more
signals on a digital oscilloscope by means of level comparison
between two successive sample values of a reference signal and a
threshold value.
Key Claims:
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1 – Triggering time is disposed if an overshooting or
undershooting of the threshold value by the reference signal is
present between the two successive sampled values of the
reference signal.
2 – Triggering time between two successive sampled values of the
reference signal is calculated by linear interpolation.
3 – Additional sampled values are distributed at an equal distance
between two successive sampled values of the reference signal.
4.1.3 Oscilloscope system for acquiring, processing, and
displaying information (Patent No. 4225940) [3]
Filing date: October 2, 1978
Abstract: This is an oscilloscope system to display waveforms
acquired by the vertical and horizontal preamplifier channels
immediately. It also allows the waveform data to be stored in a
memory so that they can be recalled and reconstructed in their
analog form and displayed at a later time.
Key Claims:
1 – Sampling circuit that takes samples of vertical and horizontal
waveforms.
2 – Samples are digitized by A/D converters and then stored in
coordinate relationship in a memory device.
3 – Waveform data can be sent to a compatible computer via
direct interface for further processing and then returned to the
system for display.
4.2
Analysis of Patent Liability
4.2.1 Self Adjusting Oscilloscope
There are many substantial similarities that this device and
our device share. We have the same structure in digital sampling
and the sampled waveform data sequence is stored in memory for
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display. We both utilize a microcomputer which has RAM and
ROM, and similar user interface (push buttons, RPGs). However,
the use of microcontroller to achieve these user interface
functions should be considered “obvious” since they are present
in most devices. The main difference between our device and this
patent is that we perform our A/D conversion through the ADC
channel on the MCU whereas they are using a digitizing circuit
for sampling. Also, our display of output signal is via VGA output
and controlled by FPGA. Our device has additional features such
as storing the waveform data to external memory and playback
the stored waveforms.
4.2.2 Method and system for secure digital triggering for an
oscilloscope
Our device is similar to this patent in two aspects: the
sampling and comparison process and the trigger determination
methodology. We both compare and detect trigger as we sample
our input signal. We both take successive sampled values to
calculate the threshold value and slope which will be used for
trigger detection. However, instead of using linear interpolation to
calculate triggering time, our trigger detection will utilize a 3point detection algorithm performed in our microcontroller which
uses the average of the three successive sampled data as the
threshold value and the calculated slope for comparison. We will
always check for trigger within 480 points and if the trigger is set
within the 480 points, “useful” data (480 points) will be acquired
starting from that point. Respectively, a trigger timeout signal will
be set if we can’t find trigger in the 480 points and the trigger will
be reset. In this case, a dynamic trigger setting is available for us
as not only can we use the user input as a fixed trigger level input,
since we are resetting the trigger every 480 points, we can have
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the trigger level automatically set by always using the first three
sampled points.
4.2.3 Oscilloscope system for acquiring, processing, and
displaying information
Our device is similar to this device in the following aspects:
the sampling process with A/D convertor, the storage of the
waveform data to external device for further processing and the
replay and reconstruction of signal for display. However, the main
difference is that this device takes both vertical and horizontal
inputs and stores them as coordinate relationship in memory
whereas we only record vertical data and use TIMER delay to plot
x-axis. Also, we perform digital reconstruction of output
waveform via FPGA whereas they are using a D/A convertor for
output display.
4.3
Actions
The analysis between Awesillo-Scope and the three patents concludes that,
there are definite similarities between Awesillo-Scope and all of the other devices
and systems; however, there are also distinct differences especially in ways of
achieving certain tasks, such as our input attenuation method, display control and
triggering algorithm. There may be other patents in which our device would
infringe so if we decide to commercially distribute this product, we would need
future research. In the case of patent infringement, we would try to acquire a
license in order to manufacture our product.
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5.0 Reliability and Safety Analysis
The project has been designed to be a lab-use instrument, so the environment can be
considered as Ground Benign (GB), with ambient temperature of 35oC. As a low-voltage
electrical product, our project does not have safety issue that will directly hurt user. On the
other hand however, there are plenty of safety concerns that may damage the product
components and sabotage the project.
5.1
Reliability Analysis
The components that are likely to fail in our project can be categorized as
either high complexity components or voltage-control components. The MCU and
FPGA consist of the complexity type while linear regulators, Zener diodes and
analog multiplexers are the voltage control components. The table below
specifically analyze the STM32 microprocessor [2], Xilinx Spartan -3E FPGA [3],
Linear regulator (part number UA78M33CKCS) [4], Instrumentation amplifier [5],
and Analog multiplexer [6].
Component: STM32F407VGT6. Model formula used: ℷp = (C1πT + C2 πE)* πQ πL
Parameter
C1
Value
0.56
πT
C2
πE
0.35
0.0425
0.5
πQ
10
πL
λp
1.8
3.9105
255721.77
MTTF
Remarks
Die Complexity failure rate for 32 Bit Microcontroller
Temperature Factor for TA = 35 oC Tj = 54.995 oC, θja = 43
Digital MOS, VHSIC CMOS, Still air
Package failure rate for 100 Pin LPFQ package
Environment Factor for Ground Benign*
Quality factor assumed due to commercial product with
unknown screening level.
Learning Factor for Years in Production=0.5 (Assumption
Made due to Data Sheet Revision made in 2011) [2]
Failures / 10^6 hours
hours to fail, approximately 29.19 years
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Component: Xilinx Spartan – 3E. Model formula used: ℷp = (C1πT + C2 πE)* πQ πL
Parameter
C1
Value
1
πT
C2
πE
0.19
0.098
0.5
πQ
10
πL
Λp
1
2.39
418410.0418
MTTF
Remarks
Die Complexity failure rate for 500,000 gates FPGA
Temperature Factor for TA = 35 oC Tj = 38.61 oC, θja = 36.1
Digital MOS, VHSIC CMOS, Still air
Package failure rate for 192 Pin DIP package, non-hermetic
Environment Factor for Ground Benign*
Quality factor assumed due to commercial product with
unknown screening level.
Learning Factor for Years in Production >= 2 (Assumption
Made due to Data Sheet Revision made in 2004) [3]
Failures / 10^6 hours
hours to fail, approximately 47.763 years
Component: UA78M33C Linear Regulator [4]. Model formula used: ℷp=ℷbπTπSπCπEπQ
Parameter
Value
Remarks
πt
14
πs
πc
πE
1
2
1
πQ
λb
λp
8
0.002
0.448
2232142.857
Temperature Factor at Tj = 125 oC (highest possible)
Electrical Stress Factor. Previous test suggest that applied
voltage will always slightly greater than rated voltage.
So choose Vs = 1.0
Contact construction factor, TOC-220
Environment Factor for Ground Benign*
Quality factor assumed due to commercial product with
plastic
Base Failure rate for voltage regulator
Failures / 10^6 hours
hours to fail, approximately 254 years
MTTF
Component: INA118 Instrumentation amplifier.
There is no assigned model for this component. Based on its internal diagram [4], there are
2 portions need analysis: precision amplifier and overload-protection. Overload protection is
a lot smaller than the precision amplify, so only precision amplify is analyzed.
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Model formula used for precision amplify: ℷp = ℷb πTπAπRπSπQπE
Parameter
λb
Value
0.00074
Remarks
Base Failure rate for amplifier
Temperature Factor at TA = 35 Tj = 35.48 oC (worst case)
,
πT
1.3
θja = 80
πA
1.5
Application factor, Assume MOSFET
πR
0.43
Power factor, P less than 0.1
πS
1
Worst stress factor is V_apply = V_rated
Quality factor assumed due to commercial product with
πQ
8
plastic
πE
1
Environment Factor assume Ground Benign*
λp
0.00496392
Failures / 10^6 hours / op-amp
MTTF
201453689.8
hours to fail, approximately 22997 years
Since there are 3 op-amps in the structure
ℷp = 3* ℷp-op-amp = 0.014891, MTTF ~ 7665 years
Component: MAX14752 Analog multiplexer, 2 formulas used:
Digital portion: ℷp = (C1πT + C2 πE)* πQ πL
Parameter
C1
Value
0.01
πT
C2
πE
1.3
0.0056
0.5
πQ
10
πL
λp
1
0.158
6329113.924
MTTF
Remarks
Die Complexity failure rate for 16 gates
Temperature Factor at Tj = 115 oC (worst case power
dissapation assumed), θja = 90
Package failure rate for 16 Pin TSSOP package
Environment Factor for Ground Benign*
Quality factor assumed due to commercial product
with unknown screening level.
Learning Factor for Years in Production >= 2
(Assumption Made due to Data Sheet Revision made
in 2010)
Failures / 10^6 hours
hours to fail, approximately 722 years
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Switch portion: ℷp = ℷb πTπSπCπEπQ
Parameter
λb
πT
πS
πC
πE
πQ
Λp
MTTF
Value
0.012
Remarks
Base Failure rate for switch
Temperature Factor at Tj = 115 oC (highest possible)
Electrical Stress Factor. Applied voltage is the output
1
votage. So Vs = 1
1
Contact construction factor, TSSOP-16
1
Environment Factor for Ground Benign*
Quality factor assumed due to commercial product
8
with plastic
0.432
Failures / 10^6 hours /switch
2314814.815
hours to fail, approximately 264 years
Overall: λp = λp-digital + 8 * λp-analog = 3.614
4.5
Overall MTTF: ~31 years
* Since our instrument will mainly be an in lab equipment, Ground Benign (GB) environment
was selected for all the components, with Tambience = 35 oC
Overall, the reliability for most of the parts is acceptable and shall not perform
erratically during lab environment. Three most critical parts are MCU, FPGA and
Analog MUX, respectively. Since 2 of the critical components are related with the
input sampling process (Analog MUX and MCU), the input procedure is having a
great deal of challenge. There was an improvement made at the beginning of the
project is to implement a Zener Diode into the input circuitry and use INA118
instrumentation amplifier as protection circuit. These two components have a
relatively low failure rate, thus they can provide effective protection to the
circuitry and turn the high criticality failure (damaged components/ circuit) into a
low criticality failure (inaccuracy or bias in measurement). The other highly
critical portion is the I2C communication. Both terminals MCU and FPGA) are
critical components and I2C itself does not have an error correction mechanism.
The way to reduce the problem is to increase the transmission frequency (100 Hz)
and make it higher than the refresh rate of the VGA output (60 Hz); additionally,
decreasing the I2C data speed will increase the reliability of this BUS. Other than
the refinement above, no further improvement is necessary.
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Failure Mode, Effects, and Criticality Analysis (FMECA)
Awesillo-Scope can be split into 4 portions: Power circuitry,
Microprocessor unit (including user interface), FPGA display unit, and input
circuitry. As for in-lab equipment, Awesillo-Scope is not likely to cause any harm
to user with its low voltage and small current. The enclosure is made by aluminum,
which should be a good shelter for voltage leakage. With the fan provide, heat
should also not be a hazer to consider by user. However, there are still highly
critical conditions which can permanently damage the voltage sensitive
components. As a result, it is determined that high criticality conditions cannot
have a failure rate exceeding 1 in 109 hours since the damage would be costly and
should be prevented with all effort. The low criticality is defined as all other
possible errors such as incorrect input value, failure to output signals, etc. It is
preferable this kind of condition will appear no more than 1 in 106 hours. Although
none of the failures can possibly cause harm to user within the containing box,
Awesillo-Scope should keep the failure rate less than 1 in 106 hours to perform
well for a decent period of time.
Power supply, among all these portions, can cause the highest criticality by
overload any subsystem if the power management is not working properly.
Obviously most of the high-criticality conditions belong to Power circuit (See
appendix B, case B-Power supply). Although power circuit is handling most of the
power consumption, the most critical portion is the input circuitry. The input
circuit has two high-failure rate components. The complexity of input analog
circuit also will increase the potential failure rate. Additionally, there is also
potentially large voltage coming in through input circuit.
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6.0 Ethical and Environmental Impact Analysis
6.1
Environmental Impact Analysis
The manufacturing process of the product will induce hazardous material.
PCB will be the major environmental impacting component. The PCB etching will
require corrosive and environmental hazard materials such as ferric chloride. To
minimize the threat to environment, the life-cycle of the product should be
prolonged to reduce the environmental damage. ROHS-compliant parts and solder
should be used; and board area should be minimized to reduce the environmental
damage.
The components on the PCB also propose critical environmental threats
since the production sequence uses hazardous materials for etching. However, all
the components selected are of ROHS standard, which means during the
manufacturing process, the use of hazardous material has already been minimized.
Many solder are comprised primarily of tin and lead. Overuse of the solder
will not be perceived in an environmentally friendly way.
For safety and protection consideration, packaging is required for our
product. A metal enclosure was selected to package the compartments and isolate
the environmental noise. The box is recycled from other products and will be
approximately 300 mm * 100mm * 80mm. The production of metal will also
inevitably impact the environment.
To minimize the environmental impact, limited materials should be used.
For example, the PCB should be as small as possible, and should be easy to fix
when certain parts are damaged. Also, the use of parts should be limited and
properly disposed if damaged. Finally, it is also important to restrict the material
used in packaging the device.
During normal utilization, the power consumption of the device is
approximately 2.5 Watts. Although comparatively smaller than most
Oscilloscopes, the device is not as power efficient because most of the power is
consumed on the linear regulator. To reduce the unnecessary energy consumption,
low dropout linear regulator (5V to 3.3V) is more preferable than the high voltage
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regulator (12V to 5V). Additionally, in order to generally use the product, a VGA
display must be presented. As a result, the VGA screen also becomes part of the
power consideration of our project. Normally, external VGA will consume 17-31
Watts if it is a high-efficient LCD screen and 80 Watts if it is an ancient CRT
display. To ensure the efficiency of the product, the display is designed as LCDscreen based and on the user manual, LCD screen will be recommended.
When the product enters its disposal phase, it should be disassembled. Since
none of the parts are degradable, all the components should either be recycled or
properly disposed. Apparently, the metal box can be easily recycled either for
other uses or commercial reproduction. The other electronic components, however,
must be taken to a disposal center. The vendor of Awesillo-Scope could offer a
customer return program and take the product apart for a more efficient recycle
and reuse purpose.
6.2
Ethical Challenges
As laboratory equipment, Awesillo-Scope does not many ethical challenges
during its proper use. However, if misused, the product can be problematic for
direct user and other people.
Laboratory instruments usually require high accuracy, which could be a
potential problem in Awesillo-Scope. Sampling sequences will be done through an
ADC and processed within the microprocessor, thus the accuracy of the signal can
be distorted by external noise or on-chip interference. During special cases,
inaccurate measuring could cause danger to devices or even the user. Thus, it is
crucial to direct attention to maximize the accuracy of each sampling. The input
voltage level should be carefully calibrated. Since the range of the frequency is
less than 200 kHz, a low pass digital filter can be implemented to construct the
noise rejection mechanism for reducing the possible noise in the sampling process.
Moreover, the VGA output should be properly protected so that the VGA output
could not be damaged due to potential short circuit of the product. Additionally,
operating in an extreme hot or cold environment will impede the performance of
the microprocessor, possibly yielding erroneous results. To ensure the highest
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performance, the user should only utilize the project in a lab and preferably on a
stationary platform with proper guidance. Warning signs and labels should be
attached on the product.
Although the product’s output channel seems to be safe to the user (+/- 12
V), it is not always safe for other electronic devices. The output voltage level
should be carefully calibrated. The output of the playback channel has to be
predictable; otherwise it may easily burn other voltage sensitive components.
Moreover, the current of the output channel should not exceed a few milliamps,
since high current output will waste energy and endanger current sensitive parts.
From the above ethical consideration, it can be concluded that all output
functionality test should be required before output functions (DAC, VGA) being
put into use. Also, it has to be assumed that the voltage output channel can be used
as a steady voltage output and low power voltage source. In conclusion, the testing
process before output any signal would be necessary and it is also critical to ensure
that the outputs can be adaptable with any viable external circuitry. Moreover, it is
highly important to measure the accuracy level of the sampling, otherwise it may
mislead user to draw wrong conclusions.
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7.0 Packaging Design Considerations
7.1
Project Packaging Specifications
The package of the device is a stand-alone box with certain input and output
terminals. By reference the products in the market, a general-purpose aluminum
rectangular case was determined to be the best choice for packaging.
The device was designed for general laboratory use, so as long as the
product is portable (doesn’t have to be “palm size”), it would be acceptable.
In conclusion, the packaging constraints are: 1. Portability: must be easy to
transfer by hand. Light-weight: 20 lbs or less in total weight. 2. Operating
environment: ±10 ºC around room temperature. A chassis fan would provide such
environment, however if the constraints cannot be met by a chassis fan, other heatsink methods would be implemented. The interface (keypad, RPGs, and VGA)
should be easy to use by students with basic oscilloscope knowledge.
7.2
PCB Footprint Layout
The three components previously identified as major elements of the project
include the STM microprocessor and Spartan 3E FPGA for digital components;
and analog components are Op-amp (2 types), precision resistors, DC/DC
converter, Voltage regulator (2 types), and ports for other off-chip components
(LED, LCD, Input/ Output port).
After searching parts online, we found that most parts have only 1 type of
size/ packaging. Fortunately the parts fit our design consideration. Detailed parts
packaging/ size see attachment.
After some optimization of our initial layout, out PC board size conclude to
be 225mm X 180 mm (digital components); and 150mm X 120 mm (analog
components). Since the application should not involve large current consumption,
using 16-mil for power supply trace and 8-mil for signal trace is sufficient.
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8.0 Schematic Design Considerations
In this project, it is necessary to separate the circuit into 2 parts and isolate them
properly. A PCB with two separated portion will be designed and connected only through
pin ports and BUSs with low voltage (<=3.3V) signals. Three different supply voltages (+12V, 5V, 3.3V) will be implemented on the analog chip; the digital chip will have a 3.3V
reference voltage, a 3.3V supply voltage (for MCU), and a 5V supply voltage (FPGA).
8.1
Theory of Operation
On the analog portion of the circuit board, two major tasks will be completed:
regulate the voltage to provide digital voltage supply (3.3V) and pre-process
(majorly attenuate or amplify) the input analog signals. The MCU will need a 3.3V
voltage supply; FPGA and relay driver will need a 5V voltage supply along with
sufficient current; and the op-amps for attenuating the output signal will need at
least a +/-12V voltage supply. As a result, multiple voltage levels are required on
this board. With the ATX computer power supply unit, it is easy to provide
different voltages with sufficient current on chip. Additionally, the maximum
sampling frequency is 200 kHz as determined before. Under this frequency all our
components will function properly.
In order to pre-process the analog signal for the MCU, an 8-bit shift register
controlled power relay driver (MAX4820, works at 3.3V) and a front-end resistor
(~900 kOhm) will be utilized to bring in 8 different voltage-selection channels.
Each channel has a digital-controlled transistor switch and a resistor. The MCU
controls the shift register with SPI so when a different voltage level is selected, the
shift register will open up the correspond channels, connecting the corresponding
resistor to the circuit. With the different voltage dividers selected by the relay
driver, the input voltage will be attenuated to different voltage level based on the
user’s setting (See attachment Fig. 1, How Relay Driver work). Then operation
amplifier buffer will be employed to stabilize the voltage by setting it in the range
of 0~ 3 V. After that, the signal will go through a low pass Butterworth filter to
avoid aliasing when sampling. The final protection circuit before the MCU ADC is
a Zener diode.
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On the digital portion of the PCB, the microprocessor will continuously
sample (if started) the regulated analog signal. All the data processing, calculation
sequences and user interface will be completed in the MCU. The MCU will
continuously feed the packaged data (signals for display with the proper
vertical/horizontal scale, measured information, other user interface information,
etc.) to the FPGA via I2C. The FPGA, which serves as a display unit, will convert
the data into VGA output signals and output them through VGA outlet to external
screens or projectors.
Other components on digital circuit are external oscillator (~160 MHz), which
will boost the MCU clock speed to fulfill the sample frequency. Additionally, nine
MCU GPIO pins will be used for user interface, which will sample the pushbuttons
and RPGs’ inputs.
8.2
Hardware Design Narrative
For an oscilloscope, the analog to digital conversion channels will be
implemented to achieve sampling, the foremost task of the whole project. The
front end of the circuit will pre-process the voltage for the ATD channel. Then the
signals will be sampled and processed . Calculations will also be performed within
the microprocessor as user requests, during which the timer module of the MCU
will be used to get sampling rate.
The SPI on the microprocessor was considered for transmitting control
signals to the relay driver; since the relay driver is controlled by shift register, it is
simple to transmit this data through SPI. When the user rotates the RPG to set the
voltage scale, the SPI will shift out subsequent data to the shift register and the
relay will form up the proper circuitry for attenuation.
The I2C interface on the MCU will be utilized to transmit raw display
signals to the FPGA; two I2C interfaces will be used if a faster connection speed is
desired. The reasons I2C was chosen for the job are primarily the connection speed
and the simplicity of the protocol.
As for the user interface, which mainly consists of pushbuttons, RPGs, and
LEDs, GPIO pins were selected to achieve the task since there are plenty of I/O
pin ports left on the microprocessor with all other functional pins being assigned.
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Finally, the MCU will also write data to an external storage device. It is
relatively easy to program the pins to write data in .txt format in a SD card.
Another SPI will be employed for this non-vital task.
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9.0 PCB Layout Design Considerations
It has been estimated that the PCB with all the crucial components will have
different power routing, power/ground distribution for sensitive components, high-speed
serial peripheral, and control circuitry. The system should function normally at maximum
200 kHz sampling rate. Major constraints of the main PCB include: three different power
supply voltages on board, analog-digital isolation, potential external signal interference,
high sensitivity analog devices (precision Op-Amplifier), high-speed communication
between MCU and FPGA, and sensitive analog-to-digital conversion channel on MCU.
9.1
General
9.1.1 Different power supplies and ground plane:
Trace size for each power supply will be selected to
match the maximum possible current through it. However the
ground distribution may be an issue since power supply cannot be
placed in the center of the board (center reserved for MCU for
clock distribution). Thus, multiple solid/ mini ground planes will
be created to optimize the ground distribution and sinking the
possible leakage current caused by multiple sources.
9.1.2 A/D isolation and related power routing:
The board will consist of analog and digital
components; therefore the isolation between them would be a
crucial part. All power regulation and voltage conversion will be
performed on analog portion, 5V will be achieved by the 12V
ATX power and an additional 3.3V will be achieved by step
down the 5V ATX output. We do not want to use the direct 3.3V
supplied by the ATX unit, since it seems to be a switching mode
power supply and have a 0.3V ripple voltage. The 3.3V is for
microcontroller, which is doing the sampling process. We do not
want external noise to affect the sampling resolution.
However, for the reference voltage required by the
MCU’s ADC, the ATX power is not sufficiently stable. Thus an
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voltage reference chip that will be used to provide a flawless
reference voltage.
To minimize the analog/digital interference, the two
types of components need to be separated as far as possible
(without enlarging the PCB significantly). They will be isolated
by being placed on the opposite end of PC board. Extra isolation
will be implemented for sensitive components/traces.
The analog ground and digital ground need to be
separated as well. A small inductor (serving as a low pass filter)
will be connected between the analog ground plane and digital
ground plane. However, if the testing on the PCB shows that
analog and digital grounds do not severely affect each other, the
two grounds can be connected.
9.1.3 High sensitivity components and channels
The components that will create most interference (i.e.
the crystal) need to be set apart from sensitive parts (i.e. precision
op-amplifier). Fortunately, the most sensitive part (op-amplifier)
will not be controlled by the MCU, thus the only protection
necessary is the decoupling capacitor.
Another sensitive part is the ATD channels on MCU.
As tested before, the last 3 bits of the ADC (12 bits total) kept
flickering when continuously sampling a signal. However after
providing an extra stable Vref, the ADC will function with only 1
unstable bit. To increase the accuracy and reduce the average
calculation in the MCU, an extra chip that will supply a steady
3.3V reference voltage will be added.
9.1.4 High-speed connection between MCU and FPGA
The communication between the MCU and FPGA is
implemented through a high speed I2C 3.0 interface. So this
interface would be susceptible to any kind of noise, such as closerange EMI.
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In order to secure this communication, the traces need to
be isolated (i.e. not overlap with any other traces) and be as short
as possible. So the MCU and FPGA need to be placed close
together. Moreover, since the oscillator needed to be placed near
the MCU also, the oscillator and I2C should be at least separated
by the MCU to prevent high-frequency EMI from affecting
transmission. A coil EMI filter will also be implemented to ensure
the transmission will be glitch-free.
Overall, in order to reduce external signal intrusion, the package will be in a metal
box and have a stable ground. As a result, the PCB has to have a limited sizing so
that it will not touch the box from inside. So the PCB size will be limited to 25 sq.
in.
9.2
PCB Layout Design Considerations - Microcontroller
The microcontroller will be managing the entire control circuitry, thus to
optimize all the control signals, the MCU should be placed in the center of the
PCB. To minimize the overall interference caused by crystal, it should be placed
next to the MCU in the center of the PCB.
Multiple bypass capacitors are required on the MCU to reduce any possible
analog interference. Between any 2 input ports of the MCU, a bypass capacitor
will be needed to stabilize the input/output signal. The location of the decoupling
capacitor will be on the back of the PCB.
The MCU power will be powered by a regulated 3.3 V power supply
obtained from a linear regulator. The current running through MCU will be less
than 100 mA which requires 1.2 mils. Thus the 8 – 10 mil trace will satisfy both
power and signal. There is no need to implement additional power traces.
9.3
PCB Layout Design Considerations - Power Supply
After thorough testing on the ATX power, it is determined that all the
voltages it provided are not as stable as we needed. This weakness will induce
extreme noise in our overall system. In order to provide steady power on all the
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parts, linear regulators will be used, and steady voltage will be achieved by
regulating a higher voltage (i.e. get regulated 5V by regulating 12V voltage).
The +- 12 V supply will not be used since after measured by DMM, the
actual output are + 11.3V / -11.5V, with +- 0.3 V peak-to-peak swing. Thus it will
create serious interference to the precision amplifier. To solve that problem, a
linear regulator will be implemented and regulate the 12 V into a steady 5 V
supply. The only components using the +/-5V supply are the precision amplifiers,
which consumes about 1mA current each chip. Thus heating should not be a big
issue for the 7V drop linear regulator.
Regulators on chip are sensitive to EMI and other possible noises around, so
for each regulated power route on board, 2 capacitors will be connected right by
the power module. The first one is 10 uF, to prevent instantaneous current glitch;
the second one is 100 pF to filter out the potential high frequency noise from the
input power line.
Throughout the PCB, small current (< 100mA) will be consumed, as a
result, there is no need to consider the interference between the power and ground
lines. So the power trace will follow the ground trace all over the PCB to minimize
the loop that causes potential EMI.
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10.0 Software Design Considerations
10.1 Software Design
10.1.1
Data Storage/ Memory Allocation
Since the FPGA will only be implemented as a display
unit and all crucial calculation/ data-processing will be performed
in the MCU, it is critical to effectively manage the SRAM size for
temporary storage and calculation. Additionally, sampling and
processing data would certainly need a large amount of memory
for arrays of variables, I/O registers, and buffers, so clearly
defined memory location and the format of the data inside the
MCU would be necessary.
There are three categories of task for the MCU to complete,
which are sampling, user interfacing, and calculation;
accordingly, there are 3 major types of data required. First, for
each of the two sampled channels, 480 data points with 12-bit
resolution data would be required; the storage of these data points
will take up a major portion of the dynamic memory and slow
down the calculation process. Next, for each general purpose
pushbutton input, a register will be used as a flag. Register value
will be set in the Interrupt, and then cleared in Main; following
that the corresponding function will be executed. The
USB_MODE register would be a toggle based register, since USB
mode in the Main function has a higher priority than all other
functions. The RPG register will be initialized as a signed value
and repeatedly changed when rotational pulse is detected. Other
necessary flags will also be defined with these flags. Last but not
least, the calculated results will be initialized as 0s and updated by
the function. The display sequence will read all these and transmit
them by pack to the FPGA.
The microcontroller possesses an embedded SRAM of 192
Kbyte, split up into three blocks of 112 Kbyte, 64 Kbyte and 16
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Kbyte. The start address of the SRAM is 0x2000 0000. Since the
CPU is directly reading/writing from/to the 112 Kbyte SRAM
(ends at 0x2001 BFFF), all the required flags, and registers
mentioned above along with the stack pointer will be stored in
this location. During execution, the SRAM will be accessed
through the system BUS, so the flag and registers will be updated
timely.
Although the SRM32F40x series MCU have the capability to
boot from SRAM by setting the BOOT [1:0] vector, it is decided
that all the code will be stored and running in the FLASH
memory, because FLASH will not lose memory when the power
is cut-off, and it has a larger space than SRAM. So the booting
mode of the microcontroller will be, by default, FLASH boot with
available FLASH memory from 0x0800 0000 to 0x080F FFFF.
10.1.2
Function Implementation
The Main function in the STM32 MCU will use flagdriven operation. Interrupts (majorly TIMER interrupt) will keep
update data arrays and Main loop will perform flag-driven, real
time analysis. Due to large amount of potential calculation (480
points FFT), TIMER interrupts will be temporarily disabled when
FFT is taking place, which will cause the device get into “No
response” state for a short period (~tenth of millisecond).
In DMA module, 2 ADC channels, 4 TIMERs, and 1
DAC channel will be employed to perform necessary functions
such as interrupting, sampling and output. The ADC sampling
channel have its own clock and Phase-Lock Loop, after
initialization, it will keep interrupting with the rate of 1.2 MHz
(controlled by ADC_SMPR1) and keep updating the ADC_DR
register. The trigger will always be setup with the fastest sampling
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rate; however the recorded data will be properly separated by
sampling rate.
TIMER1 will be used for detecting real-time general
purpose input from user interface and set up corresponding flag;
TIMER2 will be used for I2C data transmission, as mentioned
beforehand, the FPGA will neither store nor process any data, it
will simply translate the data from MCU into VGA display,
therefore the MCU is controlling the refresh rate of the screen.
The data will be send every 10 ms (100 Hz) to maintain the
refresh rate (60 Hz). When data is transmitting, it should not be
interrupted by any other TIMER; otherwise the data transmission
may be sabotaged. Therefore the priority of I2C should be the
highest among all the TIMERs.
TIMER3 and TIMER4 will perform two different kind
of sampling, one is for “Fast sampling” and the other is for “Slow
sampling”. Each will setup the trigger followed by retrieve
certain points of data. For the “Fast” mode, 480 data points will
be retrieved within 1 interrupt separated by delay functions, thus
it requires the retrieval rate to be fast; the “Slow” mode will
retrieve 1 data point at a time, but the interrupt rate will be
determined by the sampling rate.
DAC output, unlike the ADC, does not have a selftimer. Thus an additional TIMER would be utilized for the DAC
trigger. The data ready to be output will be stored into DAC
buffer and TIMER provides the proper “release rate” for the data
array. The output circuitry will take care of the magnitude of the
signal. When DAC is enabled, an additional TIMER interrupt
will be added.
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Code Priority
10.2 Software Narrative
Overall, the Main function is a hybrid of polling and flag-driven structure.
Within the main function, different blocks will be implemented and they will
perform different purposes. Also the main function will keep check for the flags
and perform corresponding sequences to clear the flags. Other than the Fast
Sampling interrupt, all the other interrupts will not perform any major calculation.
Therefore, in the main function all the priority levels and the execution chain will
be determined.
Other than the main function, 4 additional TIMER interrupts will be used
for Slow Sampling, Fast Sampling, general purpose input-check, and display
update purposes, respectively. GP input-check will simply perform routine edgedetection on each pushbutton and RPG. Other interrupt sequences are described
below.
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MCU Code, Interrupts
Slow Sampling
In Slow sampling mode, the TIMER interrupts at the
sampling rate. If the trigger is not set yet, 3 points will be
retrieved and compared with the 3 initial values for trigger setup.
Every time a new set of data is fetched before trigger is set,
timeout counter will be incremented. If the trigger is set or
timeout counter exceeds its maximum value, the sampling
sequence will not attempt to setup the trigger. Instead, a datapoint will be fetched and stored in the data-array. When the dataarray is filled, the trigger will be reset and the sampling sequence
will start-over.
Fast Sampling
In Fast sampling rate mode, same trigger setup sequence
will be implemented at each TIMER interrupt. If the trigger is not
set, it will keep fetching data in the same TIMER interrupt. After
timeout or trigger is set, 480 data-points will be retrieved
separated by delay function to satisfy user’s sampling time
setting.
I2C Data transmission
The VGA should keep refresh with minimum 60 Hz
frequency. Thus the MCU should update the data transmitted to
FPGA frequently. Therefore every 10 ms, MCU will send a new
data package to FPGA in order to update the display. The reason
to keep a 100 Hz refresh rate is to guarantee the update rate can
be stabilized at 60 Hz.
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MCU Code, Main
Peak to Peak value calculation
The algorithm to find the maximum and minimum point
of the fetched data points is Bubble Sort. As there are only 480
points for sorting, Bubble sort will be efficient and fast enough to
complete the task.
Frequency and Period Calculation
With all 480 points sampled and stored, a
“data_complete” flag will be triggered. If user requests frequency
and period information at this point, the calculation sequence will
perform a high-priority Fast Fourier Transform to the data points.
After DFT magnitudes are acquired, the maximum value will be
acquired and corresponding frequency will be calculated based
on current sampling frequency and maximum frequency position.
After the frequency is calculated, the period will be fairly easy to
calculate.
Offset
The offset function, if triggered by user, will add the
certain amount offset value to every data-point based on
corresponding RPG data register, thus the entire data sequence
displayed will be shifted accordingly.
Sampling Frequency Change
By default, the sampling frequency will be 1 kHz (1ms
separation in “slow” sampling mode). User can change the
sampling frequency by selecting it in the RPG menu and then
rotate the RPG. The updated sampling frequency data will
effectively change the TIMER interrupt rate (slow mode) or the
delay sequence between fetching data point (fast mode),
respectively; the same value will also be used in frequency/
period calculation.
Run/ Stop
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The run/stop function will be used to freeze the display
waveform (but the sampling and menu will keep running).
Therefore, the data-points will be “locked” when run/ stop flag is
cleared. However, it will affect neither the sampling sequence nor
the user interface. User can still analyze the static data-points
with internal functions. User presses the button again to resume
normal function and dynamic waveform.
Scaling Calculation
In case that user would like to view the data in a different
horizontal or vertical scale, RPG menu can be used to set the
scale factor. The scale factor (1, by default) will be multiplied to
all data-points before the points being transmitted to FPGA
display. The scale factor itself will also be transmitted in order to
display the proper Voltage/ division and Time/ division values.
Cursor Display
User can also view the exact location at any point of the
screen via cursor. When cursor is enabled, it will by default
appear in the center of the screen. Each RPG pulse will cause the
cursor to move exactly the same distance on the screen (not
necessarily same time/ voltage division). The cursor position
vector will be updated as the cursor is moving around; the
position vector will be displayed on the screen also when the
cursor is enabled (by default, at (0, 0)).
USB r/ w mode
When the MCU interacts with the USB device for reads/
writes data, all other function will be temporarily disabled except
the display function. The MCU will perform read or load from
the external storage device. In read mode, the display will show
the waveform stored in SRAM read from the USB device.
Replay function
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When the user saves a waveform, the MCU will store the datapoints of a channel and its corresponding sampling frequency
into the SRAM. When the user decides to replay the data stored
in SRAM, the DAC will continuously output the corresponding
data-points based on sampling rate.
10.2.3
FPGA Logic
I2C (
The FPGA will act as a slave device and receive data package
from MCU in a specific format (sampling data, calculation
results, and user interface info and cursor position). Since the
MCU will be the only master and FPGA the only slave, no major
feedback signals are necessary to be sent from the FPGA to the
MCU except ACK and NACK signals. The data package will not
be stored; instead will directly connect to display as the FPGA
receives data.
VGA display
The VGA will enable a 640*480 pixel resolution display. The
screen is scanned line by line to update the pixel RGB data.
Horizontal sync and Vertical sync signals are used to set up the
correct timing for scanning the screen. The display will include
both the menu view and the data waveform. Each individual
menu item will reverse color to indicate user selection.
There are multiple difficulties in coding the Awesillo-Scope considering the
complexity of functions, algorithms, and transmissions. Several mode for sampling (Fast
and Slow) and for main (USB mode and Normal mode) are required for specific
functionality. Thus plenty of flags and registers will be implemented to create the polling
structure of the Main code. Even though the majority of the code has not been completed,
the theoretical ideas of all the functions are determined.
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11.0 Version 2 Changes
We found multiple improvements that can be done in the second version:
11.1 Revise PCB
A mystery pin on FPGA needs to be pulled high externally. We didn’t
found out until the PCB soldering is finished. So a fly wire has to be made to do
such connection.
Some of unconnected landing pad for microcontroller was token out since
there is no copper or solder mask to hold the pad. A reflow oven should be used to
solder the SMT parts, especially when a lot of unconnected pads are presenting.
Place all components on upper side of the PCB, so that change component
will be easier.
Move the FPGA module away from the power supply connector, if not
eliminating the FPGA development board. The physical size of the FPGA module
is larger than then landing pattern. The current version cannot plug in FPGA and
power connecter at the same time. The power supply connecter has to be cut into
individual lines to plug in to the board.
11.2 Integrate power module onto the PCB
An external computer power supply unit was used in this project. The ATX
unit is rated at 180W and our design only requires less than 5W. On a new version
the design should intergrate 110/220V supply on board, or should be simply
powered by a battery circuit.
11.3 Eliminate FPGA development board
A FPGA board was used in this first version design to drive VGA output
display signal. In next version, such development board should be eliminated. If
possible, the microcontroller should directly drive the output VGA signal. Such
elimination will decrease the complexity of the project and reduce the possible
failure during communication. However, such action will significantly increase the
software complexity of the microcontroller. The microcontroller will require more
cycle and recourses to perform a sample-calculate-display process.
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If such compromise cannot be make, the FPGA development board should
be eliminated and a Spartan-3E FPGA chip should be placed directly on board.
11.4 Improvement in enclosure manufacturing
The aluminum enclosure was cut and drill with nibbler and drill bits. The
large octagon opening was directed by drill holes and cut by dremel tool. Such
approach is more cost efficient and less time consuming in first prototype.
However, more accurate hole positions and better appearance of the enclosure will
be desirable in next version. A CNC machine or water jet cutter will be suitable for
such requirement.
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ECE 477 Final Report
Spring 2012
12.0 Summary and Conclusions
The Awesillo-Scope provides basic functions of a typical oscilloscope, such as
displaying voltage waveform, scale setting, cursor setting, reconstruction and visualization
of signals. Additional features such as recording and replicating signals as a function
generator is integrated in this project. A PCB was designed and the circuit was constructed
by hand soldering. The mechanical construction of the product was done by band saw,
drill bit, nibbler, dremel tool, and hand screw and assemble. A microcontroller is the
major logic component in this project. A MCU application was developed to controls the
front end analog circuit, sample the analog signal, provide user interface, calculate and
process sampled data points, and finally transmit display data. A FGPA development
board was plugged on the PCB. The development board receives display data from MCU,
and generate VGA signal on the VGA output channel.
In this project, we learn the general process of designing and prototyping an electrical
engineering product, as well as how to cooperate as hardware and software specialists.
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ECE 477 Final Report
Spring 2012
13.0 References
[1] STMicroelectronics, “ARM Cortex-M4 32b MCU+FPU,” STM32F405xx/STM32F407xx
datasheet, Sep. 2011 [Revised Jan. 2012].
[2] STMicroelectronics (2011). RM0090 Reference Manual, STM32F405xx, STM32F407xx,
STM32F415xx and STM32F417xx advanced ARM-based 32-bit MCUs [Online],
Available on:
http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATU
RE/REFERENCE_MANUAL/DM00031020.pdf Retrieved Mar. 21st, 2012
[3] STMicroelectronics (2011). Application Notes [Online], Available on:
http://www.st.com/internet/mcu/product/252140.jsp, Design Support tab. Retrieved Jan.
17th, 2012
[4] Xilinx, “Spartan-3E FPGA Family,” XC3S500E-4FG320C datasheet, Mar. 2005 [Revised
Mar. 2005].
[5] Maxim, “100kΩ Precision-Matched Resistor-Divider in SOT23,” MAX5490 datasheet,
Mar. 2005 [Revised Mar. 2005].
[6] National Semiconductor, “Low Distortion Op Amp with Shutdown,” LMH6703 datasheet,
May. 2005 [Revised May. 2005].
[7] National Semiconductor, “Low Distortion Op Amp with Shutdown,” LMH6703 datasheet,
May. 2005 [Revised May. 2005].
[8] Liner Technology, “High Efficiency Step-Down and Inverting DC/DC Converter,”
LTC1174-3.3/LTC1174-5 datasheet, 1994.
[9] [Website]. : Digikey “http://www.digikey.com” [Accessed Feb. 2nd, 2012]
[10] Panasonic, “Coil type EMI Filters,” ELK-E333FA datasheet, Sep. 2010.
[11] DSO nano v2 manual v9.01B [Online], May. 2011. Available:
http://www.seeedstudio.com/depot/datasheet/DSO%20Nano%20v2%20Manual.pdf
[Accessed: Feb 7, 2012].
[12] Prof. Dr. –Ing. K. –D. Kammeyer [Online], April. 2010. Available: http://www.ant.unibremen.de/whomes/rinas/agiload/ [Accessed: Feb 7, 2012].
-40-
ECE 477 Final Report
Spring 2012
[13] MetricTest, Agilent 54621A 60MHz 2CH 200MSa/s Oscilloscope [Online], 2010.
Available: http://www.metrictest.com/product_info.jsp?mfgmdl=HP%2054621A(N)
[Accessed: Feb 7, 2012].
[14] Maxim, “+3.3V/+5V, 8-Channel Relay Drivers with Fast Recovery Time and Power-Save
Mode,” MAX4822/4824 datasheet, 2005 [Revised Aug. 2005].
[15] BURR-BROWN, “Precision, Low Power INSTRUMENTATION AMPLIFIER” LMH6703
datasheet, May. 2005 [Revised Apr. 2009].
[16] Intel Corporation, “ATX Specification”, ATX developer specification, [Version 2.2],
available http://www.formfactors.org/developer/specs/atx2_2.pdf
[17] Trace width calculator, retrieved from
http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/, accessed
Feb. 23rd, 2012,
[18] PCB manufacture specification, retrieved from
http://4pcb.com/index.php?load=content&page_id=130, accessed on Feb. 23rd , 2012.
[19] PCB layout guidline, retrieved from:
https://engineering.purdue.edu/ece477/Homework/CommonRefs/Tutorials/PCB/PCB%20D
esign%20Specifications.pdf, accessed on Feb. 22nd ,2012.
[20] System Design and Layout Techniques for Noise Reduction in MCU- Based Systems. By
Mark Glenewinkel. CSIC Applications. Austin, Texas, retrieved from:
https://engineering.purdue.edu/ece477/Homework/CommonRefs/AN1259.pdf, accessed on
Feb 22nd, 2012.
[21] Odenheimer, R.P., Hastings, K., “Self Adjusting Oscilloscope” U.S. Patent 4743844,
December 19, 1986.
[22] Freidhof, M., Huber, J., “Method and system for secure digital triggering for an
oscilloscope” U.S. Patent 7860674, April 24, 2006.
[23] Moriyasu, H., Gilmore, J.A., Velsink, W.B., Havarro, L.J, “Oscilloscope system for
acquiring, processing, and displaying information” U.S. Patent 4225940, October 2, 1978.
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ECE 477 Final Report
Spring 2012
[24] Engineering Education Reform: A Trilogy, Frank G. Splittz, Jan. 2003 Retrieved from
https://engineering.purdue.edu/ece477/Homework/CommonRefs/enviro_refs.pdf, accessed
Apr. 10th, 2012
[25] Analog, RF and EMC Considerations, James Colotti, Telephonics - Command Systems
Division, Copyright Telephonics 2002-2005, revision 4a, retrieved from
http://www.ieee.li/pdf/viewgraphs_pwb_design.pdf, accessed Apr. 12th, 2012
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ECE 477 Final Report
Appendix A:
Spring 2012
Individual Contributions
A.1 Contributions of Bo Yuan:
I mainly work on the MCU. I used the initialized template from ST library
to start my work. The MCU code has three parts, sampling interface, user interface,
and communication interface. Finally, I have all the MCU code successfully working.
The sampling interface includes the timer and the ADCs. The timer is
initialized with the highest prescalar. In order to adjust the sampling rate, I am using a
time base configuration. Time base configuration will check for interrupt counter with
a certain CCR value. If the CCR value is not reached at the time interrupted, the
counter will just be incremented and the data will not be sampled. To make sure the
data is sampled continuously and smoothly, the priority of the sampling timer is set to
be the highest in the nested vector, so other interrupts will not be able to interrupt
sampling process, but sampling interrupt can interrupt other interrupt. The data will be
converted from ADC. ADC is set to be running at 1.2 MHz 12bit resolution. The
DMA mode will take the value on DR (data register) and send to the pre-set address.
The converted ADC value will be tested by a trigger function. The trigger function
takes several data and keeps track of the trend of the data. More data than displayed
will be sampled to meet the requirement of some other calculations. After all sampling
process finished, a flag will be set.
The communication interface is using SPI. In this project, since the
communication is one direction communication, I only set up MOSI, SCLK, and NSS.
The SPI is running at 5M Hz. After the sampling finished flag been set, the user
interface will start to send data to the FPGA. I turned on DMA mode so the SPI can
send data directly from the internal memory. The SPI is using same DMA stream as
ADCs but different channels. The SPI is also set to have the highest priority. The
transmission from MCU to FPGA contains 480*2 bytes of sampled data and other
information of the user interface. During the transmission, the sampling process will
be temporarily paused.
The user interface generally controls top level operations. The digital
multiplexer is selected by GPIO outputs. There are in total three digital multiplexers.
Two multiplexers are for ADC input attenuation, which will convert -12V to 12V to
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ECE 477 Final Report
Spring 2012
0V to 3V, and the other one is for DAC output, which will convert 0V to 3V output to
-12V to 12V. I use another timer to check for pushbuttons’ input and RPGs. The timer
will check for falling edge of the pushbutton GPIO signals and track first three initial
states of the RPG. The other functions such as peak-to-peak voltage and cursors are
also implemented in the user interface.
Looking at the MCU code from other perspective, all the codes are
APB&AHB clocks, GPIO and alternative pin function initializations, timer settings,
IRQ interrupt handler, NVIC priorities, and DMA modes. APB&AHB clocks are for
the pin internal clocks. GPIO and alternative pin functions include all the possible use
of pins. NVIC determines the priority of interrupts. DMA takes care of memory to
peripheral or peripheral to memory transmissions. All the possible applications of the
code can be concluded as the combination of these set-ups.
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ECE 477 Final Report
Spring 2012
A.2 Contributions of Yimin Xiao:
I am majorly in charge of the hardware side of the project. I design and
construct the circuit and mechanical parts of the project. Then finally the whole
product was assembled.
First, I layout the analog circuit between the input channels and the
microcontroller ATD pins. The analog scaling must be done in this part of circuit, so I
select the buffer, analog multiplexer, and precision amplifier components. Then
microcontroller circuit and FPGA circuit were designed with required decoupling
capacitors. Then user interface was added, including the push buttons and RPGs, a
VGA connector, and a USB connector. Based on the components required, a power
supply system was designed with an ATX computer power supply unit and linear
regulators.
Base on the schematic, I layout the PCB with extra concern in analog and
sampling circuit, since the whole project is about sampling user inputted analog signal
sampling, maximizing the accuracy and sampling frequency is one of the largest
concern in this project. Then the gerber files were generated, DFM test was run and all
minor problems were fixed. Then the PCB order was placed.
When the PCB came in, initial check was performed. Later I cut the board
into two pieces with band saw and sanded the edge to make nice rectangular boards,
since I place two boards on one file to reduce PCB manufactory cost. Then the power
supply circuit was soldered and external ATX power supply unit was plugged into the
board. After the power supply circuit is verified fully functioning, analog circuit
followed by microcontroller circuit were soldered onto the PCB. After soldering major
parts on PCB, headers and connecters (i.e. the taller and bigger parts) were soldered to
the PCB. Then I tested the PCB after finished all soldering.
On mechanical part, after the PCB is verified, I started with sketching drill
positions of screws holes on the rectangular aluminum enclosure. Then one by one, the
BNC , VGA, USB connector’s open was labeled, cut or drilled by nibbler or drill bit.
Then the ATX power supply unit was opened and the circuit was token out from the
ATX enclosure. Opening for wall plug wire and 110/220V selector was cut by nibbler.
Finally the fan opening was cut by dremel tool. The dremel tool cutting path was
A-3
ECE 477 Final Report
Spring 2012
guided by drill holes on the sketched edges. Fan out openings were designed to be on
the right of the enclosure and was drilled out by 3/8 inch drill bit. Then the fan was
installed on the fan opening.
After all parts are installed, I test run all the hardware circuit and verified
the hardware, including the power supply, PCB, FPGA module, VGA and USB
connection, BNC input.
During software developing process, I helped my teammate on jump wires,
soldering headers and connectors for development boards, adjusting potentiometers to
calibrate the analog sampling and DTA output range.
Finally after the teammate finish developed software part of the project, I
closed the cover of the enclosure and the product is ready for use.
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ECE 477 Final Report
Spring 2012
A.3 Contributions of Yang Yang:
I'm majorly in charge of the FPGA display unit of our project, specifically
utilizing VGA to display and digitally reconstruct sampled signal. I was able to
generate VGA control signals: vertical sync, horizontal sync as well as RGB signals
for VGA to achieve a 480*640 resolution at 60Hz refresh rate. I was also able to
display characters and create a simple oscilloscope menu for the user to view. For
character display, I created a font library file which includes 8*8 pixel displays of
simple letters and numbers.
In order to display a dynamic waveform of the signal, a SPI interface was
used to receive sampled and preprocessed data from MCU. After simple conversion(to
make the data format suitable for VGA display), data ready for display is stored into a
FIFO which later will be read as the VGA scans through the whole screen. Since the
FPGA will be always receiving exactly 480 points from the MCU for display, I made
the VGA display area for waveform to be 480*480. After receiving horizontal sync,
VGA will start scanning from pixel row 0 and pixel column 0 (the top left of the
monitor screen). After finishes the first row, it will receive a new horizontal sync
which indicates the start of scanning the next row. After VGA finishes scanning the
whole screen, it will wait for the vertical sync which indicates the start of scanning the
whole screen. Therefore, the algorithm I came up with for waveform display is that as
the VGA scans, the pixel column will be used as the address for us to fetch data from
the FIFO. The data read from FIFO will be the “voltage of the signal” which
corresponds to the pixel row at that specific pixel column (480 pixel column
corresponds to 480 data points) that should be “light up”. The program will compare
the data read from FIFO with the current pixel row and light up the ones that have the
same value. I was initially going to use SRAM instead of FIFO for storage of data and
I have written the SRAM controller code to interface with SRAM. However, I was
doing all the testing on the FPGA development board and I realized that we didn't
solder the SRAM to our PCB. Therefore, I switched to use FIFO for storage instead.
In the case of communication between MCU and FPGA, I initially decided to
use I2C interface and FPGA will act as a slave device. I modified Jintao's I2C slave
code from ECE 337 but was not able to successfully communicate with MCU. I
A-5
ECE 477 Final Report
Spring 2012
worked with Jintao to debug the code and we both thought that it was because the
SDA signal was utilized as input and output signal and the FPGA can not drive SDA
signal low without external circuitry. Therefore, I decided to use SPI for
communication instead. The FPGA will still act as a slave device and since the FPGA
clock is faster than MCU master clock, a rising clock edge detection mechanism was
implemented. At each rising clock edge of the MCU master clock, one bit will be
transmitted. The FPGA SPI slave code is essentially a shift register which shifts in one
bit at a time and assert a data ready signal after one byte has been received.
Besides the coding on FPGA, I also assisted the team in doing constraints
analysis, parts selection, soldering, PCB and final package design. I finished the
assigned professional and design component report and participated in relevant TCSP
sessions.
A-6
ECE 477 Final Report
Spring 2012
A.4 Contributions of Jintao Zhang:
My contributions to the project are relatively diverse compare to other
teammates. By utilizing my previous knowledge from coursework and newly learned
skills throughout the project, I worked on hardware selection (including MCU and
miscellaneous components), PCB soldering, embedded C programming (DAC part),
and FPGA (communication portion).
At the beginning of the project, I mainly worked on parts searching and circuit
design with Yimin. AWESILLOSCOPE require multiple circuit selection mechanism
and operation amplifier, thus I did lots of research on analog multiplexer, relay driver,
and op-amps. During this part my biggest contribution is determine that we use analog
multiplexer as front-end circuit selection, which will both satisfy our power
consumption needs (only few mA of current is required) and can conveniently select 1
of the 8 channels by 3 MCU output signals. I also complete the resistance calculation
for the front end of the circuit in order to attenuate the input signal with a proper ratio
after the PCB is fabricated so that our input signal can be attenuated to a proper value
with the control of MCU.
On the software side, I worked on the DAC channel initialization and allow our
product to output the proper sampled signal from the third BNC port. Since Bo is
majorly worked on the C code skeleton and libraries, my part of the code should not
be a set of “stand alone” code; instead, it should be able to insert in the skeleton file
Bo created. So I programmed two functions for DAC, one is to allowed the other
portion of the program change the DAC interrupt frequency, thus to change the output
signal frequency; the other one is to output a signal data array based on input starting
address. So the code is compatible for our main skeleton file.
I also worked on the FPGA code, majorly the communication interface between
MCU and FPGA. I altered my I2C code from ECE 337 so that it is compatible for out
transmission. Soon after we discover our hardware flaw on I2C, I programmed the SPI
slave interface and quickly establish our communication protocol. Additionally, I
write several MATLAB function to generate VHDL test code for our FPGA in order
to do the hardware testing.
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ECE 477 Final Report
Spring 2012
Other than the technical contribution, I worked on software narrative and safety
analysis report. I did lots of research to identify the possible failure and the proper
ways to resolve them if possible. Additionally I contribute to finalize the senior design
report and keep the “Photo” and “Link” part of the website updated.
A-8
ECE 477 Final Report
Appendix B:
Spring 2012
Packaging
Figure B-1. Over view of product packaging
Figure B-2. Front panel-left
B-1
ECE 477 Final Report
Spring 2012
Figure B-3. Front panel-right
Figure B-4. Side view of product packaging
B-2
ECE 477 Final Report
Appendix C:
Spring 2012
Schematic
Figure C-1. Power Supply Circuit
C-1
ECE 477 Final Report
Spring 2012
Figure C-2. Analog Front End Circuit
C-2
ECE 477 Final Report
Spring 2012
Figure C-3. MCU Circuit
C-3
ECE 477 Final Report
Spring 2012
Figure C-4. FPGA Circuit
C-4
ECE 477 Final Report
Spring 2012
Figure C-5. User Interface Circuit
C-5
ECE 477 Final Report
Appendix D:
Spring 2012
PCB Layout Top and Bottom Copper
Figure D-1. Bottom Copper of PCB
D-1
ECE 477 Final Report
Spring 2012
Figure D-1. Top Copper of PCB.
D-2
ECE 477 Final Report
Appendix E:
Spring 2012
Parts List Spreadsheet
Catalog #
KA7805ETU-ND
497-1472-5-ND
296-21633-5-ND
AD1583BRTZ-REEL7CT-ND
296-12846-5-ND
XG8T-1431-ND
INA118U-ND
Part #
KA7805ETU
L7905CV
UA78M33CKCS
AD1583BRTZ-REEL7
LF411CD
XG8T-1431
INA118U
987-1398-ND
A35116-ND
A97561-ND
MM5Z3V0CT-ND
STM32F407VGT6
EN11-HSM1BF20
1-1734530-1
1-1634624-0
MM5Z3V0
STM32F407VGT6
NX3225SA26.000000MHZ
Spartan 3-E FPGA
Module
EXC-3BB102H
RR1220P-4023-D-M
RR1220P-914-D
RR1220P-104-D
TPSA225K010R1800
GRM21BF51A106ZE15L
MAX147520
POT100K_3362U
644-1054-1-ND
P10190CT-ND
RR12P402KDCT-ND
RR12P910KDCT-ND
RR12P100KDCT-ND
478-1753-1-ND
490-3332-1-ND
Item Description
IC REG POS 5V 1.0A 4% TOL TO-220
IC REG NEG VOLT 5V TO-220
IC POS-V REG 500MA 3.3V TO220-3
IC VREF SERIES PREC 3V SOT-23-3
IC OPAMP JFET 3MHZ SGL HS 8SOIC
JUMPER PLUG 14POS DOUBLE ROW
IC OPAMP INSTR 800KHZ SGL 8SOIC
ENCODER 11MM ROTARY SW TOP
ADJ
CONN HD D-SUB RCPT R/A 15POS
CONN SOCKET BNC R/A 75 OHM PCB
DIODE ZENER 3V 200MW SOD-523F
STM32 ARM Cortex-M4 MCU
UNIT
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
5
3
5
10
3
1.58
1.96
2.83
0.327
0
7.9
5.88
14.15
3.27
0
CRYSTAL 26.000000 MHZ 8PF SMD
PCS
10
0.92
9.2
Spartan 3E Development Board
BEAD CORE 50MA 0603 SMD
RES 402K OHM 1/10W .5% 0805 SMD
RES 910K OHM 1/10W .5% 0805 SMD
RES 100K OHM 1/10W .5% 0805 SMD
CAP TANT 2.2UF 10V 10% 1206
CAP CER 10UF 10V Y5V 0805
Analog multiplexer
potentiometer
USB Connector
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
PCS
1
10
10
10
50
3
25
5
5
1
0
0.085
0.102
0.102
0.0624
0.94
0.092
0
0
0
0
0.85
1.02
1.02
3.12
2.82
2.3
0
0
0
145.76
E-1
QUAN
3
3
3
3
6
10
5
UNIT Cost
Total Cost
0.68
2.04
0.65
1.95
0.6
1.8
2.5
7.5
1.64
9.84
0.73
7.3
12.76
63.8
ECE 477 Final Report
Appendix F:
Spring 2012
FMECA Worksheet
Table F-1: General Circuit FMECA Table
Failure
Failure Mode
No.
A1
Power traces on
PCB over current
and got burn.
Possible Causes
Failure Effects
Wrong layout of
power supply
connector.
One backup 5V
trace burn out.
Method of
Detection
See smoke.
Criticality
Remarks
High
Power supply connector
cut and plugged in each
pin individually.
A2
3.3V rail = 0V
Linear regulator is
not functioning
Debugger cannot
communicate
with MCU since
it is not powered.
With multimeter.
Low
Change new linear
regulator.
A3
VGA signal is
distorted on PCB.
Do not know.
Cannot generator
VGA display with
the same map-file
on development
board.
With
oscilloscope
and external
monitor.
Low
A4
VRef rail = 0V.
Missing voltage
reference component
Sampling on
microcontroller
not working.
Reads FF on
any input on
MCU ATD
channel.
Low
By touching the board,
the PCB sometimes
give the right signal.
Found out which two
pins are shorted by
hand and fly wire.
Problem solved but
cause still not clear.
Voltage reference chip
was soldered back to
the board.
F-2
ECE 477 Final Report
Spring 2012
Table F-2: Microcontroller FMECA Table
Failure
Failure Mode
No.
B1
I2C interface is
not working.
Possible Causes
FPGA doesn’t
support open drain
mode operation.
Failure Effects
Method of
Detection
Cannot send ACK With
bit back to MCU
oscilloscope
Criticality
Remarks
Medium
Invest other
communication
interface. Decided to
use SPI.
B2
SPI bus cannot
synchronize byte
start condition
FPGA receive data
with random bit shift
error
Read same
pattern but error
data.
With external
display
generated by
FPGA
Low
Use a chip selection pin
to synchronize the start
of byte transmission.
B3
Development
board ATD
channel not
working
Over voltage feed to
ATD pin on
development board
The board’s
sampling function
no longer works.
Observation
Medium
Purchase new
development board.
B4
Fail to communicate
Internal flags cannot be
Can’t use I2C to
Same starting
Low
Change to SPI2 to
with FPGA though
cleared if don’t get a
send data
condition been
I2C
ACK back
sent. Being
observed on
oscilloscope.
F-3
communicate.
ECE 477 Final Report
Spring 2012
Table F-3: FPGA FMECA Table
Failure
Failure Mode
Possible Causes
Failure Effects
No.
C1
Method of
Criticality
Remarks
Detection
Fail to achieve
Incorrect VGA clock
Can’t display
Observe VGA
desired resolution
input. Incorrect “vsync”
640*480 resolution
pixel column less
and “hsync”
Low
Recalculate timing for
640*480 resolution at 60Hz
than 640 and pixel
row less than 480
C2
Fail to display
No “storage” for data.
No display. Failure
No output being
waveform
Data can’t be hold
to generate output
observed on
hold all 480 data such as
monitor
utilizing SRAM
before VGA scans to the
Medium
Implement a storage unit to
pixel coordinates that
needs to be “light up”
C3
Fail to interface with
SRAM is not being
Can’t use SRAM to
No output being
SRAM when tested
soldered on our PCB (on
store data
observed on
on PCB
the development board
monitor. Observe
instead)
SRAM unit is on
development
board
F-4
Low
Implement a FIFO to store
data instead of SRAM