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Number One
Tom Bozic
Ian Nuber
Greg Ramsey
Henry Romero
Matt Unangst
GITHU Processor
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General Purpose 32-bit, pipelined computer
processor
MIPS-like architecture
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24-bit address space
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Reduced instruction set
22 bits, concatenate with ending 00
32 bit boundaries
16 Registers
Registers
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16 Registers (ease in immediate operations)
3 Special Purpose
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R0 – zero
R14 – stack pointer
R15 – return address
Instruction Set Architecture
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First two bits indicate instruction category
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16 bit immediate built into R-type reduces complexity
of design
Addressing Modes
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Load, store, bra/jump, R-type
Direct
Indirect with Offset
ISA accounts for full address space
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NO PC-relative addressing
Instruction Format
Load / Store
31 30 29
Op(2)
24 23
Addr(6)
20 19
Rt (4)
16 15
Rs (4)
0
Address Displacement (16)
R-Type
31
24 23
Opcode(8)
20 19
Rd(4)
16 15
Rs1 (4)
12 11
Rs2 (4)
0
Immediate (12)
Bra / Jmp
31 30 29
Op(2)
26 25
Type(4)
24 23
Addr (2)
20 19
Rs (4)
0
Address Continued (20)
Instructions
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Arithmetic
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Add
Addi – add immediate
Sub
Subi – subtract immediate
Data Transfer
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Ld - load word
St – store word
Instructions
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Logic
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And
Andi – And immediate
Or
Ori – Or immediate
Nor
Nand
Sll – logic shift left
Slr – logic shift right
Instructions
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Branches
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Beq – branch equal to zero
Bne – branch not equal to zero
Jumps
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Jmp – jump to specified address
Jsr – jump to subroutine
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Interrupt handler
Save current PC in register
Nop – No Operation
Datapath Diagram
Functional Units
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Register File
ALU
Control Logic
Memory System
Assembler
Hardware
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Xilinx XCV300/400/600/800 FPGA
Keep FPGA on board
Make PCB for all off-chip peripherals
Connect two boards together via ribbon
cable
Processor I/O
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Serial RS232 port
LCD, Monitor outputs
Keypad, Keyboard Inputs
Vital Goals
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Implement processor on FPGA in Verilog
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Pipelined
Thorough simulation
Complete Assembler
Keypad, LCD I/O
Make PCB with off-chip peripherals
Successfully run assembly program
Extended Goals
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On-chip caches (Instruction and data)
C Compiler
Monitor, Keyboard I/O
Multiplier, Divider units
Floating Point Units
Individuals Roles
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Tom Bozic
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
Ian Nuber
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ALU, PCB design
Henry Romero
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Assembler, control logic, test-program design
Greg Ramsey
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Assembler, control logic, documentation
PCB design, Memory system
Matt Unangst
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Pipeline implementation (forwarding, rollback)
Register File
Schedule
Risks
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PCB issues (signal noise, speed, etc)
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Wire wrapping
Pipeline complexity
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Design allows for insertion of no-ops to essentially
turn machine into multi-cycle machine
Questions?